1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 395 unchanged lines hidden (view full) --- 404 } 405 406 uint32_t int_id; 407 408 if (hppiCanPreempt()) { 409 int_id = getHPPIR0(); 410 411 // avoid activation for special interrupts |
412 if (int_id < Gicv3::INTID_SECURE || 413 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { |
414 activateIRQ(int_id, hppi.group); 415 } 416 } else { 417 int_id = Gicv3::INTID_SPURIOUS; 418 } 419 420 value = int_id; 421 break; --- 38 unchanged lines hidden (view full) --- 460 } 461 462 uint32_t int_id; 463 464 if (hppiCanPreempt()) { 465 int_id = getHPPIR1(); 466 467 // avoid activation for special interrupts |
468 if (int_id < Gicv3::INTID_SECURE || 469 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { |
470 activateIRQ(int_id, hppi.group); 471 } 472 } else { 473 int_id = Gicv3::INTID_SPURIOUS; 474 } 475 476 value = int_id; 477 break; --- 297 unchanged lines hidden (view full) --- 775 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 776 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 777 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 778 } 779 780 int int_id = val & 0xffffff; 781 782 // avoid activation for special interrupts |
783 if (int_id >= Gicv3::INTID_SECURE && 784 int_id <= Gicv3::INTID_SPURIOUS) { |
785 return; 786 } 787 788 Gicv3::GroupId group = Gicv3::G0S; 789 790 if (highestActiveGroup() != group) { 791 return; 792 } --- 52 unchanged lines hidden (view full) --- 845 case MISCREG_ICC_EOIR1_EL1: { 846 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 847 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 848 } 849 850 int int_id = val & 0xffffff; 851 852 // avoid deactivation for special interrupts |
853 if (int_id >= Gicv3::INTID_SECURE && 854 int_id <= Gicv3::INTID_SPURIOUS) { |
855 return; 856 } 857 858 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 859 860 if (highestActiveGroup() == Gicv3::G0S) { 861 return; 862 } --- 906 unchanged lines hidden (view full) --- 1769 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1770 // SGI or PPI, redistributor 1771 redistributor->activateIRQ(int_id); 1772 redistributor->updateAndInformCPUInterface(); 1773 } else if (int_id < Gicv3::INTID_SECURE) { 1774 // SPI, distributor 1775 distributor->activateIRQ(int_id); 1776 distributor->updateAndInformCPUInterfaces(); |
1777 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 1778 // LPI, Redistributor 1779 redistributor->setClrLPI(int_id, false); |
1780 } 1781} 1782 1783void 1784Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1785{ 1786 // Update active priority registers. 1787 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + --- 20 unchanged lines hidden (view full) --- 1808 // SGI or PPI, redistributor 1809 redistributor->deactivateIRQ(int_id); 1810 redistributor->updateAndInformCPUInterface(); 1811 } else if (int_id < Gicv3::INTID_SECURE) { 1812 // SPI, distributor 1813 distributor->deactivateIRQ(int_id); 1814 distributor->updateAndInformCPUInterfaces(); 1815 } else { |
1816 // LPI, redistributor, shouldn't deactivate 1817 redistributor->updateAndInformCPUInterface(); |
1818 } 1819} 1820 1821void 1822Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 1823{ 1824 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1825 lr_idx); --- 641 unchanged lines hidden --- |