131c131
< break;
---
> return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
743c743,744
< break;
---
> setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
> return;
1722,1726c1723
< int apr_misc_reg;
< RegVal apr;
< apr_misc_reg = group == Gicv3::G0S ?
< MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
< apr = isa->readMiscRegNoEffect(apr_misc_reg);
---
> int apr_misc_reg = 0;
1727a1725,1740
> switch (group) {
> case Gicv3::G0S:
> apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
> break;
> case Gicv3::G1S:
> apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
> break;
> case Gicv3::G1NS:
> apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
> break;
> default:
> panic("Invalid Gicv3::GroupId");
> }
>
> RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
>
1817,1818c1830,1845
< int apr_idx = group == Gicv3::G0S ?
< MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
---
>
> int apr_idx = 0;
> switch (group) {
> case Gicv3::G0S:
> apr_idx = MISCREG_ICC_AP0R0_EL1;
> break;
> case Gicv3::G1S:
> apr_idx = MISCREG_ICC_AP1R0_EL1_S;
> break;
> case Gicv3::G1NS:
> apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
> break;
> default:
> panic("Invalid Gicv3::GroupId");
> }
>