677a678,689
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP0R1:
> case MISCREG_ICH_AP0R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R2:
> case MISCREG_ICH_AP0R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R3:
> case MISCREG_ICH_AP0R3_EL2:
> // Unimplemented registers are RAZ/WI
> return 0;
>
682a695,706
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP1R1:
> case MISCREG_ICH_AP1R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R2:
> case MISCREG_ICH_AP1R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R3:
> case MISCREG_ICH_AP1R3_EL2:
> // Unimplemented registers are RAZ/WI
> return 0;
>
1617,1618c1641,1656
< case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
< case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
---
> case MISCREG_ICH_AP0R0:
> case MISCREG_ICH_AP0R0_EL2:
> break;
>
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP0R1:
> case MISCREG_ICH_AP0R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R2:
> case MISCREG_ICH_AP0R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R3:
> case MISCREG_ICH_AP0R3_EL2:
> // Unimplemented registers are RAZ/WI
> return;
>
1620,1621c1658,1659
< case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
< case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
---
> case MISCREG_ICH_AP1R0:
> case MISCREG_ICH_AP1R0_EL2:
1623a1662,1673
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP1R1:
> case MISCREG_ICH_AP1R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R2:
> case MISCREG_ICH_AP1R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R3:
> case MISCREG_ICH_AP1R3_EL2:
> // Unimplemented registers are RAZ/WI
> return;
>
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP0R1:
> case MISCREG_ICH_AP0R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R2:
> case MISCREG_ICH_AP0R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R3:
> case MISCREG_ICH_AP0R3_EL2:
> // Unimplemented registers are RAZ/WI
> return 0;
>
682a695,706
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP1R1:
> case MISCREG_ICH_AP1R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R2:
> case MISCREG_ICH_AP1R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R3:
> case MISCREG_ICH_AP1R3_EL2:
> // Unimplemented registers are RAZ/WI
> return 0;
>
1617,1618c1641,1656
< case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
< case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
---
> case MISCREG_ICH_AP0R0:
> case MISCREG_ICH_AP0R0_EL2:
> break;
>
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP0R1:
> case MISCREG_ICH_AP0R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R2:
> case MISCREG_ICH_AP0R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP0R3:
> case MISCREG_ICH_AP0R3_EL2:
> // Unimplemented registers are RAZ/WI
> return;
>
1620,1621c1658,1659
< case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
< case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
---
> case MISCREG_ICH_AP1R0:
> case MISCREG_ICH_AP1R0_EL2:
1623a1662,1673
> // only implemented if supporting 6 or more bits of priority
> case MISCREG_ICH_AP1R1:
> case MISCREG_ICH_AP1R1_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R2:
> case MISCREG_ICH_AP1R2_EL2:
> // only implemented if supporting 7 or more bits of priority
> case MISCREG_ICH_AP1R3:
> case MISCREG_ICH_AP1R3_EL2:
> // Unimplemented registers are RAZ/WI
> return;
>