162c162
< return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
---
> return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
167a168,174
> case MISCREG_ICV_IGRPEN0_EL1: {
> ICH_VMCR_EL2 ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> value = ich_vmcr_el2.VENG0;
> break;
> }
>
172c179
< return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
---
> return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
177a185,191
> case MISCREG_ICV_IGRPEN1_EL1: {
> ICH_VMCR_EL2 ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> value = ich_vmcr_el2.VENG1;
> break;
> }
>
383c397
< return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
---
> return readMiscReg(MISCREG_ICV_PMR_EL1);
403a418,425
> case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
> ICH_VMCR_EL2 ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
>
> value = ich_vmcr_el2.VPMR;
> break;
> }
>
1276c1298
< return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
---
> return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1305a1328,1337
> case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
> ICH_VMCR_EL2 ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> ich_vmcr_el2.VPMR = val & 0xff;
>
> isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
> virtualUpdate();
> return;
> }
>