391c391
< return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
---
> return readMiscReg(MISCREG_ICV_PMR_EL1);
408a409,416
> case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
> RegVal ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
>
> value = ich_vmcr_el2 >> ICH_VMCR_EL2_VPMR_SHIFT;
> break;
> }
>
1271c1279
< return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
---
> return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1297a1306,1318
> case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
> RegVal ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> ich_vmcr_el2 = insertBits(
> ich_vmcr_el2,
> ICH_VMCR_EL2_VPMR_SHIFT + ICH_VMCR_EL2_VPMR_LENGTH - 1,
> ICH_VMCR_EL2_VPMR_SHIFT, val);
>
> isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
> virtualUpdate();
> return;
> }
>