154c154
< return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
---
> return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
159a160,166
> case MISCREG_ICV_IGRPEN0_EL1: {
> RegVal ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG0_SHIFT);
> break;
> }
>
163c170
< return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
---
> return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
168a176,182
> case MISCREG_ICV_IGRPEN1_EL1: {
> RegVal ich_vmcr_el2 =
> isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
> value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG1_SHIFT);
> break;
> }
>