1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#include "dev/arm/gic_v3_cpu_interface.hh"
44
45#include "arch/arm/isa.hh"
46#include "debug/GIC.hh"
47#include "dev/arm/gic_v3.hh"
48#include "dev/arm/gic_v3_distributor.hh"
49#include "dev/arm/gic_v3_redistributor.hh"
50
51const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
52const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
53
54Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
55 : BaseISADevice(),
56 gic(gic),
57 redistributor(nullptr),
58 distributor(nullptr),
59 cpuId(cpu_id)
60{
61}
62
63void
64Gicv3CPUInterface::init()
65{
66 redistributor = gic->getRedistributor(cpuId);
67 distributor = gic->getDistributor();
68}
69
70void
71Gicv3CPUInterface::initState()
72{
73 reset();
74}
75
76void
77Gicv3CPUInterface::reset()
78{
79 hppi.prio = 0xff;
80}
81
82void
83Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
84{
85 maintenanceInterrupt = gic->params()->maint_int->get(tc);
86}
87
88bool
89Gicv3CPUInterface::getHCREL2FMO() const
90{
91 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
92
93 if (hcr.tge && hcr.e2h) {
94 return false;
95 } else if (hcr.tge) {
96 return true;
97 } else {
98 return hcr.fmo;
99 }
100}
101
102bool
103Gicv3CPUInterface::getHCREL2IMO() const
104{
105 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
106
107 if (hcr.tge && hcr.e2h) {
108 return false;
109 } else if (hcr.tge) {
110 return true;
111 } else {
112 return hcr.imo;
113 }
114}
115
116RegVal
117Gicv3CPUInterface::readMiscReg(int misc_reg)
118{
119 RegVal value = isa->readMiscRegNoEffect(misc_reg);
120 bool hcr_fmo = getHCREL2FMO();
121 bool hcr_imo = getHCREL2IMO();
122
123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
131 return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:
140
141 // only implemented if supporting 7 or more bits of priority
142 case MISCREG_ICC_AP1R3:
143 case MISCREG_ICC_AP1R3_EL1:
144 // only implemented if supporting 7 or more bits of priority
145 return 0;
146
147 // Active Priorities Group 0 Registers
148 case MISCREG_ICC_AP0R0:
149 case MISCREG_ICC_AP0R0_EL1: {
150 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
151 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
152 }
153
154 break;
155 }
156
157 case MISCREG_ICC_AP0R1:
158 case MISCREG_ICC_AP0R1_EL1:
159
160 // only implemented if supporting 6 or more bits of priority
161 case MISCREG_ICC_AP0R2:
162 case MISCREG_ICC_AP0R2_EL1:
163
164 // only implemented if supporting 7 or more bits of priority
165 case MISCREG_ICC_AP0R3:
166 case MISCREG_ICC_AP0R3_EL1:
167 // only implemented if supporting 7 or more bits of priority
168 return 0;
169
170 // Interrupt Group 0 Enable register EL1
171 case MISCREG_ICC_IGRPEN0:
172 case MISCREG_ICC_IGRPEN0_EL1: {
173 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
174 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
175 }
176
177 break;
178 }
179
180 case MISCREG_ICV_IGRPEN0_EL1: {
181 ICH_VMCR_EL2 ich_vmcr_el2 =
182 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
183 value = ich_vmcr_el2.VENG0;
184 break;
185 }
186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
194 value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
195 break;
196 }
197
198 case MISCREG_ICV_IGRPEN1_EL1: {
199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;
203 }
204
205 // Interrupt Group 1 Enable register EL3
206 case MISCREG_ICC_MGRPEN1:
| 1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#include "dev/arm/gic_v3_cpu_interface.hh"
44
45#include "arch/arm/isa.hh"
46#include "debug/GIC.hh"
47#include "dev/arm/gic_v3.hh"
48#include "dev/arm/gic_v3_distributor.hh"
49#include "dev/arm/gic_v3_redistributor.hh"
50
51const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
52const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
53
54Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
55 : BaseISADevice(),
56 gic(gic),
57 redistributor(nullptr),
58 distributor(nullptr),
59 cpuId(cpu_id)
60{
61}
62
63void
64Gicv3CPUInterface::init()
65{
66 redistributor = gic->getRedistributor(cpuId);
67 distributor = gic->getDistributor();
68}
69
70void
71Gicv3CPUInterface::initState()
72{
73 reset();
74}
75
76void
77Gicv3CPUInterface::reset()
78{
79 hppi.prio = 0xff;
80}
81
82void
83Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
84{
85 maintenanceInterrupt = gic->params()->maint_int->get(tc);
86}
87
88bool
89Gicv3CPUInterface::getHCREL2FMO() const
90{
91 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
92
93 if (hcr.tge && hcr.e2h) {
94 return false;
95 } else if (hcr.tge) {
96 return true;
97 } else {
98 return hcr.fmo;
99 }
100}
101
102bool
103Gicv3CPUInterface::getHCREL2IMO() const
104{
105 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
106
107 if (hcr.tge && hcr.e2h) {
108 return false;
109 } else if (hcr.tge) {
110 return true;
111 } else {
112 return hcr.imo;
113 }
114}
115
116RegVal
117Gicv3CPUInterface::readMiscReg(int misc_reg)
118{
119 RegVal value = isa->readMiscRegNoEffect(misc_reg);
120 bool hcr_fmo = getHCREL2FMO();
121 bool hcr_imo = getHCREL2IMO();
122
123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
131 return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:
140
141 // only implemented if supporting 7 or more bits of priority
142 case MISCREG_ICC_AP1R3:
143 case MISCREG_ICC_AP1R3_EL1:
144 // only implemented if supporting 7 or more bits of priority
145 return 0;
146
147 // Active Priorities Group 0 Registers
148 case MISCREG_ICC_AP0R0:
149 case MISCREG_ICC_AP0R0_EL1: {
150 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
151 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
152 }
153
154 break;
155 }
156
157 case MISCREG_ICC_AP0R1:
158 case MISCREG_ICC_AP0R1_EL1:
159
160 // only implemented if supporting 6 or more bits of priority
161 case MISCREG_ICC_AP0R2:
162 case MISCREG_ICC_AP0R2_EL1:
163
164 // only implemented if supporting 7 or more bits of priority
165 case MISCREG_ICC_AP0R3:
166 case MISCREG_ICC_AP0R3_EL1:
167 // only implemented if supporting 7 or more bits of priority
168 return 0;
169
170 // Interrupt Group 0 Enable register EL1
171 case MISCREG_ICC_IGRPEN0:
172 case MISCREG_ICC_IGRPEN0_EL1: {
173 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
174 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
175 }
176
177 break;
178 }
179
180 case MISCREG_ICV_IGRPEN0_EL1: {
181 ICH_VMCR_EL2 ich_vmcr_el2 =
182 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
183 value = ich_vmcr_el2.VENG0;
184 break;
185 }
186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
194 value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
195 break;
196 }
197
198 case MISCREG_ICV_IGRPEN1_EL1: {
199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;
203 }
204
205 // Interrupt Group 1 Enable register EL3
206 case MISCREG_ICC_MGRPEN1:
|
207 case MISCREG_ICC_IGRPEN1_EL3:
| 207 case MISCREG_ICC_IGRPEN1_EL3: {
208 ICC_IGRPEN1_EL3 igrp_el3 = 0;
209 igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
210 MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
211
212 igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
213 MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
214
215 value = igrp_el3;
|
208 break;
| 216 break;
|
| 217 }
|
209
210 // Running Priority Register
211 case MISCREG_ICC_RPR:
212 case MISCREG_ICC_RPR_EL1: {
213 if ((currEL() == EL1) && !inSecureState() &&
214 (hcr_imo || hcr_fmo)) {
215 return readMiscReg(MISCREG_ICV_RPR_EL1);
216 }
217
218 uint8_t rprio = highestActivePriority();
219
220 if (haveEL(EL3) && !inSecureState() &&
221 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
222 // Spec section 4.8.1
223 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
224 if ((rprio & 0x80) == 0) {
225 // If the current priority mask value is in the range of
226 // 0x00-0x7F a read access returns the value 0x0
227 rprio = 0;
228 } else if (rprio != 0xff) {
229 // If the current priority mask value is in the range of
230 // 0x80-0xFF a read access returns the Non-secure read of
231 // the current value
232 rprio = (rprio << 1) & 0xff;
233 }
234 }
235
236 value = rprio;
237 break;
238 }
239
240 // Virtual Running Priority Register
241 case MISCREG_ICV_RPR_EL1: {
242 value = virtualHighestActivePriority();
243 break;
244 }
245
246 // Highest Priority Pending Interrupt Register 0
247 case MISCREG_ICC_HPPIR0:
248 case MISCREG_ICC_HPPIR0_EL1: {
249 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
250 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
251 }
252
253 value = getHPPIR0();
254 break;
255 }
256
257 // Virtual Highest Priority Pending Interrupt Register 0
258 case MISCREG_ICV_HPPIR0_EL1: {
259 value = Gicv3::INTID_SPURIOUS;
260 int lr_idx = getHPPVILR();
261
262 if (lr_idx >= 0) {
263 ICH_LR_EL2 ich_lr_el2 =
264 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
265 Gicv3::GroupId group =
266 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
267
268 if (group == Gicv3::G0S) {
269 value = ich_lr_el2.vINTID;
270 }
271 }
272
273 break;
274 }
275
276 // Highest Priority Pending Interrupt Register 1
277 case MISCREG_ICC_HPPIR1:
278 case MISCREG_ICC_HPPIR1_EL1: {
279 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
280 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
281 }
282
283 value = getHPPIR1();
284 break;
285 }
286
287 // Virtual Highest Priority Pending Interrupt Register 1
288 case MISCREG_ICV_HPPIR1_EL1: {
289 value = Gicv3::INTID_SPURIOUS;
290 int lr_idx = getHPPVILR();
291
292 if (lr_idx >= 0) {
293 ICH_LR_EL2 ich_lr_el2 =
294 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
295 Gicv3::GroupId group =
296 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
297
298 if (group == Gicv3::G1NS) {
299 value = ich_lr_el2.vINTID;
300 }
301 }
302
303 break;
304 }
305
306 // Binary Point Register 0
307 case MISCREG_ICC_BPR0:
308 case MISCREG_ICC_BPR0_EL1: {
309 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
310 return readMiscReg(MISCREG_ICV_BPR0_EL1);
311 }
312
313 value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
314 break;
315 }
316
317 // Binary Point Register 1
318 case MISCREG_ICC_BPR1:
319 case MISCREG_ICC_BPR1_EL1: {
320 value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS);
321 break;
322 }
323
324 // Virtual Binary Point Register 0
325 case MISCREG_ICV_BPR0_EL1: {
326 ICH_VMCR_EL2 ich_vmcr_el2 =
327 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
328
329 value = ich_vmcr_el2.VBPR0;
330 break;
331 }
332
333 // Virtual Binary Point Register 1
334 case MISCREG_ICV_BPR1_EL1: {
335 ICH_VMCR_EL2 ich_vmcr_el2 =
336 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
337
338 if (ich_vmcr_el2.VCBPR) {
339 // bpr0 + 1 saturated to 7, WI
340 value = ich_vmcr_el2.VBPR0 + 1;
341 value = value < 7 ? value : 7;
342 } else {
343 value = ich_vmcr_el2.VBPR1;
344 }
345
346 break;
347 }
348
349 // Interrupt Priority Mask Register
350 case MISCREG_ICC_PMR:
351 case MISCREG_ICC_PMR_EL1:
352 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
353 return readMiscReg(MISCREG_ICV_PMR_EL1);
354 }
355
356 if (haveEL(EL3) && !inSecureState() &&
357 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
358 // Spec section 4.8.1
359 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
360 if ((value & 0x80) == 0) {
361 // If the current priority mask value is in the range of
362 // 0x00-0x7F a read access returns the value 0x00.
363 value = 0;
364 } else if (value != 0xff) {
365 // If the current priority mask value is in the range of
366 // 0x80-0xFF a read access returns the Non-secure read of the
367 // current value.
368 value = (value << 1) & 0xff;
369 }
370 }
371
372 break;
373
374 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
375 ICH_VMCR_EL2 ich_vmcr_el2 =
376 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
377
378 value = ich_vmcr_el2.VPMR;
379 break;
380 }
381
382 // Interrupt Acknowledge Register 0
383 case MISCREG_ICC_IAR0:
384 case MISCREG_ICC_IAR0_EL1: {
385 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
386 return readMiscReg(MISCREG_ICV_IAR0_EL1);
387 }
388
389 uint32_t int_id;
390
391 if (hppiCanPreempt()) {
392 int_id = getHPPIR0();
393
394 // avoid activation for special interrupts
395 if (int_id < Gicv3::INTID_SECURE ||
396 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
397 activateIRQ(int_id, hppi.group);
398 }
399 } else {
400 int_id = Gicv3::INTID_SPURIOUS;
401 }
402
403 value = int_id;
404 break;
405 }
406
407 // Virtual Interrupt Acknowledge Register 0
408 case MISCREG_ICV_IAR0_EL1: {
409 int lr_idx = getHPPVILR();
410 uint32_t int_id = Gicv3::INTID_SPURIOUS;
411
412 if (lr_idx >= 0) {
413 ICH_LR_EL2 ich_lr_el2 =
414 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
415
416 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
417 int_id = ich_lr_el2.vINTID;
418
419 if (int_id < Gicv3::INTID_SECURE ||
420 int_id > Gicv3::INTID_SPURIOUS) {
421 virtualActivateIRQ(lr_idx);
422 } else {
423 // Bogus... Pseudocode says:
424 // - Move from pending to invalid...
425 // - Return de bogus id...
426 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
427 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
428 ich_lr_el2);
429 }
430 }
431 }
432
433 value = int_id;
434 virtualUpdate();
435 break;
436 }
437
438 // Interrupt Acknowledge Register 1
439 case MISCREG_ICC_IAR1:
440 case MISCREG_ICC_IAR1_EL1: {
441 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
442 return readMiscReg(MISCREG_ICV_IAR1_EL1);
443 }
444
445 uint32_t int_id;
446
447 if (hppiCanPreempt()) {
448 int_id = getHPPIR1();
449
450 // avoid activation for special interrupts
451 if (int_id < Gicv3::INTID_SECURE ||
452 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
453 activateIRQ(int_id, hppi.group);
454 }
455 } else {
456 int_id = Gicv3::INTID_SPURIOUS;
457 }
458
459 value = int_id;
460 break;
461 }
462
463 // Virtual Interrupt Acknowledge Register 1
464 case MISCREG_ICV_IAR1_EL1: {
465 int lr_idx = getHPPVILR();
466 uint32_t int_id = Gicv3::INTID_SPURIOUS;
467
468 if (lr_idx >= 0) {
469 ICH_LR_EL2 ich_lr_el2 =
470 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
471
472 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
473 int_id = ich_lr_el2.vINTID;
474
475 if (int_id < Gicv3::INTID_SECURE ||
476 int_id > Gicv3::INTID_SPURIOUS) {
477 virtualActivateIRQ(lr_idx);
478 } else {
479 // Bogus... Pseudocode says:
480 // - Move from pending to invalid...
481 // - Return de bogus id...
482 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
483 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
484 ich_lr_el2);
485 }
486 }
487 }
488
489 value = int_id;
490 virtualUpdate();
491 break;
492 }
493
494 // System Register Enable Register EL1
495 case MISCREG_ICC_SRE:
496 case MISCREG_ICC_SRE_EL1: {
497 /*
498 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
499 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
500 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
501 */
502 ICC_SRE_EL1 icc_sre_el1 = 0;
503 icc_sre_el1.SRE = 1;
504 icc_sre_el1.DIB = 1;
505 icc_sre_el1.DFB = 1;
506 value = icc_sre_el1;
507 break;
508 }
509
510 // System Register Enable Register EL2
511 case MISCREG_ICC_HSRE:
512 case MISCREG_ICC_SRE_EL2: {
513 /*
514 * Enable [3] == 1
515 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
516 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
517 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
518 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
519 */
520 ICC_SRE_EL2 icc_sre_el2 = 0;
521 icc_sre_el2.SRE = 1;
522 icc_sre_el2.DIB = 1;
523 icc_sre_el2.DFB = 1;
524 icc_sre_el2.Enable = 1;
525 value = icc_sre_el2;
526 break;
527 }
528
529 // System Register Enable Register EL3
530 case MISCREG_ICC_MSRE:
531 case MISCREG_ICC_SRE_EL3: {
532 /*
533 * Enable [3] == 1
534 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
535 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
536 * RAO/WI)
537 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
538 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
539 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
540 */
541 ICC_SRE_EL3 icc_sre_el3 = 0;
542 icc_sre_el3.SRE = 1;
543 icc_sre_el3.DIB = 1;
544 icc_sre_el3.DFB = 1;
545 icc_sre_el3.Enable = 1;
546 value = icc_sre_el3;
547 break;
548 }
549
550 // Control Register
551 case MISCREG_ICC_CTLR:
552 case MISCREG_ICC_CTLR_EL1: {
553 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
554 return readMiscReg(MISCREG_ICV_CTLR_EL1);
555 }
556
557 value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
558 // Enforce value for RO bits
559 // ExtRange [19], INTIDs in the range 1024..8191 not supported
560 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
561 // A3V [15], supports non-zero values of the Aff3 field in SGI
562 // generation System registers
563 // SEIS [14], does not support generation of SEIs (deprecated)
564 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
565 // PRIbits [10:8], number of priority bits implemented, minus one
566 ICC_CTLR_EL1 icc_ctlr_el1 = value;
567 icc_ctlr_el1.ExtRange = 0;
568 icc_ctlr_el1.RSS = 1;
569 icc_ctlr_el1.A3V = 1;
570 icc_ctlr_el1.SEIS = 0;
571 icc_ctlr_el1.IDbits = 1;
572 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
573 value = icc_ctlr_el1;
574 break;
575 }
576
577 // Virtual Control Register
578 case MISCREG_ICV_CTLR_EL1: {
579 ICV_CTLR_EL1 icv_ctlr_el1 = value;
580 icv_ctlr_el1.RSS = 0;
581 icv_ctlr_el1.A3V = 1;
582 icv_ctlr_el1.SEIS = 0;
583 icv_ctlr_el1.IDbits = 1;
584 icv_ctlr_el1.PRIbits = 7;
585 value = icv_ctlr_el1;
586 break;
587 }
588
589 // Control Register
590 case MISCREG_ICC_MCTLR:
591 case MISCREG_ICC_CTLR_EL3: {
592 // Enforce value for RO bits
593 // ExtRange [19], INTIDs in the range 1024..8191 not supported
594 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
595 // nDS [17], supports disabling of security
596 // A3V [15], supports non-zero values of the Aff3 field in SGI
597 // generation System registers
598 // SEIS [14], does not support generation of SEIs (deprecated)
599 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
600 // PRIbits [10:8], number of priority bits implemented, minus one
601 ICC_CTLR_EL3 icc_ctlr_el3 = value;
602 icc_ctlr_el3.ExtRange = 0;
603 icc_ctlr_el3.RSS = 1;
604 icc_ctlr_el3.nDS = 0;
605 icc_ctlr_el3.A3V = 1;
606 icc_ctlr_el3.SEIS = 0;
607 icc_ctlr_el3.IDbits = 0;
608 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
609 value = icc_ctlr_el3;
610 break;
611 }
612
613 // Hyp Control Register
614 case MISCREG_ICH_HCR:
615 case MISCREG_ICH_HCR_EL2:
616 break;
617
618 // Hyp Active Priorities Group 0 Registers
619 case MISCREG_ICH_AP0R0:
620 case MISCREG_ICH_AP0R0_EL2:
621 break;
622
623 // only implemented if supporting 6 or more bits of priority
624 case MISCREG_ICH_AP0R1:
625 case MISCREG_ICH_AP0R1_EL2:
626 // only implemented if supporting 7 or more bits of priority
627 case MISCREG_ICH_AP0R2:
628 case MISCREG_ICH_AP0R2_EL2:
629 // only implemented if supporting 7 or more bits of priority
630 case MISCREG_ICH_AP0R3:
631 case MISCREG_ICH_AP0R3_EL2:
632 // Unimplemented registers are RAZ/WI
633 return 0;
634
635 // Hyp Active Priorities Group 1 Registers
636 case MISCREG_ICH_AP1R0:
637 case MISCREG_ICH_AP1R0_EL2:
638 break;
639
640 // only implemented if supporting 6 or more bits of priority
641 case MISCREG_ICH_AP1R1:
642 case MISCREG_ICH_AP1R1_EL2:
643 // only implemented if supporting 7 or more bits of priority
644 case MISCREG_ICH_AP1R2:
645 case MISCREG_ICH_AP1R2_EL2:
646 // only implemented if supporting 7 or more bits of priority
647 case MISCREG_ICH_AP1R3:
648 case MISCREG_ICH_AP1R3_EL2:
649 // Unimplemented registers are RAZ/WI
650 return 0;
651
652 // Maintenance Interrupt State Register
653 case MISCREG_ICH_MISR:
654 case MISCREG_ICH_MISR_EL2:
655 value = maintenanceInterruptStatus();
656 break;
657
658 // VGIC Type Register
659 case MISCREG_ICH_VTR:
660 case MISCREG_ICH_VTR_EL2: {
661 ICH_VTR_EL2 ich_vtr_el2 = value;
662
663 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
664 ich_vtr_el2.A3V = 1;
665 ich_vtr_el2.IDbits = 1;
666 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
667 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
668
669 value = ich_vtr_el2;
670 break;
671 }
672
673 // End of Interrupt Status Register
674 case MISCREG_ICH_EISR:
675 case MISCREG_ICH_EISR_EL2:
676 value = eoiMaintenanceInterruptStatus();
677 break;
678
679 // Empty List Register Status Register
680 case MISCREG_ICH_ELRSR:
681 case MISCREG_ICH_ELRSR_EL2:
682 value = 0;
683
684 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
685 ICH_LR_EL2 ich_lr_el2 =
686 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
687
688 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
689 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
690 value |= (1 << lr_idx);
691 }
692 }
693
694 break;
695
696 // List Registers
697 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
698 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
699 value = value >> 32;
700 break;
701
702 // List Registers
703 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
704 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
705 value = value & 0xffffffff;
706 break;
707
708 // List Registers
709 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
710 break;
711
712 // Virtual Machine Control Register
713 case MISCREG_ICH_VMCR:
714 case MISCREG_ICH_VMCR_EL2:
715 break;
716
717 default:
718 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
719 misc_reg, miscRegName[misc_reg]);
720 }
721
722 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
723 miscRegName[misc_reg], value);
724 return value;
725}
726
727void
728Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
729{
730 bool do_virtual_update = false;
731 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
732 miscRegName[misc_reg], val);
733 bool hcr_fmo = getHCREL2FMO();
734 bool hcr_imo = getHCREL2IMO();
735
736 switch (misc_reg) {
737 // Active Priorities Group 1 Registers
738 case MISCREG_ICC_AP1R0:
739 case MISCREG_ICC_AP1R0_EL1:
740 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
741 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
742 }
743
744 setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
745 return;
746
747 case MISCREG_ICC_AP1R1:
748 case MISCREG_ICC_AP1R1_EL1:
749
750 // only implemented if supporting 6 or more bits of priority
751 case MISCREG_ICC_AP1R2:
752 case MISCREG_ICC_AP1R2_EL1:
753
754 // only implemented if supporting 7 or more bits of priority
755 case MISCREG_ICC_AP1R3:
756 case MISCREG_ICC_AP1R3_EL1:
757 // only implemented if supporting 7 or more bits of priority
758 break;
759
760 // Active Priorities Group 0 Registers
761 case MISCREG_ICC_AP0R0:
762 case MISCREG_ICC_AP0R0_EL1:
763 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
764 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
765 }
766
767 break;
768
769 case MISCREG_ICC_AP0R1:
770 case MISCREG_ICC_AP0R1_EL1:
771
772 // only implemented if supporting 6 or more bits of priority
773 case MISCREG_ICC_AP0R2:
774 case MISCREG_ICC_AP0R2_EL1:
775
776 // only implemented if supporting 7 or more bits of priority
777 case MISCREG_ICC_AP0R3:
778 case MISCREG_ICC_AP0R3_EL1:
779 // only implemented if supporting 7 or more bits of priority
780 break;
781
782 // End Of Interrupt Register 0
783 case MISCREG_ICC_EOIR0:
784 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
785 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
786 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
787 }
788
789 int int_id = val & 0xffffff;
790
791 // avoid activation for special interrupts
792 if (int_id >= Gicv3::INTID_SECURE &&
793 int_id <= Gicv3::INTID_SPURIOUS) {
794 return;
795 }
796
797 Gicv3::GroupId group = Gicv3::G0S;
798
799 if (highestActiveGroup() != group) {
800 return;
801 }
802
803 dropPriority(group);
804
805 if (!isEOISplitMode()) {
806 deactivateIRQ(int_id, group);
807 }
808
809 break;
810 }
811
812 // Virtual End Of Interrupt Register 0
813 case MISCREG_ICV_EOIR0_EL1: {
814 int int_id = val & 0xffffff;
815
816 // avoid deactivation for special interrupts
817 if (int_id >= Gicv3::INTID_SECURE &&
818 int_id <= Gicv3::INTID_SPURIOUS) {
819 return;
820 }
821
822 uint8_t drop_prio = virtualDropPriority();
823
824 if (drop_prio == 0xff) {
825 return;
826 }
827
828 int lr_idx = virtualFindActive(int_id);
829
830 if (lr_idx < 0) {
831 // No LR found matching
832 virtualIncrementEOICount();
833 } else {
834 ICH_LR_EL2 ich_lr_el2 =
835 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
836 Gicv3::GroupId lr_group =
837 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
838 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
839
840 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
841 //if (!virtualIsEOISplitMode())
842 {
843 virtualDeactivateIRQ(lr_idx);
844 }
845 }
846 }
847
848 virtualUpdate();
849 break;
850 }
851
852 // End Of Interrupt Register 1
853 case MISCREG_ICC_EOIR1:
854 case MISCREG_ICC_EOIR1_EL1: {
855 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
856 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
857 }
858
859 int int_id = val & 0xffffff;
860
861 // avoid deactivation for special interrupts
862 if (int_id >= Gicv3::INTID_SECURE &&
863 int_id <= Gicv3::INTID_SPURIOUS) {
864 return;
865 }
866
867 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
868
869 if (highestActiveGroup() == Gicv3::G0S) {
870 return;
871 }
872
873 if (distributor->DS == 0) {
874 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
875 return;
876 } else if (highestActiveGroup() == Gicv3::G1NS &&
877 !(!inSecureState() or (currEL() == EL3))) {
878 return;
879 }
880 }
881
882 dropPriority(group);
883
884 if (!isEOISplitMode()) {
885 deactivateIRQ(int_id, group);
886 }
887
888 break;
889 }
890
891 // Virtual End Of Interrupt Register 1
892 case MISCREG_ICV_EOIR1_EL1: {
893 int int_id = val & 0xffffff;
894
895 // avoid deactivation for special interrupts
896 if (int_id >= Gicv3::INTID_SECURE &&
897 int_id <= Gicv3::INTID_SPURIOUS) {
898 return;
899 }
900
901 uint8_t drop_prio = virtualDropPriority();
902
903 if (drop_prio == 0xff) {
904 return;
905 }
906
907 int lr_idx = virtualFindActive(int_id);
908
909 if (lr_idx < 0) {
910 // No matching LR found
911 virtualIncrementEOICount();
912 } else {
913 ICH_LR_EL2 ich_lr_el2 =
914 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
915 Gicv3::GroupId lr_group =
916 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
917 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
918
919 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
920 if (!virtualIsEOISplitMode()) {
921 virtualDeactivateIRQ(lr_idx);
922 }
923 }
924 }
925
926 virtualUpdate();
927 break;
928 }
929
930 // Deactivate Interrupt Register
931 case MISCREG_ICC_DIR:
932 case MISCREG_ICC_DIR_EL1: {
933 if ((currEL() == EL1) && !inSecureState() &&
934 (hcr_imo || hcr_fmo)) {
935 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
936 }
937
938 int int_id = val & 0xffffff;
939
940 // The following checks are as per spec pseudocode
941 // aarch64/support/ICC_DIR_EL1
942
943 // Check for spurious ID
944 if (int_id >= Gicv3::INTID_SECURE) {
945 return;
946 }
947
948 // EOI mode is not set, so don't deactivate
949 if (!isEOISplitMode()) {
950 return;
951 }
952
953 Gicv3::GroupId group =
954 int_id >= 32 ? distributor->getIntGroup(int_id) :
955 redistributor->getIntGroup(int_id);
956 bool irq_is_grp0 = group == Gicv3::G0S;
957 bool single_sec_state = distributor->DS;
958 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
959 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
960 bool route_fiq_to_el3 = scr_el3.fiq;
961 bool route_irq_to_el3 = scr_el3.irq;
962 bool route_fiq_to_el2 = hcr_fmo;
963 bool route_irq_to_el2 = hcr_imo;
964
965 switch (currEL()) {
966 case EL3:
967 break;
968
969 case EL2:
970 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
971 break;
972 }
973
974 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
975 break;
976 }
977
978 return;
979
980 case EL1:
981 if (!isSecureBelowEL3()) {
982 if (single_sec_state && irq_is_grp0 &&
983 !route_fiq_to_el3 && !route_fiq_to_el2) {
984 break;
985 }
986
987 if (!irq_is_secure && !irq_is_grp0 &&
988 !route_irq_to_el3 && !route_irq_to_el2) {
989 break;
990 }
991 } else {
992 if (irq_is_grp0 && !route_fiq_to_el3) {
993 break;
994 }
995
996 if (!irq_is_grp0 &&
997 (!irq_is_secure || !single_sec_state) &&
998 !route_irq_to_el3) {
999 break;
1000 }
1001 }
1002
1003 return;
1004
1005 default:
1006 break;
1007 }
1008
1009 deactivateIRQ(int_id, group);
1010 break;
1011 }
1012
1013 // Deactivate Virtual Interrupt Register
1014 case MISCREG_ICV_DIR_EL1: {
1015 int int_id = val & 0xffffff;
1016
1017 // avoid deactivation for special interrupts
1018 if (int_id >= Gicv3::INTID_SECURE &&
1019 int_id <= Gicv3::INTID_SPURIOUS) {
1020 return;
1021 }
1022
1023 if (!virtualIsEOISplitMode()) {
1024 return;
1025 }
1026
1027 int lr_idx = virtualFindActive(int_id);
1028
1029 if (lr_idx < 0) {
1030 // No matching LR found
1031 virtualIncrementEOICount();
1032 } else {
1033 virtualDeactivateIRQ(lr_idx);
1034 }
1035
1036 virtualUpdate();
1037 break;
1038 }
1039
1040 // Binary Point Register 0
1041 case MISCREG_ICC_BPR0:
1042 case MISCREG_ICC_BPR0_EL1: {
1043 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1044 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1045 }
1046 break;
1047 }
1048 // Binary Point Register 1
1049 case MISCREG_ICC_BPR1:
1050 case MISCREG_ICC_BPR1_EL1: {
1051 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1052 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1053 }
1054
1055 val &= 0x7;
1056
1057 if (isSecureBelowEL3()) {
1058 // group == Gicv3::G1S
1059 ICC_CTLR_EL1 icc_ctlr_el1_s =
1060 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1061
1062 val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR;
1063 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
1064 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1065 } else {
1066 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1067 }
1068 return;
1069 } else {
1070 // group == Gicv3::G1NS
1071 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1072 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1073
1074 val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS;
1075 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
1076 // Non secure writes from EL1 and EL2 are ignored
1077 } else {
1078 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1079 }
1080 return;
1081 }
1082
1083 break;
1084 }
1085
1086 // Virtual Binary Point Register 0
1087 case MISCREG_ICV_BPR0_EL1:
1088 // Virtual Binary Point Register 1
1089 case MISCREG_ICV_BPR1_EL1: {
1090 Gicv3::GroupId group =
1091 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1092 ICH_VMCR_EL2 ich_vmcr_el2 =
1093 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1094
1095 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1096 // BPR0 + 1 saturated to 7, WI
1097 return;
1098 }
1099
1100 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1101
1102 if (group != Gicv3::G0S) {
1103 min_VPBR++;
1104 }
1105
1106 if (val < min_VPBR) {
1107 val = min_VPBR;
1108 }
1109
1110 if (group == Gicv3::G0S) {
1111 ich_vmcr_el2.VBPR0 = val;
1112 } else {
1113 ich_vmcr_el2.VBPR1 = val;
1114 }
1115
1116 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1117 do_virtual_update = true;
1118 break;
1119 }
1120
1121 // Control Register EL1
1122 case MISCREG_ICC_CTLR:
1123 case MISCREG_ICC_CTLR_EL1: {
1124 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1125 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1126 }
1127
1128 /*
1129 * ExtRange is RO.
1130 * RSS is RO.
1131 * A3V is RO.
1132 * SEIS is RO.
1133 * IDbits is RO.
1134 * PRIbits is RO.
1135 */
1136 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1137 ICC_CTLR_EL1 icc_ctlr_el1 =
1138 readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1139
1140 ICC_CTLR_EL3 icc_ctlr_el3 =
1141 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1142
1143 // The following could be refactored but it is following
1144 // spec description section 9.2.6 point by point.
1145
1146 // PMHE
1147 if (haveEL(EL3)) {
1148 // PMHE is alias of ICC_CTLR_EL3.PMHE
1149
1150 if (distributor->DS == 0) {
1151 // PMHE is RO
1152 } else if (distributor->DS == 1) {
1153 // PMHE is RW
1154 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1155 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1156 }
1157 } else {
1158 // PMHE is RW (by implementation choice)
1159 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1160 }
1161
1162 // EOImode
1163 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1164
1165 if (inSecureState()) {
1166 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1167 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1168 } else {
1169 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1170 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1171 }
1172
1173 // CBPR
1174 if (haveEL(EL3)) {
1175 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1176
1177 if (distributor->DS == 0) {
1178 // CBPR is RO
1179 } else {
1180 // CBPR is RW
1181 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1182
1183 if (inSecureState()) {
1184 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1185 } else {
1186 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1187 }
1188 }
1189 } else {
1190 // CBPR is RW
1191 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1192 }
1193
1194 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1195
1196 setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
1197 return;
1198 }
1199
1200 // Virtual Control Register
1201 case MISCREG_ICV_CTLR_EL1: {
1202 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1203 ICV_CTLR_EL1 icv_ctlr_el1 =
1204 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1205 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1206 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1207 val = icv_ctlr_el1;
1208
1209 // Aliases
1210 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1211 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1212 ICH_VMCR_EL2 ich_vmcr_el2 =
1213 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1214 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1215 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1216 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1217 break;
1218 }
1219
1220 // Control Register EL3
1221 case MISCREG_ICC_MCTLR:
1222 case MISCREG_ICC_CTLR_EL3: {
1223 /*
1224 * ExtRange is RO.
1225 * RSS is RO.
1226 * nDS is RO.
1227 * A3V is RO.
1228 * SEIS is RO.
1229 * IDbits is RO.
1230 * PRIbits is RO.
1231 * PMHE is RAO/WI, priority-based routing is always used.
1232 */
1233 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1234
1235 // Aliases
1236 if (haveEL(EL3))
1237 {
1238 ICC_CTLR_EL1 icc_ctlr_el1_s =
1239 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1240 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1241 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1242
1243 // ICC_CTLR_EL1(NS).EOImode is an alias of
1244 // ICC_CTLR_EL3.EOImode_EL1NS
1245 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1246 // ICC_CTLR_EL1(S).EOImode is an alias of
1247 // ICC_CTLR_EL3.EOImode_EL1S
1248 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1249 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1250 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1251 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1252 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1253
1254 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1255 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1256 icc_ctlr_el1_ns);
1257 }
1258
1259 ICC_CTLR_EL3 icc_ctlr_el3 =
1260 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1261
1262 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1263 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1264 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1265 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1266 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1267 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1268
1269 val = icc_ctlr_el3;
1270 break;
1271 }
1272
1273 // Priority Mask Register
1274 case MISCREG_ICC_PMR:
1275 case MISCREG_ICC_PMR_EL1: {
1276 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1277 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1278 }
1279
1280 val &= 0xff;
1281 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1282
1283 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1284 // Spec section 4.8.1
1285 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1286 RegVal old_icc_pmr_el1 =
1287 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1288
1289 if (!(old_icc_pmr_el1 & 0x80)) {
1290 // If the current priority mask value is in the range of
1291 // 0x00-0x7F then WI
1292 return;
1293 }
1294
1295 // If the current priority mask value is in the range of
1296 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1297 // based on the Non-secure read of the priority mask value
1298 // written to the register.
1299
1300 val = (val >> 1) | 0x80;
1301 }
1302
1303 val &= ~0U << (8 - PRIORITY_BITS);
1304 break;
1305 }
1306
1307 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1308 ICH_VMCR_EL2 ich_vmcr_el2 =
1309 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1310 ich_vmcr_el2.VPMR = val & 0xff;
1311
1312 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1313 virtualUpdate();
1314 return;
1315 }
1316
1317 // Interrupt Group 0 Enable Register EL1
1318 case MISCREG_ICC_IGRPEN0:
1319 case MISCREG_ICC_IGRPEN0_EL1: {
1320 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1321 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1322 }
1323
1324 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1325 updateDistributor();
1326 return;
1327 }
1328
1329 // Virtual Interrupt Group 0 Enable register
1330 case MISCREG_ICV_IGRPEN0_EL1: {
1331 bool enable = val & 0x1;
1332 ICH_VMCR_EL2 ich_vmcr_el2 =
1333 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1334 ich_vmcr_el2.VENG0 = enable;
1335 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1336 virtualUpdate();
1337 return;
1338 }
1339
1340 // Interrupt Group 1 Enable register EL1
1341 case MISCREG_ICC_IGRPEN1:
1342 case MISCREG_ICC_IGRPEN1_EL1: {
1343 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1344 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1345 }
1346
| 218
219 // Running Priority Register
220 case MISCREG_ICC_RPR:
221 case MISCREG_ICC_RPR_EL1: {
222 if ((currEL() == EL1) && !inSecureState() &&
223 (hcr_imo || hcr_fmo)) {
224 return readMiscReg(MISCREG_ICV_RPR_EL1);
225 }
226
227 uint8_t rprio = highestActivePriority();
228
229 if (haveEL(EL3) && !inSecureState() &&
230 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
231 // Spec section 4.8.1
232 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
233 if ((rprio & 0x80) == 0) {
234 // If the current priority mask value is in the range of
235 // 0x00-0x7F a read access returns the value 0x0
236 rprio = 0;
237 } else if (rprio != 0xff) {
238 // If the current priority mask value is in the range of
239 // 0x80-0xFF a read access returns the Non-secure read of
240 // the current value
241 rprio = (rprio << 1) & 0xff;
242 }
243 }
244
245 value = rprio;
246 break;
247 }
248
249 // Virtual Running Priority Register
250 case MISCREG_ICV_RPR_EL1: {
251 value = virtualHighestActivePriority();
252 break;
253 }
254
255 // Highest Priority Pending Interrupt Register 0
256 case MISCREG_ICC_HPPIR0:
257 case MISCREG_ICC_HPPIR0_EL1: {
258 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
259 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
260 }
261
262 value = getHPPIR0();
263 break;
264 }
265
266 // Virtual Highest Priority Pending Interrupt Register 0
267 case MISCREG_ICV_HPPIR0_EL1: {
268 value = Gicv3::INTID_SPURIOUS;
269 int lr_idx = getHPPVILR();
270
271 if (lr_idx >= 0) {
272 ICH_LR_EL2 ich_lr_el2 =
273 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
274 Gicv3::GroupId group =
275 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
276
277 if (group == Gicv3::G0S) {
278 value = ich_lr_el2.vINTID;
279 }
280 }
281
282 break;
283 }
284
285 // Highest Priority Pending Interrupt Register 1
286 case MISCREG_ICC_HPPIR1:
287 case MISCREG_ICC_HPPIR1_EL1: {
288 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
289 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
290 }
291
292 value = getHPPIR1();
293 break;
294 }
295
296 // Virtual Highest Priority Pending Interrupt Register 1
297 case MISCREG_ICV_HPPIR1_EL1: {
298 value = Gicv3::INTID_SPURIOUS;
299 int lr_idx = getHPPVILR();
300
301 if (lr_idx >= 0) {
302 ICH_LR_EL2 ich_lr_el2 =
303 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
304 Gicv3::GroupId group =
305 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
306
307 if (group == Gicv3::G1NS) {
308 value = ich_lr_el2.vINTID;
309 }
310 }
311
312 break;
313 }
314
315 // Binary Point Register 0
316 case MISCREG_ICC_BPR0:
317 case MISCREG_ICC_BPR0_EL1: {
318 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
319 return readMiscReg(MISCREG_ICV_BPR0_EL1);
320 }
321
322 value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
323 break;
324 }
325
326 // Binary Point Register 1
327 case MISCREG_ICC_BPR1:
328 case MISCREG_ICC_BPR1_EL1: {
329 value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS);
330 break;
331 }
332
333 // Virtual Binary Point Register 0
334 case MISCREG_ICV_BPR0_EL1: {
335 ICH_VMCR_EL2 ich_vmcr_el2 =
336 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
337
338 value = ich_vmcr_el2.VBPR0;
339 break;
340 }
341
342 // Virtual Binary Point Register 1
343 case MISCREG_ICV_BPR1_EL1: {
344 ICH_VMCR_EL2 ich_vmcr_el2 =
345 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
346
347 if (ich_vmcr_el2.VCBPR) {
348 // bpr0 + 1 saturated to 7, WI
349 value = ich_vmcr_el2.VBPR0 + 1;
350 value = value < 7 ? value : 7;
351 } else {
352 value = ich_vmcr_el2.VBPR1;
353 }
354
355 break;
356 }
357
358 // Interrupt Priority Mask Register
359 case MISCREG_ICC_PMR:
360 case MISCREG_ICC_PMR_EL1:
361 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
362 return readMiscReg(MISCREG_ICV_PMR_EL1);
363 }
364
365 if (haveEL(EL3) && !inSecureState() &&
366 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
367 // Spec section 4.8.1
368 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
369 if ((value & 0x80) == 0) {
370 // If the current priority mask value is in the range of
371 // 0x00-0x7F a read access returns the value 0x00.
372 value = 0;
373 } else if (value != 0xff) {
374 // If the current priority mask value is in the range of
375 // 0x80-0xFF a read access returns the Non-secure read of the
376 // current value.
377 value = (value << 1) & 0xff;
378 }
379 }
380
381 break;
382
383 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
384 ICH_VMCR_EL2 ich_vmcr_el2 =
385 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
386
387 value = ich_vmcr_el2.VPMR;
388 break;
389 }
390
391 // Interrupt Acknowledge Register 0
392 case MISCREG_ICC_IAR0:
393 case MISCREG_ICC_IAR0_EL1: {
394 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
395 return readMiscReg(MISCREG_ICV_IAR0_EL1);
396 }
397
398 uint32_t int_id;
399
400 if (hppiCanPreempt()) {
401 int_id = getHPPIR0();
402
403 // avoid activation for special interrupts
404 if (int_id < Gicv3::INTID_SECURE ||
405 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
406 activateIRQ(int_id, hppi.group);
407 }
408 } else {
409 int_id = Gicv3::INTID_SPURIOUS;
410 }
411
412 value = int_id;
413 break;
414 }
415
416 // Virtual Interrupt Acknowledge Register 0
417 case MISCREG_ICV_IAR0_EL1: {
418 int lr_idx = getHPPVILR();
419 uint32_t int_id = Gicv3::INTID_SPURIOUS;
420
421 if (lr_idx >= 0) {
422 ICH_LR_EL2 ich_lr_el2 =
423 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
424
425 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
426 int_id = ich_lr_el2.vINTID;
427
428 if (int_id < Gicv3::INTID_SECURE ||
429 int_id > Gicv3::INTID_SPURIOUS) {
430 virtualActivateIRQ(lr_idx);
431 } else {
432 // Bogus... Pseudocode says:
433 // - Move from pending to invalid...
434 // - Return de bogus id...
435 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
436 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
437 ich_lr_el2);
438 }
439 }
440 }
441
442 value = int_id;
443 virtualUpdate();
444 break;
445 }
446
447 // Interrupt Acknowledge Register 1
448 case MISCREG_ICC_IAR1:
449 case MISCREG_ICC_IAR1_EL1: {
450 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
451 return readMiscReg(MISCREG_ICV_IAR1_EL1);
452 }
453
454 uint32_t int_id;
455
456 if (hppiCanPreempt()) {
457 int_id = getHPPIR1();
458
459 // avoid activation for special interrupts
460 if (int_id < Gicv3::INTID_SECURE ||
461 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
462 activateIRQ(int_id, hppi.group);
463 }
464 } else {
465 int_id = Gicv3::INTID_SPURIOUS;
466 }
467
468 value = int_id;
469 break;
470 }
471
472 // Virtual Interrupt Acknowledge Register 1
473 case MISCREG_ICV_IAR1_EL1: {
474 int lr_idx = getHPPVILR();
475 uint32_t int_id = Gicv3::INTID_SPURIOUS;
476
477 if (lr_idx >= 0) {
478 ICH_LR_EL2 ich_lr_el2 =
479 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
480
481 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
482 int_id = ich_lr_el2.vINTID;
483
484 if (int_id < Gicv3::INTID_SECURE ||
485 int_id > Gicv3::INTID_SPURIOUS) {
486 virtualActivateIRQ(lr_idx);
487 } else {
488 // Bogus... Pseudocode says:
489 // - Move from pending to invalid...
490 // - Return de bogus id...
491 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
492 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
493 ich_lr_el2);
494 }
495 }
496 }
497
498 value = int_id;
499 virtualUpdate();
500 break;
501 }
502
503 // System Register Enable Register EL1
504 case MISCREG_ICC_SRE:
505 case MISCREG_ICC_SRE_EL1: {
506 /*
507 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
508 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
509 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
510 */
511 ICC_SRE_EL1 icc_sre_el1 = 0;
512 icc_sre_el1.SRE = 1;
513 icc_sre_el1.DIB = 1;
514 icc_sre_el1.DFB = 1;
515 value = icc_sre_el1;
516 break;
517 }
518
519 // System Register Enable Register EL2
520 case MISCREG_ICC_HSRE:
521 case MISCREG_ICC_SRE_EL2: {
522 /*
523 * Enable [3] == 1
524 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
525 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
526 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
527 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
528 */
529 ICC_SRE_EL2 icc_sre_el2 = 0;
530 icc_sre_el2.SRE = 1;
531 icc_sre_el2.DIB = 1;
532 icc_sre_el2.DFB = 1;
533 icc_sre_el2.Enable = 1;
534 value = icc_sre_el2;
535 break;
536 }
537
538 // System Register Enable Register EL3
539 case MISCREG_ICC_MSRE:
540 case MISCREG_ICC_SRE_EL3: {
541 /*
542 * Enable [3] == 1
543 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
544 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
545 * RAO/WI)
546 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
547 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
548 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
549 */
550 ICC_SRE_EL3 icc_sre_el3 = 0;
551 icc_sre_el3.SRE = 1;
552 icc_sre_el3.DIB = 1;
553 icc_sre_el3.DFB = 1;
554 icc_sre_el3.Enable = 1;
555 value = icc_sre_el3;
556 break;
557 }
558
559 // Control Register
560 case MISCREG_ICC_CTLR:
561 case MISCREG_ICC_CTLR_EL1: {
562 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
563 return readMiscReg(MISCREG_ICV_CTLR_EL1);
564 }
565
566 value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
567 // Enforce value for RO bits
568 // ExtRange [19], INTIDs in the range 1024..8191 not supported
569 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
570 // A3V [15], supports non-zero values of the Aff3 field in SGI
571 // generation System registers
572 // SEIS [14], does not support generation of SEIs (deprecated)
573 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
574 // PRIbits [10:8], number of priority bits implemented, minus one
575 ICC_CTLR_EL1 icc_ctlr_el1 = value;
576 icc_ctlr_el1.ExtRange = 0;
577 icc_ctlr_el1.RSS = 1;
578 icc_ctlr_el1.A3V = 1;
579 icc_ctlr_el1.SEIS = 0;
580 icc_ctlr_el1.IDbits = 1;
581 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
582 value = icc_ctlr_el1;
583 break;
584 }
585
586 // Virtual Control Register
587 case MISCREG_ICV_CTLR_EL1: {
588 ICV_CTLR_EL1 icv_ctlr_el1 = value;
589 icv_ctlr_el1.RSS = 0;
590 icv_ctlr_el1.A3V = 1;
591 icv_ctlr_el1.SEIS = 0;
592 icv_ctlr_el1.IDbits = 1;
593 icv_ctlr_el1.PRIbits = 7;
594 value = icv_ctlr_el1;
595 break;
596 }
597
598 // Control Register
599 case MISCREG_ICC_MCTLR:
600 case MISCREG_ICC_CTLR_EL3: {
601 // Enforce value for RO bits
602 // ExtRange [19], INTIDs in the range 1024..8191 not supported
603 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
604 // nDS [17], supports disabling of security
605 // A3V [15], supports non-zero values of the Aff3 field in SGI
606 // generation System registers
607 // SEIS [14], does not support generation of SEIs (deprecated)
608 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
609 // PRIbits [10:8], number of priority bits implemented, minus one
610 ICC_CTLR_EL3 icc_ctlr_el3 = value;
611 icc_ctlr_el3.ExtRange = 0;
612 icc_ctlr_el3.RSS = 1;
613 icc_ctlr_el3.nDS = 0;
614 icc_ctlr_el3.A3V = 1;
615 icc_ctlr_el3.SEIS = 0;
616 icc_ctlr_el3.IDbits = 0;
617 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
618 value = icc_ctlr_el3;
619 break;
620 }
621
622 // Hyp Control Register
623 case MISCREG_ICH_HCR:
624 case MISCREG_ICH_HCR_EL2:
625 break;
626
627 // Hyp Active Priorities Group 0 Registers
628 case MISCREG_ICH_AP0R0:
629 case MISCREG_ICH_AP0R0_EL2:
630 break;
631
632 // only implemented if supporting 6 or more bits of priority
633 case MISCREG_ICH_AP0R1:
634 case MISCREG_ICH_AP0R1_EL2:
635 // only implemented if supporting 7 or more bits of priority
636 case MISCREG_ICH_AP0R2:
637 case MISCREG_ICH_AP0R2_EL2:
638 // only implemented if supporting 7 or more bits of priority
639 case MISCREG_ICH_AP0R3:
640 case MISCREG_ICH_AP0R3_EL2:
641 // Unimplemented registers are RAZ/WI
642 return 0;
643
644 // Hyp Active Priorities Group 1 Registers
645 case MISCREG_ICH_AP1R0:
646 case MISCREG_ICH_AP1R0_EL2:
647 break;
648
649 // only implemented if supporting 6 or more bits of priority
650 case MISCREG_ICH_AP1R1:
651 case MISCREG_ICH_AP1R1_EL2:
652 // only implemented if supporting 7 or more bits of priority
653 case MISCREG_ICH_AP1R2:
654 case MISCREG_ICH_AP1R2_EL2:
655 // only implemented if supporting 7 or more bits of priority
656 case MISCREG_ICH_AP1R3:
657 case MISCREG_ICH_AP1R3_EL2:
658 // Unimplemented registers are RAZ/WI
659 return 0;
660
661 // Maintenance Interrupt State Register
662 case MISCREG_ICH_MISR:
663 case MISCREG_ICH_MISR_EL2:
664 value = maintenanceInterruptStatus();
665 break;
666
667 // VGIC Type Register
668 case MISCREG_ICH_VTR:
669 case MISCREG_ICH_VTR_EL2: {
670 ICH_VTR_EL2 ich_vtr_el2 = value;
671
672 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
673 ich_vtr_el2.A3V = 1;
674 ich_vtr_el2.IDbits = 1;
675 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
676 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
677
678 value = ich_vtr_el2;
679 break;
680 }
681
682 // End of Interrupt Status Register
683 case MISCREG_ICH_EISR:
684 case MISCREG_ICH_EISR_EL2:
685 value = eoiMaintenanceInterruptStatus();
686 break;
687
688 // Empty List Register Status Register
689 case MISCREG_ICH_ELRSR:
690 case MISCREG_ICH_ELRSR_EL2:
691 value = 0;
692
693 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
694 ICH_LR_EL2 ich_lr_el2 =
695 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
696
697 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
698 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
699 value |= (1 << lr_idx);
700 }
701 }
702
703 break;
704
705 // List Registers
706 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
707 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
708 value = value >> 32;
709 break;
710
711 // List Registers
712 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
713 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
714 value = value & 0xffffffff;
715 break;
716
717 // List Registers
718 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
719 break;
720
721 // Virtual Machine Control Register
722 case MISCREG_ICH_VMCR:
723 case MISCREG_ICH_VMCR_EL2:
724 break;
725
726 default:
727 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
728 misc_reg, miscRegName[misc_reg]);
729 }
730
731 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
732 miscRegName[misc_reg], value);
733 return value;
734}
735
736void
737Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
738{
739 bool do_virtual_update = false;
740 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
741 miscRegName[misc_reg], val);
742 bool hcr_fmo = getHCREL2FMO();
743 bool hcr_imo = getHCREL2IMO();
744
745 switch (misc_reg) {
746 // Active Priorities Group 1 Registers
747 case MISCREG_ICC_AP1R0:
748 case MISCREG_ICC_AP1R0_EL1:
749 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
750 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
751 }
752
753 setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
754 return;
755
756 case MISCREG_ICC_AP1R1:
757 case MISCREG_ICC_AP1R1_EL1:
758
759 // only implemented if supporting 6 or more bits of priority
760 case MISCREG_ICC_AP1R2:
761 case MISCREG_ICC_AP1R2_EL1:
762
763 // only implemented if supporting 7 or more bits of priority
764 case MISCREG_ICC_AP1R3:
765 case MISCREG_ICC_AP1R3_EL1:
766 // only implemented if supporting 7 or more bits of priority
767 break;
768
769 // Active Priorities Group 0 Registers
770 case MISCREG_ICC_AP0R0:
771 case MISCREG_ICC_AP0R0_EL1:
772 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
773 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
774 }
775
776 break;
777
778 case MISCREG_ICC_AP0R1:
779 case MISCREG_ICC_AP0R1_EL1:
780
781 // only implemented if supporting 6 or more bits of priority
782 case MISCREG_ICC_AP0R2:
783 case MISCREG_ICC_AP0R2_EL1:
784
785 // only implemented if supporting 7 or more bits of priority
786 case MISCREG_ICC_AP0R3:
787 case MISCREG_ICC_AP0R3_EL1:
788 // only implemented if supporting 7 or more bits of priority
789 break;
790
791 // End Of Interrupt Register 0
792 case MISCREG_ICC_EOIR0:
793 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
794 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
795 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
796 }
797
798 int int_id = val & 0xffffff;
799
800 // avoid activation for special interrupts
801 if (int_id >= Gicv3::INTID_SECURE &&
802 int_id <= Gicv3::INTID_SPURIOUS) {
803 return;
804 }
805
806 Gicv3::GroupId group = Gicv3::G0S;
807
808 if (highestActiveGroup() != group) {
809 return;
810 }
811
812 dropPriority(group);
813
814 if (!isEOISplitMode()) {
815 deactivateIRQ(int_id, group);
816 }
817
818 break;
819 }
820
821 // Virtual End Of Interrupt Register 0
822 case MISCREG_ICV_EOIR0_EL1: {
823 int int_id = val & 0xffffff;
824
825 // avoid deactivation for special interrupts
826 if (int_id >= Gicv3::INTID_SECURE &&
827 int_id <= Gicv3::INTID_SPURIOUS) {
828 return;
829 }
830
831 uint8_t drop_prio = virtualDropPriority();
832
833 if (drop_prio == 0xff) {
834 return;
835 }
836
837 int lr_idx = virtualFindActive(int_id);
838
839 if (lr_idx < 0) {
840 // No LR found matching
841 virtualIncrementEOICount();
842 } else {
843 ICH_LR_EL2 ich_lr_el2 =
844 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
845 Gicv3::GroupId lr_group =
846 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
847 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
848
849 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
850 //if (!virtualIsEOISplitMode())
851 {
852 virtualDeactivateIRQ(lr_idx);
853 }
854 }
855 }
856
857 virtualUpdate();
858 break;
859 }
860
861 // End Of Interrupt Register 1
862 case MISCREG_ICC_EOIR1:
863 case MISCREG_ICC_EOIR1_EL1: {
864 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
865 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
866 }
867
868 int int_id = val & 0xffffff;
869
870 // avoid deactivation for special interrupts
871 if (int_id >= Gicv3::INTID_SECURE &&
872 int_id <= Gicv3::INTID_SPURIOUS) {
873 return;
874 }
875
876 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
877
878 if (highestActiveGroup() == Gicv3::G0S) {
879 return;
880 }
881
882 if (distributor->DS == 0) {
883 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
884 return;
885 } else if (highestActiveGroup() == Gicv3::G1NS &&
886 !(!inSecureState() or (currEL() == EL3))) {
887 return;
888 }
889 }
890
891 dropPriority(group);
892
893 if (!isEOISplitMode()) {
894 deactivateIRQ(int_id, group);
895 }
896
897 break;
898 }
899
900 // Virtual End Of Interrupt Register 1
901 case MISCREG_ICV_EOIR1_EL1: {
902 int int_id = val & 0xffffff;
903
904 // avoid deactivation for special interrupts
905 if (int_id >= Gicv3::INTID_SECURE &&
906 int_id <= Gicv3::INTID_SPURIOUS) {
907 return;
908 }
909
910 uint8_t drop_prio = virtualDropPriority();
911
912 if (drop_prio == 0xff) {
913 return;
914 }
915
916 int lr_idx = virtualFindActive(int_id);
917
918 if (lr_idx < 0) {
919 // No matching LR found
920 virtualIncrementEOICount();
921 } else {
922 ICH_LR_EL2 ich_lr_el2 =
923 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
924 Gicv3::GroupId lr_group =
925 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
926 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
927
928 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
929 if (!virtualIsEOISplitMode()) {
930 virtualDeactivateIRQ(lr_idx);
931 }
932 }
933 }
934
935 virtualUpdate();
936 break;
937 }
938
939 // Deactivate Interrupt Register
940 case MISCREG_ICC_DIR:
941 case MISCREG_ICC_DIR_EL1: {
942 if ((currEL() == EL1) && !inSecureState() &&
943 (hcr_imo || hcr_fmo)) {
944 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
945 }
946
947 int int_id = val & 0xffffff;
948
949 // The following checks are as per spec pseudocode
950 // aarch64/support/ICC_DIR_EL1
951
952 // Check for spurious ID
953 if (int_id >= Gicv3::INTID_SECURE) {
954 return;
955 }
956
957 // EOI mode is not set, so don't deactivate
958 if (!isEOISplitMode()) {
959 return;
960 }
961
962 Gicv3::GroupId group =
963 int_id >= 32 ? distributor->getIntGroup(int_id) :
964 redistributor->getIntGroup(int_id);
965 bool irq_is_grp0 = group == Gicv3::G0S;
966 bool single_sec_state = distributor->DS;
967 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
968 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
969 bool route_fiq_to_el3 = scr_el3.fiq;
970 bool route_irq_to_el3 = scr_el3.irq;
971 bool route_fiq_to_el2 = hcr_fmo;
972 bool route_irq_to_el2 = hcr_imo;
973
974 switch (currEL()) {
975 case EL3:
976 break;
977
978 case EL2:
979 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
980 break;
981 }
982
983 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
984 break;
985 }
986
987 return;
988
989 case EL1:
990 if (!isSecureBelowEL3()) {
991 if (single_sec_state && irq_is_grp0 &&
992 !route_fiq_to_el3 && !route_fiq_to_el2) {
993 break;
994 }
995
996 if (!irq_is_secure && !irq_is_grp0 &&
997 !route_irq_to_el3 && !route_irq_to_el2) {
998 break;
999 }
1000 } else {
1001 if (irq_is_grp0 && !route_fiq_to_el3) {
1002 break;
1003 }
1004
1005 if (!irq_is_grp0 &&
1006 (!irq_is_secure || !single_sec_state) &&
1007 !route_irq_to_el3) {
1008 break;
1009 }
1010 }
1011
1012 return;
1013
1014 default:
1015 break;
1016 }
1017
1018 deactivateIRQ(int_id, group);
1019 break;
1020 }
1021
1022 // Deactivate Virtual Interrupt Register
1023 case MISCREG_ICV_DIR_EL1: {
1024 int int_id = val & 0xffffff;
1025
1026 // avoid deactivation for special interrupts
1027 if (int_id >= Gicv3::INTID_SECURE &&
1028 int_id <= Gicv3::INTID_SPURIOUS) {
1029 return;
1030 }
1031
1032 if (!virtualIsEOISplitMode()) {
1033 return;
1034 }
1035
1036 int lr_idx = virtualFindActive(int_id);
1037
1038 if (lr_idx < 0) {
1039 // No matching LR found
1040 virtualIncrementEOICount();
1041 } else {
1042 virtualDeactivateIRQ(lr_idx);
1043 }
1044
1045 virtualUpdate();
1046 break;
1047 }
1048
1049 // Binary Point Register 0
1050 case MISCREG_ICC_BPR0:
1051 case MISCREG_ICC_BPR0_EL1: {
1052 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1053 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1054 }
1055 break;
1056 }
1057 // Binary Point Register 1
1058 case MISCREG_ICC_BPR1:
1059 case MISCREG_ICC_BPR1_EL1: {
1060 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1061 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1062 }
1063
1064 val &= 0x7;
1065
1066 if (isSecureBelowEL3()) {
1067 // group == Gicv3::G1S
1068 ICC_CTLR_EL1 icc_ctlr_el1_s =
1069 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1070
1071 val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR;
1072 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
1073 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1074 } else {
1075 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1076 }
1077 return;
1078 } else {
1079 // group == Gicv3::G1NS
1080 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1081 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1082
1083 val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS;
1084 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
1085 // Non secure writes from EL1 and EL2 are ignored
1086 } else {
1087 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1088 }
1089 return;
1090 }
1091
1092 break;
1093 }
1094
1095 // Virtual Binary Point Register 0
1096 case MISCREG_ICV_BPR0_EL1:
1097 // Virtual Binary Point Register 1
1098 case MISCREG_ICV_BPR1_EL1: {
1099 Gicv3::GroupId group =
1100 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1101 ICH_VMCR_EL2 ich_vmcr_el2 =
1102 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1103
1104 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1105 // BPR0 + 1 saturated to 7, WI
1106 return;
1107 }
1108
1109 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1110
1111 if (group != Gicv3::G0S) {
1112 min_VPBR++;
1113 }
1114
1115 if (val < min_VPBR) {
1116 val = min_VPBR;
1117 }
1118
1119 if (group == Gicv3::G0S) {
1120 ich_vmcr_el2.VBPR0 = val;
1121 } else {
1122 ich_vmcr_el2.VBPR1 = val;
1123 }
1124
1125 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1126 do_virtual_update = true;
1127 break;
1128 }
1129
1130 // Control Register EL1
1131 case MISCREG_ICC_CTLR:
1132 case MISCREG_ICC_CTLR_EL1: {
1133 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1134 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1135 }
1136
1137 /*
1138 * ExtRange is RO.
1139 * RSS is RO.
1140 * A3V is RO.
1141 * SEIS is RO.
1142 * IDbits is RO.
1143 * PRIbits is RO.
1144 */
1145 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1146 ICC_CTLR_EL1 icc_ctlr_el1 =
1147 readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1148
1149 ICC_CTLR_EL3 icc_ctlr_el3 =
1150 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1151
1152 // The following could be refactored but it is following
1153 // spec description section 9.2.6 point by point.
1154
1155 // PMHE
1156 if (haveEL(EL3)) {
1157 // PMHE is alias of ICC_CTLR_EL3.PMHE
1158
1159 if (distributor->DS == 0) {
1160 // PMHE is RO
1161 } else if (distributor->DS == 1) {
1162 // PMHE is RW
1163 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1164 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1165 }
1166 } else {
1167 // PMHE is RW (by implementation choice)
1168 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1169 }
1170
1171 // EOImode
1172 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1173
1174 if (inSecureState()) {
1175 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1176 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1177 } else {
1178 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1179 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1180 }
1181
1182 // CBPR
1183 if (haveEL(EL3)) {
1184 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1185
1186 if (distributor->DS == 0) {
1187 // CBPR is RO
1188 } else {
1189 // CBPR is RW
1190 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1191
1192 if (inSecureState()) {
1193 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1194 } else {
1195 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1196 }
1197 }
1198 } else {
1199 // CBPR is RW
1200 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1201 }
1202
1203 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1204
1205 setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
1206 return;
1207 }
1208
1209 // Virtual Control Register
1210 case MISCREG_ICV_CTLR_EL1: {
1211 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1212 ICV_CTLR_EL1 icv_ctlr_el1 =
1213 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1214 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1215 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1216 val = icv_ctlr_el1;
1217
1218 // Aliases
1219 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1220 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1221 ICH_VMCR_EL2 ich_vmcr_el2 =
1222 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1223 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1224 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1225 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1226 break;
1227 }
1228
1229 // Control Register EL3
1230 case MISCREG_ICC_MCTLR:
1231 case MISCREG_ICC_CTLR_EL3: {
1232 /*
1233 * ExtRange is RO.
1234 * RSS is RO.
1235 * nDS is RO.
1236 * A3V is RO.
1237 * SEIS is RO.
1238 * IDbits is RO.
1239 * PRIbits is RO.
1240 * PMHE is RAO/WI, priority-based routing is always used.
1241 */
1242 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1243
1244 // Aliases
1245 if (haveEL(EL3))
1246 {
1247 ICC_CTLR_EL1 icc_ctlr_el1_s =
1248 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1249 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1250 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1251
1252 // ICC_CTLR_EL1(NS).EOImode is an alias of
1253 // ICC_CTLR_EL3.EOImode_EL1NS
1254 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1255 // ICC_CTLR_EL1(S).EOImode is an alias of
1256 // ICC_CTLR_EL3.EOImode_EL1S
1257 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1258 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1259 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1260 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1261 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1262
1263 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1264 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1265 icc_ctlr_el1_ns);
1266 }
1267
1268 ICC_CTLR_EL3 icc_ctlr_el3 =
1269 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1270
1271 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1272 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1273 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1274 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1275 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1276 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1277
1278 val = icc_ctlr_el3;
1279 break;
1280 }
1281
1282 // Priority Mask Register
1283 case MISCREG_ICC_PMR:
1284 case MISCREG_ICC_PMR_EL1: {
1285 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1286 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1287 }
1288
1289 val &= 0xff;
1290 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1291
1292 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1293 // Spec section 4.8.1
1294 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1295 RegVal old_icc_pmr_el1 =
1296 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1297
1298 if (!(old_icc_pmr_el1 & 0x80)) {
1299 // If the current priority mask value is in the range of
1300 // 0x00-0x7F then WI
1301 return;
1302 }
1303
1304 // If the current priority mask value is in the range of
1305 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1306 // based on the Non-secure read of the priority mask value
1307 // written to the register.
1308
1309 val = (val >> 1) | 0x80;
1310 }
1311
1312 val &= ~0U << (8 - PRIORITY_BITS);
1313 break;
1314 }
1315
1316 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1317 ICH_VMCR_EL2 ich_vmcr_el2 =
1318 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1319 ich_vmcr_el2.VPMR = val & 0xff;
1320
1321 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1322 virtualUpdate();
1323 return;
1324 }
1325
1326 // Interrupt Group 0 Enable Register EL1
1327 case MISCREG_ICC_IGRPEN0:
1328 case MISCREG_ICC_IGRPEN0_EL1: {
1329 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1330 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1331 }
1332
1333 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1334 updateDistributor();
1335 return;
1336 }
1337
1338 // Virtual Interrupt Group 0 Enable register
1339 case MISCREG_ICV_IGRPEN0_EL1: {
1340 bool enable = val & 0x1;
1341 ICH_VMCR_EL2 ich_vmcr_el2 =
1342 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1343 ich_vmcr_el2.VENG0 = enable;
1344 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1345 virtualUpdate();
1346 return;
1347 }
1348
1349 // Interrupt Group 1 Enable register EL1
1350 case MISCREG_ICC_IGRPEN1:
1351 case MISCREG_ICC_IGRPEN1_EL1: {
1352 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1353 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1354 }
1355
|
1347 if (haveEL(EL3)) {
1348 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1349 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1350 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1351
1352 if (inSecureState()) {
1353 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1354 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1355 } else {
1356 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1357 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1358 }
1359
1360 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1361 icc_igrpen1_el3);
1362 }
1363
| |
1364 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1365 updateDistributor();
1366 return;
1367 }
1368
1369 // Virtual Interrupt Group 1 Enable register
1370 case MISCREG_ICV_IGRPEN1_EL1: {
1371 bool enable = val & 0x1;
1372 ICH_VMCR_EL2 ich_vmcr_el2 =
1373 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1374 ich_vmcr_el2.VENG1 = enable;
1375 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1376 virtualUpdate();
1377 return;
1378 }
1379
1380 // Interrupt Group 1 Enable register
1381 case MISCREG_ICC_MGRPEN1:
1382 case MISCREG_ICC_IGRPEN1_EL3: {
1383 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
| 1356 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1357 updateDistributor();
1358 return;
1359 }
1360
1361 // Virtual Interrupt Group 1 Enable register
1362 case MISCREG_ICV_IGRPEN1_EL1: {
1363 bool enable = val & 0x1;
1364 ICH_VMCR_EL2 ich_vmcr_el2 =
1365 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1366 ich_vmcr_el2.VENG1 = enable;
1367 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1368 virtualUpdate();
1369 return;
1370 }
1371
1372 // Interrupt Group 1 Enable register
1373 case MISCREG_ICC_MGRPEN1:
1374 case MISCREG_ICC_IGRPEN1_EL3: {
1375 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
|
1384 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1385 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
| |
1386
| 1376
|
1387 if (inSecureState()) {
1388 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1389 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1390 } else {
1391 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1392 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1393 }
1394
1395 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1396 break;
| 1377 isa->setMiscRegNoEffect(
1378 MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
1379 isa->setMiscRegNoEffect(
1380 MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
1381 return;
|
1397 }
1398
1399 // Software Generated Interrupt Group 0 Register
1400 case MISCREG_ICC_SGI0R:
1401 case MISCREG_ICC_SGI0R_EL1:
1402 generateSGI(val, Gicv3::G0S);
1403 break;
1404
1405 // Software Generated Interrupt Group 1 Register
1406 case MISCREG_ICC_SGI1R:
1407 case MISCREG_ICC_SGI1R_EL1: {
1408 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
1409
1410 generateSGI(val, group);
1411 break;
1412 }
1413
1414 // Alias Software Generated Interrupt Group 1 Register
1415 case MISCREG_ICC_ASGI1R:
1416 case MISCREG_ICC_ASGI1R_EL1: {
1417 Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S;
1418
1419 generateSGI(val, group);
1420 break;
1421 }
1422
1423 // System Register Enable Register EL1
1424 case MISCREG_ICC_SRE:
1425 case MISCREG_ICC_SRE_EL1:
1426 // System Register Enable Register EL2
1427 case MISCREG_ICC_HSRE:
1428 case MISCREG_ICC_SRE_EL2:
1429 // System Register Enable Register EL3
1430 case MISCREG_ICC_MSRE:
1431 case MISCREG_ICC_SRE_EL3:
1432 // All bits are RAO/WI
1433 return;
1434
1435 // Hyp Control Register
1436 case MISCREG_ICH_HCR:
1437 case MISCREG_ICH_HCR_EL2: {
1438 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1439 ICH_HCR_EL2 ich_hcr_el2 =
1440 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1441
1442 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1443 {
1444 // EOIcount - Permitted behaviors are:
1445 // - Increment EOIcount.
1446 // - Leave EOIcount unchanged.
1447 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1448 }
1449
1450 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1451 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1452 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1453 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1454 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1455 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1456 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1457 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1458 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1459 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1460 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1461 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1462 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1463 val = ich_hcr_el2;
1464 do_virtual_update = true;
1465 break;
1466 }
1467
1468 // List Registers
1469 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1470 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1471 ICH_LRC requested_ich_lrc = val;
1472 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1473
1474 ich_lrc.State = requested_ich_lrc.State;
1475 ich_lrc.HW = requested_ich_lrc.HW;
1476 ich_lrc.Group = requested_ich_lrc.Group;
1477
1478 // Priority, bits [23:16]
1479 // At least five bits must be implemented.
1480 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1481 // We implement 5 bits.
1482 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1483 (ich_lrc.Priority & 0x07);
1484
1485 // pINTID, bits [12:0]
1486 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1487 // - Bits[12:10] : RES0.
1488 // - Bit[9] : EOI.
1489 // - Bits[8:0] : RES0.
1490 // When ICH_LR<n>.HW is 1:
1491 // - This field is only required to implement enough bits to hold a
1492 // valid value for the implemented INTID size. Any unused higher
1493 // order bits are RES0.
1494 if (requested_ich_lrc.HW == 0) {
1495 ich_lrc.EOI = requested_ich_lrc.EOI;
1496 } else {
1497 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1498 }
1499
1500 val = ich_lrc;
1501 do_virtual_update = true;
1502 break;
1503 }
1504
1505 // List Registers
1506 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1507 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1508 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1509 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1510 do_virtual_update = true;
1511 break;
1512 }
1513
1514 // List Registers
1515 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1516 ICH_LR_EL2 requested_ich_lr_el2 = val;
1517 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1518
1519 ich_lr_el2.State = requested_ich_lr_el2.State;
1520 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1521 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1522
1523 // Priority, bits [55:48]
1524 // At least five bits must be implemented.
1525 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1526 // We implement 5 bits.
1527 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1528 (ich_lr_el2.Priority & 0x07);
1529
1530 // pINTID, bits [44:32]
1531 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1532 // - Bits[44:42] : RES0.
1533 // - Bit[41] : EOI.
1534 // - Bits[40:32] : RES0.
1535 // When ICH_LR<n>_EL2.HW is 1:
1536 // - This field is only required to implement enough bits to hold a
1537 // valid value for the implemented INTID size. Any unused higher
1538 // order bits are RES0.
1539 if (requested_ich_lr_el2.HW == 0) {
1540 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1541 } else {
1542 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1543 }
1544
1545 // vINTID, bits [31:0]
1546 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1547 // though at least 16 bits must be implemented.
1548 // Unimplemented bits are RES0.
1549 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1550
1551 val = ich_lr_el2;
1552 do_virtual_update = true;
1553 break;
1554 }
1555
1556 // Virtual Machine Control Register
1557 case MISCREG_ICH_VMCR:
1558 case MISCREG_ICH_VMCR_EL2: {
1559 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1560 ICH_VMCR_EL2 ich_vmcr_el2 =
1561 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1562 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1563 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1564
1565 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1566 ich_vmcr_el2.VBPR0 = min_vpr0;
1567 } else {
1568 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1569 }
1570
1571 uint8_t min_vpr1 = min_vpr0 + 1;
1572
1573 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1574 ich_vmcr_el2.VBPR1 = min_vpr1;
1575 } else {
1576 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1577 }
1578
1579 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1580 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1581 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1582 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1583 val = ich_vmcr_el2;
1584 break;
1585 }
1586
1587 // Hyp Active Priorities Group 0 Registers
1588 case MISCREG_ICH_AP0R0:
1589 case MISCREG_ICH_AP0R0_EL2:
1590 break;
1591
1592 // only implemented if supporting 6 or more bits of priority
1593 case MISCREG_ICH_AP0R1:
1594 case MISCREG_ICH_AP0R1_EL2:
1595 // only implemented if supporting 7 or more bits of priority
1596 case MISCREG_ICH_AP0R2:
1597 case MISCREG_ICH_AP0R2_EL2:
1598 // only implemented if supporting 7 or more bits of priority
1599 case MISCREG_ICH_AP0R3:
1600 case MISCREG_ICH_AP0R3_EL2:
1601 // Unimplemented registers are RAZ/WI
1602 return;
1603
1604 // Hyp Active Priorities Group 1 Registers
1605 case MISCREG_ICH_AP1R0:
1606 case MISCREG_ICH_AP1R0_EL2:
1607 break;
1608
1609 // only implemented if supporting 6 or more bits of priority
1610 case MISCREG_ICH_AP1R1:
1611 case MISCREG_ICH_AP1R1_EL2:
1612 // only implemented if supporting 7 or more bits of priority
1613 case MISCREG_ICH_AP1R2:
1614 case MISCREG_ICH_AP1R2_EL2:
1615 // only implemented if supporting 7 or more bits of priority
1616 case MISCREG_ICH_AP1R3:
1617 case MISCREG_ICH_AP1R3_EL2:
1618 // Unimplemented registers are RAZ/WI
1619 return;
1620
1621 default:
1622 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1623 misc_reg, miscRegName[misc_reg]);
1624 }
1625
1626 isa->setMiscRegNoEffect(misc_reg, val);
1627
1628 if (do_virtual_update) {
1629 virtualUpdate();
1630 }
1631}
1632
1633RegVal
1634Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
1635{
1636 return isa->readMiscRegNoEffect(
1637 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
1638}
1639
1640void
1641Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1642{
1643 isa->setMiscRegNoEffect(
1644 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
1645}
1646
1647int
1648Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1649{
1650 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1651 ICH_LR_EL2 ich_lr_el2 =
1652 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1653
1654 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1655 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1656 (ich_lr_el2.vINTID == int_id)) {
1657 return lr_idx;
1658 }
1659 }
1660
1661 return -1;
1662}
1663
1664uint32_t
1665Gicv3CPUInterface::getHPPIR0() const
1666{
1667 if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1668 return Gicv3::INTID_SPURIOUS;
1669 }
1670
1671 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1672
1673 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1674 // interrupt for the other state pending
1675 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1676 }
1677
1678 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1679 return Gicv3::INTID_SPURIOUS;
1680 }
1681
1682 if (irq_is_secure && !inSecureState()) {
1683 // Secure interrupts not visible in Non-secure
1684 return Gicv3::INTID_SPURIOUS;
1685 }
1686
1687 return hppi.intid;
1688}
1689
1690uint32_t
1691Gicv3CPUInterface::getHPPIR1() const
1692{
1693 if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1694 return Gicv3::INTID_SPURIOUS;
1695 }
1696
1697 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1698 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1699 if (hppi.group == Gicv3::G0S) {
1700 return Gicv3::INTID_SECURE;
1701 } else if (hppi.group == Gicv3::G1NS) {
1702 return Gicv3::INTID_NONSECURE;
1703 }
1704 }
1705
1706 if (hppi.group == Gicv3::G0S) {
1707 return Gicv3::INTID_SPURIOUS;
1708 }
1709
1710 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1711
1712 if (irq_is_secure) {
1713 if (!inSecureState()) {
1714 // Secure interrupts not visible in Non-secure
1715 return Gicv3::INTID_SPURIOUS;
1716 }
1717 } else if (!isEL3OrMon() && inSecureState()) {
1718 // Group 1 non-secure interrupts not visible in Secure EL1
1719 return Gicv3::INTID_SPURIOUS;
1720 }
1721
1722 return hppi.intid;
1723}
1724
1725void
1726Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1727{
1728 int apr_misc_reg = 0;
1729
1730 switch (group) {
1731 case Gicv3::G0S:
1732 apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
1733 break;
1734 case Gicv3::G1S:
1735 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
1736 break;
1737 case Gicv3::G1NS:
1738 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
1739 break;
1740 default:
1741 panic("Invalid Gicv3::GroupId");
1742 }
1743
1744 RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1745
1746 if (apr) {
1747 apr &= apr - 1;
1748 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1749 }
1750
1751 update();
1752}
1753
1754uint8_t
1755Gicv3CPUInterface::virtualDropPriority()
1756{
1757 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1758
1759 for (int i = 0; i < apr_max; i++) {
1760 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1761 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1762
1763 if (!vapr0 && !vapr1) {
1764 continue;
1765 }
1766
1767 int vapr0_count = ctz32(vapr0);
1768 int vapr1_count = ctz32(vapr1);
1769
1770 if (vapr0_count <= vapr1_count) {
1771 vapr0 &= vapr0 - 1;
1772 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1773 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1774 } else {
1775 vapr1 &= vapr1 - 1;
1776 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1777 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1778 }
1779 }
1780
1781 return 0xff;
1782}
1783
1784void
1785Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1786{
1787 uint8_t aff3 = bits(val, 55, 48);
1788 uint8_t aff2 = bits(val, 39, 32);
1789 uint8_t aff1 = bits(val, 23, 16);;
1790 uint16_t target_list = bits(val, 15, 0);
1791 uint32_t int_id = bits(val, 27, 24);
1792 bool irm = bits(val, 40, 40);
1793 uint8_t rs = bits(val, 47, 44);
1794
1795 bool ns = !inSecureState();
1796
1797 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1798 Gicv3Redistributor * redistributor_i =
1799 gic->getRedistributor(i);
1800 uint32_t affinity_i = redistributor_i->getAffinity();
1801
1802 if (irm) {
1803 // Interrupts routed to all PEs in the system,
1804 // excluding "self"
1805 if (affinity_i == redistributor->getAffinity()) {
1806 continue;
1807 }
1808 } else {
1809 // Interrupts routed to the PEs specified by
1810 // Aff3.Aff2.Aff1.<target list>
1811 if ((affinity_i >> 8) !=
1812 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1813 continue;
1814 }
1815
1816 uint8_t aff0_i = bits(affinity_i, 7, 0);
1817
1818 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1819 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1820 continue;
1821 }
1822 }
1823
1824 redistributor_i->sendSGI(int_id, group, ns);
1825 }
1826}
1827
1828void
1829Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1830{
1831 // Update active priority registers.
1832 uint32_t prio = hppi.prio & 0xf8;
1833 int apr_bit = prio >> (8 - PRIORITY_BITS);
1834 int reg_bit = apr_bit % 32;
1835
1836 int apr_idx = 0;
1837 switch (group) {
1838 case Gicv3::G0S:
1839 apr_idx = MISCREG_ICC_AP0R0_EL1;
1840 break;
1841 case Gicv3::G1S:
1842 apr_idx = MISCREG_ICC_AP1R0_EL1_S;
1843 break;
1844 case Gicv3::G1NS:
1845 apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
1846 break;
1847 default:
1848 panic("Invalid Gicv3::GroupId");
1849 }
1850
1851 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1852 apr |= (1 << reg_bit);
1853 isa->setMiscRegNoEffect(apr_idx, apr);
1854
1855 // Move interrupt state from pending to active.
1856 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1857 // SGI or PPI, redistributor
1858 redistributor->activateIRQ(int_id);
1859 } else if (int_id < Gicv3::INTID_SECURE) {
1860 // SPI, distributor
1861 distributor->activateIRQ(int_id);
1862 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
1863 // LPI, Redistributor
1864 redistributor->setClrLPI(int_id, false);
1865 }
1866
1867 // By setting the priority to 0xff we are effectively
1868 // making the int_id not pending anymore at the cpu
1869 // interface.
1870 hppi.prio = 0xff;
1871 updateDistributor();
1872}
1873
1874void
1875Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1876{
1877 // Update active priority registers.
1878 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1879 lr_idx);
1880 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1881 uint8_t prio = ich_lr_el.Priority & 0xf8;
1882 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1883 int reg_no = apr_bit / 32;
1884 int reg_bit = apr_bit % 32;
1885 int apr_idx = group == Gicv3::G0S ?
1886 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1887 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1888 apr |= (1 << reg_bit);
1889 isa->setMiscRegNoEffect(apr_idx, apr);
1890 // Move interrupt state from pending to active.
1891 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1892 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1893}
1894
1895void
1896Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1897{
1898 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1899 // SGI or PPI, redistributor
1900 redistributor->deactivateIRQ(int_id);
1901 } else if (int_id < Gicv3::INTID_SECURE) {
1902 // SPI, distributor
1903 distributor->deactivateIRQ(int_id);
1904 }
1905
1906 updateDistributor();
1907}
1908
1909void
1910Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1911{
1912 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1913 lr_idx);
1914
1915 if (ich_lr_el2.HW) {
1916 // Deactivate the associated physical interrupt
1917 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1918 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1919 distributor->getIntGroup(ich_lr_el2.pINTID) :
1920 redistributor->getIntGroup(ich_lr_el2.pINTID);
1921 deactivateIRQ(ich_lr_el2.pINTID, group);
1922 }
1923 }
1924
1925 // Remove the active bit
1926 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1927 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1928}
1929
1930/*
1931 * Returns the priority group field for the current BPR value for the group.
1932 * GroupBits() Pseudocode from spec.
1933 */
1934uint32_t
1935Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
1936{
1937 ICC_CTLR_EL1 icc_ctlr_el1_s =
1938 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1939 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1940 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1941
1942 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1943 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1944 group = Gicv3::G0S;
1945 }
1946
1947 int bpr;
1948
1949 if (group == Gicv3::G0S) {
1950 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
1951 } else if (group == Gicv3::G1S) {
1952 bpr = bpr1(Gicv3::G1S) & 0x7;
1953 } else {
1954 bpr = bpr1(Gicv3::G1NS) & 0x7;
1955 }
1956
1957 if (group == Gicv3::G1NS) {
1958 assert(bpr > 0);
1959 bpr--;
1960 }
1961
1962 return ~0U << (bpr + 1);
1963}
1964
1965uint32_t
1966Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1967{
1968 ICH_VMCR_EL2 ich_vmcr_el2 =
1969 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1970
1971 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1972 group = Gicv3::G0S;
1973 }
1974
1975 int bpr;
1976
1977 if (group == Gicv3::G0S) {
1978 bpr = ich_vmcr_el2.VBPR0;
1979 } else {
1980 bpr = ich_vmcr_el2.VBPR1;
1981 }
1982
1983 if (group == Gicv3::G1NS) {
1984 assert(bpr > 0);
1985 bpr--;
1986 }
1987
1988 return ~0U << (bpr + 1);
1989}
1990
1991bool
1992Gicv3CPUInterface::isEOISplitMode() const
1993{
1994 if (isEL3OrMon()) {
1995 ICC_CTLR_EL3 icc_ctlr_el3 =
1996 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1997 return icc_ctlr_el3.EOImode_EL3;
1998 } else {
1999 ICC_CTLR_EL1 icc_ctlr_el1 = 0;
2000 if (inSecureState())
2001 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
2002 else
2003 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
2004 return icc_ctlr_el1.EOImode;
2005 }
2006}
2007
2008bool
2009Gicv3CPUInterface::virtualIsEOISplitMode() const
2010{
2011 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2012 return ich_vmcr_el2.VEOIM;
2013}
2014
2015int
2016Gicv3CPUInterface::highestActiveGroup() const
2017{
2018 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
2019 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
2020 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
2021
2022 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
2023 return Gicv3::G1NS;
2024 }
2025
2026 if (gq_ctz < g0_ctz) {
2027 return Gicv3::G1S;
2028 }
2029
2030 if (g0_ctz < 32) {
2031 return Gicv3::G0S;
2032 }
2033
2034 return -1;
2035}
2036
2037void
2038Gicv3CPUInterface::updateDistributor()
2039{
2040 distributor->update();
2041}
2042
2043void
2044Gicv3CPUInterface::update()
2045{
2046 bool signal_IRQ = false;
2047 bool signal_FIQ = false;
2048
2049 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2050 /*
2051 * Secure enabled GIC sending a G1S IRQ to a secure disabled
2052 * CPU -> send G0 IRQ
2053 */
2054 hppi.group = Gicv3::G0S;
2055 }
2056
2057 if (hppiCanPreempt()) {
2058 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
2059 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
2060 "posting int as %d!\n", int_type);
2061 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
2062 }
2063
2064 if (signal_IRQ) {
2065 gic->postInt(cpuId, ArmISA::INT_IRQ);
2066 } else {
2067 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
2068 }
2069
2070 if (signal_FIQ) {
2071 gic->postInt(cpuId, ArmISA::INT_FIQ);
2072 } else {
2073 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
2074 }
2075}
2076
2077void
2078Gicv3CPUInterface::virtualUpdate()
2079{
2080 bool signal_IRQ = false;
2081 bool signal_FIQ = false;
2082 int lr_idx = getHPPVILR();
2083
2084 if (lr_idx >= 0) {
2085 ICH_LR_EL2 ich_lr_el2 =
2086 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2087
2088 if (hppviCanPreempt(lr_idx)) {
2089 if (ich_lr_el2.Group) {
2090 signal_IRQ = true;
2091 } else {
2092 signal_FIQ = true;
2093 }
2094 }
2095 }
2096
2097 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2098
2099 if (ich_hcr_el2.En) {
2100 if (maintenanceInterruptStatus()) {
2101 maintenanceInterrupt->raise();
2102 }
2103 }
2104
2105 if (signal_IRQ) {
2106 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2107 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2108 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2109 } else {
2110 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2111 }
2112
2113 if (signal_FIQ) {
2114 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2115 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2116 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2117 } else {
2118 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2119 }
2120}
2121
2122// Returns the index of the LR with the HPPI
2123int
2124Gicv3CPUInterface::getHPPVILR() const
2125{
2126 int idx = -1;
2127 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2128
2129 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2130 // VG0 and VG1 disabled...
2131 return idx;
2132 }
2133
2134 uint8_t highest_prio = 0xff;
2135
2136 for (int i = 0; i < 16; i++) {
2137 ICH_LR_EL2 ich_lr_el2 =
2138 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2139
2140 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2141 continue;
2142 }
2143
2144 if (ich_lr_el2.Group) {
2145 // VG1
2146 if (!ich_vmcr_el2.VENG1) {
2147 continue;
2148 }
2149 } else {
2150 // VG0
2151 if (!ich_vmcr_el2.VENG0) {
2152 continue;
2153 }
2154 }
2155
2156 uint8_t prio = ich_lr_el2.Priority;
2157
2158 if (prio < highest_prio) {
2159 highest_prio = prio;
2160 idx = i;
2161 }
2162 }
2163
2164 return idx;
2165}
2166
2167bool
2168Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2169{
2170 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2171 if (!ich_hcr_el2.En) {
2172 // virtual interface is disabled
2173 return false;
2174 }
2175
2176 ICH_LR_EL2 ich_lr_el2 =
2177 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2178 uint8_t prio = ich_lr_el2.Priority;
2179 uint8_t vpmr =
2180 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2181
2182 if (prio >= vpmr) {
2183 // prioriry masked
2184 return false;
2185 }
2186
2187 uint8_t rprio = virtualHighestActivePriority();
2188
2189 if (rprio == 0xff) {
2190 return true;
2191 }
2192
2193 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2194 uint32_t prio_mask = virtualGroupPriorityMask(group);
2195
2196 if ((prio & prio_mask) < (rprio & prio_mask)) {
2197 return true;
2198 }
2199
2200 return false;
2201}
2202
2203uint8_t
2204Gicv3CPUInterface::virtualHighestActivePriority() const
2205{
2206 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2207
2208 for (int i = 0; i < num_aprs; i++) {
2209 RegVal vapr =
2210 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2211 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2212
2213 if (!vapr) {
2214 continue;
2215 }
2216
2217 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2218 }
2219
2220 // no active interrups, return idle priority
2221 return 0xff;
2222}
2223
2224void
2225Gicv3CPUInterface::virtualIncrementEOICount()
2226{
2227 // Increment the EOICOUNT field in ICH_HCR_EL2
2228 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2229 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2230 EOI_cout++;
2231 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2232 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2233}
2234
2235// spec section 4.6.2
2236ArmISA::InterruptTypes
2237Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2238{
2239 bool is_fiq = false;
2240
2241 switch (group) {
2242 case Gicv3::G0S:
2243 is_fiq = true;
2244 break;
2245
2246 case Gicv3::G1S:
2247 is_fiq = (distributor->DS == 0) &&
2248 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2249 break;
2250
2251 case Gicv3::G1NS:
2252 is_fiq = (distributor->DS == 0) && inSecureState();
2253 break;
2254
2255 default:
2256 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2257 }
2258
2259 if (is_fiq) {
2260 return ArmISA::INT_FIQ;
2261 } else {
2262 return ArmISA::INT_IRQ;
2263 }
2264}
2265
2266bool
2267Gicv3CPUInterface::hppiCanPreempt()
2268{
2269 if (hppi.prio == 0xff) {
2270 // there is no pending interrupt
2271 return false;
2272 }
2273
2274 if (!groupEnabled(hppi.group)) {
2275 // group disabled at CPU interface
2276 return false;
2277 }
2278
2279 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2280 // priority masked
2281 return false;
2282 }
2283
2284 uint8_t rprio = highestActivePriority();
2285
2286 if (rprio == 0xff) {
2287 return true;
2288 }
2289
2290 uint32_t prio_mask = groupPriorityMask(hppi.group);
2291
2292 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2293 return true;
2294 }
2295
2296 return false;
2297}
2298
2299uint8_t
2300Gicv3CPUInterface::highestActivePriority() const
2301{
2302 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2303 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2304 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2305
2306 if (apr) {
2307 return ctz32(apr) << (GIC_MIN_BPR + 1);
2308 }
2309
2310 // no active interrups, return idle priority
2311 return 0xff;
2312}
2313
2314bool
2315Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2316{
2317 switch (group) {
2318 case Gicv3::G0S: {
2319 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2320 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2321 return icc_igrpen0_el1.Enable && distributor->EnableGrp0;
2322 }
2323
2324 case Gicv3::G1S: {
2325 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2326 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2327 return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S;
2328 }
2329
2330 case Gicv3::G1NS: {
2331 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2332 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2333 return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS;
2334 }
2335
2336 default:
2337 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2338 }
2339}
2340
2341bool
2342Gicv3CPUInterface::inSecureState() const
2343{
2344 if (!gic->getSystem()->haveSecurity()) {
2345 return false;
2346 }
2347
2348 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2349 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2350 return ArmISA::inSecureState(scr, cpsr);
2351}
2352
2353int
2354Gicv3CPUInterface::currEL() const
2355{
2356 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2357 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2358
2359 if (is_64) {
2360 return (ExceptionLevel)(uint8_t) cpsr.el;
2361 } else {
2362 switch (cpsr.mode) {
2363 case MODE_USER:
2364 return 0;
2365
2366 case MODE_HYP:
2367 return 2;
2368
2369 case MODE_MON:
2370 return 3;
2371
2372 default:
2373 return 1;
2374 }
2375 }
2376}
2377
2378bool
2379Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2380{
2381 switch (el) {
2382 case EL0:
2383 case EL1:
2384 return true;
2385
2386 case EL2:
2387 return gic->getSystem()->haveVirtualization();
2388
2389 case EL3:
2390 return gic->getSystem()->haveSecurity();
2391
2392 default:
2393 warn("Unimplemented Exception Level\n");
2394 return false;
2395 }
2396}
2397
2398bool
2399Gicv3CPUInterface::isSecureBelowEL3() const
2400{
2401 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2402 return haveEL(EL3) && scr.ns == 0;
2403}
2404
2405bool
2406Gicv3CPUInterface::isAA64() const
2407{
2408 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2409 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2410}
2411
2412bool
2413Gicv3CPUInterface::isEL3OrMon() const
2414{
2415 if (haveEL(EL3)) {
2416 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2417 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2418
2419 if (is_64 && (cpsr.el == EL3)) {
2420 return true;
2421 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2422 return true;
2423 }
2424 }
2425
2426 return false;
2427}
2428
2429// Computes ICH_EISR_EL2
2430uint64_t
2431Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2432{
2433 // ICH_EISR_EL2
2434 // Bits [63:16] - RES0
2435 // Status<n>, bit [n], for n = 0 to 15
2436 // EOI maintenance interrupt status bit for List register <n>:
2437 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2438 // maintenance interrupt.
2439 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2440 // interrupt that has not been handled.
2441 //
2442 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2443 // of the following are true:
2444 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2445 // - ICH_LR<n>_EL2.HW is 0.
2446 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2447
2448 uint64_t value = 0;
2449
2450 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2451 ICH_LR_EL2 ich_lr_el2 =
2452 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2453
2454 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2455 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2456 value |= (1 << lr_idx);
2457 }
2458 }
2459
2460 return value;
2461}
2462
2463Gicv3CPUInterface::ICH_MISR_EL2
2464Gicv3CPUInterface::maintenanceInterruptStatus() const
2465{
2466 // Comments are copied from SPEC section 9.4.7 (ID012119)
2467 ICH_MISR_EL2 ich_misr_el2 = 0;
2468 ICH_HCR_EL2 ich_hcr_el2 =
2469 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2470 ICH_VMCR_EL2 ich_vmcr_el2 =
2471 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2472
2473 // End Of Interrupt. [bit 0]
2474 // This maintenance interrupt is asserted when at least one bit in
2475 // ICH_EISR_EL2 is 1.
2476
2477 if (eoiMaintenanceInterruptStatus()) {
2478 ich_misr_el2.EOI = 1;
2479 }
2480
2481 // Underflow. [bit 1]
2482 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2483 // zero or one of the List register entries are marked as a valid
2484 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2485 // do not equal 0x0.
2486 uint32_t num_valid_interrupts = 0;
2487 uint32_t num_pending_interrupts = 0;
2488
2489 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2490 ICH_LR_EL2 ich_lr_el2 =
2491 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2492
2493 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2494 num_valid_interrupts++;
2495 }
2496
2497 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2498 num_pending_interrupts++;
2499 }
2500 }
2501
2502 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2503 ich_misr_el2.U = 1;
2504 }
2505
2506 // List Register Entry Not Present. [bit 2]
2507 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2508 // and ICH_HCR_EL2.EOIcount is non-zero.
2509 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2510 ich_misr_el2.LRENP = 1;
2511 }
2512
2513 // No Pending. [bit 3]
2514 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2515 // no List register is in pending state.
2516 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2517 ich_misr_el2.NP = 1;
2518 }
2519
2520 // vPE Group 0 Enabled. [bit 4]
2521 // This maintenance interrupt is asserted when
2522 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2523 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2524 ich_misr_el2.VGrp0E = 1;
2525 }
2526
2527 // vPE Group 0 Disabled. [bit 5]
2528 // This maintenance interrupt is asserted when
2529 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2530 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2531 ich_misr_el2.VGrp0D = 1;
2532 }
2533
2534 // vPE Group 1 Enabled. [bit 6]
2535 // This maintenance interrupt is asserted when
2536 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2537 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2538 ich_misr_el2.VGrp1E = 1;
2539 }
2540
2541 // vPE Group 1 Disabled. [bit 7]
2542 // This maintenance interrupt is asserted when
2543 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2544 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2545 ich_misr_el2.VGrp1D = 1;
2546 }
2547
2548 return ich_misr_el2;
2549}
2550
2551RegVal
2552Gicv3CPUInterface::bpr1(Gicv3::GroupId group)
2553{
2554 bool hcr_imo = getHCREL2IMO();
2555 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
2556 return readMiscReg(MISCREG_ICV_BPR1_EL1);
2557 }
2558
2559 RegVal bpr = 0;
2560
2561 if (group == Gicv3::G1S) {
2562 ICC_CTLR_EL1 icc_ctlr_el1_s =
2563 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
2564
2565 if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
2566 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
2567 } else {
2568 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S);
2569 bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR;
2570 }
2571 } else if (group == Gicv3::G1NS) {
2572 ICC_CTLR_EL1 icc_ctlr_el1_ns =
2573 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
2574
2575 // Check if EL3 is implemented and this is a non secure accesses at
2576 // EL1 and EL2
2577 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
2578 // Reads return BPR0 + 1 saturated to 7, WI
2579 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1;
2580 bpr = bpr < 7 ? bpr : 7;
2581 } else {
2582 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS);
2583 bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS;
2584 }
2585 } else {
2586 panic("Should be used with G1S and G1NS only\n");
2587 }
2588
2589 return bpr;
2590}
2591
2592void
2593Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2594{
2595 SERIALIZE_SCALAR(hppi.intid);
2596 SERIALIZE_SCALAR(hppi.prio);
2597 SERIALIZE_ENUM(hppi.group);
2598}
2599
2600void
2601Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2602{
2603 UNSERIALIZE_SCALAR(hppi.intid);
2604 UNSERIALIZE_SCALAR(hppi.prio);
2605 UNSERIALIZE_ENUM(hppi.group);
2606}
| 1382 }
1383
1384 // Software Generated Interrupt Group 0 Register
1385 case MISCREG_ICC_SGI0R:
1386 case MISCREG_ICC_SGI0R_EL1:
1387 generateSGI(val, Gicv3::G0S);
1388 break;
1389
1390 // Software Generated Interrupt Group 1 Register
1391 case MISCREG_ICC_SGI1R:
1392 case MISCREG_ICC_SGI1R_EL1: {
1393 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
1394
1395 generateSGI(val, group);
1396 break;
1397 }
1398
1399 // Alias Software Generated Interrupt Group 1 Register
1400 case MISCREG_ICC_ASGI1R:
1401 case MISCREG_ICC_ASGI1R_EL1: {
1402 Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S;
1403
1404 generateSGI(val, group);
1405 break;
1406 }
1407
1408 // System Register Enable Register EL1
1409 case MISCREG_ICC_SRE:
1410 case MISCREG_ICC_SRE_EL1:
1411 // System Register Enable Register EL2
1412 case MISCREG_ICC_HSRE:
1413 case MISCREG_ICC_SRE_EL2:
1414 // System Register Enable Register EL3
1415 case MISCREG_ICC_MSRE:
1416 case MISCREG_ICC_SRE_EL3:
1417 // All bits are RAO/WI
1418 return;
1419
1420 // Hyp Control Register
1421 case MISCREG_ICH_HCR:
1422 case MISCREG_ICH_HCR_EL2: {
1423 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1424 ICH_HCR_EL2 ich_hcr_el2 =
1425 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1426
1427 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1428 {
1429 // EOIcount - Permitted behaviors are:
1430 // - Increment EOIcount.
1431 // - Leave EOIcount unchanged.
1432 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1433 }
1434
1435 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1436 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1437 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1438 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1439 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1440 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1441 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1442 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1443 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1444 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1445 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1446 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1447 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1448 val = ich_hcr_el2;
1449 do_virtual_update = true;
1450 break;
1451 }
1452
1453 // List Registers
1454 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1455 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1456 ICH_LRC requested_ich_lrc = val;
1457 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1458
1459 ich_lrc.State = requested_ich_lrc.State;
1460 ich_lrc.HW = requested_ich_lrc.HW;
1461 ich_lrc.Group = requested_ich_lrc.Group;
1462
1463 // Priority, bits [23:16]
1464 // At least five bits must be implemented.
1465 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1466 // We implement 5 bits.
1467 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1468 (ich_lrc.Priority & 0x07);
1469
1470 // pINTID, bits [12:0]
1471 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1472 // - Bits[12:10] : RES0.
1473 // - Bit[9] : EOI.
1474 // - Bits[8:0] : RES0.
1475 // When ICH_LR<n>.HW is 1:
1476 // - This field is only required to implement enough bits to hold a
1477 // valid value for the implemented INTID size. Any unused higher
1478 // order bits are RES0.
1479 if (requested_ich_lrc.HW == 0) {
1480 ich_lrc.EOI = requested_ich_lrc.EOI;
1481 } else {
1482 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1483 }
1484
1485 val = ich_lrc;
1486 do_virtual_update = true;
1487 break;
1488 }
1489
1490 // List Registers
1491 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1492 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1493 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1494 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1495 do_virtual_update = true;
1496 break;
1497 }
1498
1499 // List Registers
1500 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1501 ICH_LR_EL2 requested_ich_lr_el2 = val;
1502 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1503
1504 ich_lr_el2.State = requested_ich_lr_el2.State;
1505 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1506 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1507
1508 // Priority, bits [55:48]
1509 // At least five bits must be implemented.
1510 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1511 // We implement 5 bits.
1512 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1513 (ich_lr_el2.Priority & 0x07);
1514
1515 // pINTID, bits [44:32]
1516 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1517 // - Bits[44:42] : RES0.
1518 // - Bit[41] : EOI.
1519 // - Bits[40:32] : RES0.
1520 // When ICH_LR<n>_EL2.HW is 1:
1521 // - This field is only required to implement enough bits to hold a
1522 // valid value for the implemented INTID size. Any unused higher
1523 // order bits are RES0.
1524 if (requested_ich_lr_el2.HW == 0) {
1525 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1526 } else {
1527 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1528 }
1529
1530 // vINTID, bits [31:0]
1531 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1532 // though at least 16 bits must be implemented.
1533 // Unimplemented bits are RES0.
1534 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1535
1536 val = ich_lr_el2;
1537 do_virtual_update = true;
1538 break;
1539 }
1540
1541 // Virtual Machine Control Register
1542 case MISCREG_ICH_VMCR:
1543 case MISCREG_ICH_VMCR_EL2: {
1544 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1545 ICH_VMCR_EL2 ich_vmcr_el2 =
1546 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1547 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1548 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1549
1550 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1551 ich_vmcr_el2.VBPR0 = min_vpr0;
1552 } else {
1553 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1554 }
1555
1556 uint8_t min_vpr1 = min_vpr0 + 1;
1557
1558 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1559 ich_vmcr_el2.VBPR1 = min_vpr1;
1560 } else {
1561 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1562 }
1563
1564 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1565 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1566 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1567 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1568 val = ich_vmcr_el2;
1569 break;
1570 }
1571
1572 // Hyp Active Priorities Group 0 Registers
1573 case MISCREG_ICH_AP0R0:
1574 case MISCREG_ICH_AP0R0_EL2:
1575 break;
1576
1577 // only implemented if supporting 6 or more bits of priority
1578 case MISCREG_ICH_AP0R1:
1579 case MISCREG_ICH_AP0R1_EL2:
1580 // only implemented if supporting 7 or more bits of priority
1581 case MISCREG_ICH_AP0R2:
1582 case MISCREG_ICH_AP0R2_EL2:
1583 // only implemented if supporting 7 or more bits of priority
1584 case MISCREG_ICH_AP0R3:
1585 case MISCREG_ICH_AP0R3_EL2:
1586 // Unimplemented registers are RAZ/WI
1587 return;
1588
1589 // Hyp Active Priorities Group 1 Registers
1590 case MISCREG_ICH_AP1R0:
1591 case MISCREG_ICH_AP1R0_EL2:
1592 break;
1593
1594 // only implemented if supporting 6 or more bits of priority
1595 case MISCREG_ICH_AP1R1:
1596 case MISCREG_ICH_AP1R1_EL2:
1597 // only implemented if supporting 7 or more bits of priority
1598 case MISCREG_ICH_AP1R2:
1599 case MISCREG_ICH_AP1R2_EL2:
1600 // only implemented if supporting 7 or more bits of priority
1601 case MISCREG_ICH_AP1R3:
1602 case MISCREG_ICH_AP1R3_EL2:
1603 // Unimplemented registers are RAZ/WI
1604 return;
1605
1606 default:
1607 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1608 misc_reg, miscRegName[misc_reg]);
1609 }
1610
1611 isa->setMiscRegNoEffect(misc_reg, val);
1612
1613 if (do_virtual_update) {
1614 virtualUpdate();
1615 }
1616}
1617
1618RegVal
1619Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
1620{
1621 return isa->readMiscRegNoEffect(
1622 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
1623}
1624
1625void
1626Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1627{
1628 isa->setMiscRegNoEffect(
1629 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
1630}
1631
1632int
1633Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1634{
1635 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1636 ICH_LR_EL2 ich_lr_el2 =
1637 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1638
1639 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1640 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1641 (ich_lr_el2.vINTID == int_id)) {
1642 return lr_idx;
1643 }
1644 }
1645
1646 return -1;
1647}
1648
1649uint32_t
1650Gicv3CPUInterface::getHPPIR0() const
1651{
1652 if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1653 return Gicv3::INTID_SPURIOUS;
1654 }
1655
1656 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1657
1658 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1659 // interrupt for the other state pending
1660 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1661 }
1662
1663 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1664 return Gicv3::INTID_SPURIOUS;
1665 }
1666
1667 if (irq_is_secure && !inSecureState()) {
1668 // Secure interrupts not visible in Non-secure
1669 return Gicv3::INTID_SPURIOUS;
1670 }
1671
1672 return hppi.intid;
1673}
1674
1675uint32_t
1676Gicv3CPUInterface::getHPPIR1() const
1677{
1678 if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1679 return Gicv3::INTID_SPURIOUS;
1680 }
1681
1682 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1683 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1684 if (hppi.group == Gicv3::G0S) {
1685 return Gicv3::INTID_SECURE;
1686 } else if (hppi.group == Gicv3::G1NS) {
1687 return Gicv3::INTID_NONSECURE;
1688 }
1689 }
1690
1691 if (hppi.group == Gicv3::G0S) {
1692 return Gicv3::INTID_SPURIOUS;
1693 }
1694
1695 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1696
1697 if (irq_is_secure) {
1698 if (!inSecureState()) {
1699 // Secure interrupts not visible in Non-secure
1700 return Gicv3::INTID_SPURIOUS;
1701 }
1702 } else if (!isEL3OrMon() && inSecureState()) {
1703 // Group 1 non-secure interrupts not visible in Secure EL1
1704 return Gicv3::INTID_SPURIOUS;
1705 }
1706
1707 return hppi.intid;
1708}
1709
1710void
1711Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1712{
1713 int apr_misc_reg = 0;
1714
1715 switch (group) {
1716 case Gicv3::G0S:
1717 apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
1718 break;
1719 case Gicv3::G1S:
1720 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
1721 break;
1722 case Gicv3::G1NS:
1723 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
1724 break;
1725 default:
1726 panic("Invalid Gicv3::GroupId");
1727 }
1728
1729 RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1730
1731 if (apr) {
1732 apr &= apr - 1;
1733 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1734 }
1735
1736 update();
1737}
1738
1739uint8_t
1740Gicv3CPUInterface::virtualDropPriority()
1741{
1742 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1743
1744 for (int i = 0; i < apr_max; i++) {
1745 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1746 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1747
1748 if (!vapr0 && !vapr1) {
1749 continue;
1750 }
1751
1752 int vapr0_count = ctz32(vapr0);
1753 int vapr1_count = ctz32(vapr1);
1754
1755 if (vapr0_count <= vapr1_count) {
1756 vapr0 &= vapr0 - 1;
1757 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1758 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1759 } else {
1760 vapr1 &= vapr1 - 1;
1761 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1762 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1763 }
1764 }
1765
1766 return 0xff;
1767}
1768
1769void
1770Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1771{
1772 uint8_t aff3 = bits(val, 55, 48);
1773 uint8_t aff2 = bits(val, 39, 32);
1774 uint8_t aff1 = bits(val, 23, 16);;
1775 uint16_t target_list = bits(val, 15, 0);
1776 uint32_t int_id = bits(val, 27, 24);
1777 bool irm = bits(val, 40, 40);
1778 uint8_t rs = bits(val, 47, 44);
1779
1780 bool ns = !inSecureState();
1781
1782 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1783 Gicv3Redistributor * redistributor_i =
1784 gic->getRedistributor(i);
1785 uint32_t affinity_i = redistributor_i->getAffinity();
1786
1787 if (irm) {
1788 // Interrupts routed to all PEs in the system,
1789 // excluding "self"
1790 if (affinity_i == redistributor->getAffinity()) {
1791 continue;
1792 }
1793 } else {
1794 // Interrupts routed to the PEs specified by
1795 // Aff3.Aff2.Aff1.<target list>
1796 if ((affinity_i >> 8) !=
1797 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1798 continue;
1799 }
1800
1801 uint8_t aff0_i = bits(affinity_i, 7, 0);
1802
1803 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1804 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1805 continue;
1806 }
1807 }
1808
1809 redistributor_i->sendSGI(int_id, group, ns);
1810 }
1811}
1812
1813void
1814Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1815{
1816 // Update active priority registers.
1817 uint32_t prio = hppi.prio & 0xf8;
1818 int apr_bit = prio >> (8 - PRIORITY_BITS);
1819 int reg_bit = apr_bit % 32;
1820
1821 int apr_idx = 0;
1822 switch (group) {
1823 case Gicv3::G0S:
1824 apr_idx = MISCREG_ICC_AP0R0_EL1;
1825 break;
1826 case Gicv3::G1S:
1827 apr_idx = MISCREG_ICC_AP1R0_EL1_S;
1828 break;
1829 case Gicv3::G1NS:
1830 apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
1831 break;
1832 default:
1833 panic("Invalid Gicv3::GroupId");
1834 }
1835
1836 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1837 apr |= (1 << reg_bit);
1838 isa->setMiscRegNoEffect(apr_idx, apr);
1839
1840 // Move interrupt state from pending to active.
1841 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1842 // SGI or PPI, redistributor
1843 redistributor->activateIRQ(int_id);
1844 } else if (int_id < Gicv3::INTID_SECURE) {
1845 // SPI, distributor
1846 distributor->activateIRQ(int_id);
1847 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
1848 // LPI, Redistributor
1849 redistributor->setClrLPI(int_id, false);
1850 }
1851
1852 // By setting the priority to 0xff we are effectively
1853 // making the int_id not pending anymore at the cpu
1854 // interface.
1855 hppi.prio = 0xff;
1856 updateDistributor();
1857}
1858
1859void
1860Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1861{
1862 // Update active priority registers.
1863 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1864 lr_idx);
1865 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1866 uint8_t prio = ich_lr_el.Priority & 0xf8;
1867 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1868 int reg_no = apr_bit / 32;
1869 int reg_bit = apr_bit % 32;
1870 int apr_idx = group == Gicv3::G0S ?
1871 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1872 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1873 apr |= (1 << reg_bit);
1874 isa->setMiscRegNoEffect(apr_idx, apr);
1875 // Move interrupt state from pending to active.
1876 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1877 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1878}
1879
1880void
1881Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1882{
1883 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1884 // SGI or PPI, redistributor
1885 redistributor->deactivateIRQ(int_id);
1886 } else if (int_id < Gicv3::INTID_SECURE) {
1887 // SPI, distributor
1888 distributor->deactivateIRQ(int_id);
1889 }
1890
1891 updateDistributor();
1892}
1893
1894void
1895Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1896{
1897 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1898 lr_idx);
1899
1900 if (ich_lr_el2.HW) {
1901 // Deactivate the associated physical interrupt
1902 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1903 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1904 distributor->getIntGroup(ich_lr_el2.pINTID) :
1905 redistributor->getIntGroup(ich_lr_el2.pINTID);
1906 deactivateIRQ(ich_lr_el2.pINTID, group);
1907 }
1908 }
1909
1910 // Remove the active bit
1911 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1912 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1913}
1914
1915/*
1916 * Returns the priority group field for the current BPR value for the group.
1917 * GroupBits() Pseudocode from spec.
1918 */
1919uint32_t
1920Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
1921{
1922 ICC_CTLR_EL1 icc_ctlr_el1_s =
1923 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1924 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1925 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1926
1927 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1928 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1929 group = Gicv3::G0S;
1930 }
1931
1932 int bpr;
1933
1934 if (group == Gicv3::G0S) {
1935 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
1936 } else if (group == Gicv3::G1S) {
1937 bpr = bpr1(Gicv3::G1S) & 0x7;
1938 } else {
1939 bpr = bpr1(Gicv3::G1NS) & 0x7;
1940 }
1941
1942 if (group == Gicv3::G1NS) {
1943 assert(bpr > 0);
1944 bpr--;
1945 }
1946
1947 return ~0U << (bpr + 1);
1948}
1949
1950uint32_t
1951Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1952{
1953 ICH_VMCR_EL2 ich_vmcr_el2 =
1954 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1955
1956 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1957 group = Gicv3::G0S;
1958 }
1959
1960 int bpr;
1961
1962 if (group == Gicv3::G0S) {
1963 bpr = ich_vmcr_el2.VBPR0;
1964 } else {
1965 bpr = ich_vmcr_el2.VBPR1;
1966 }
1967
1968 if (group == Gicv3::G1NS) {
1969 assert(bpr > 0);
1970 bpr--;
1971 }
1972
1973 return ~0U << (bpr + 1);
1974}
1975
1976bool
1977Gicv3CPUInterface::isEOISplitMode() const
1978{
1979 if (isEL3OrMon()) {
1980 ICC_CTLR_EL3 icc_ctlr_el3 =
1981 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1982 return icc_ctlr_el3.EOImode_EL3;
1983 } else {
1984 ICC_CTLR_EL1 icc_ctlr_el1 = 0;
1985 if (inSecureState())
1986 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1987 else
1988 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1989 return icc_ctlr_el1.EOImode;
1990 }
1991}
1992
1993bool
1994Gicv3CPUInterface::virtualIsEOISplitMode() const
1995{
1996 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1997 return ich_vmcr_el2.VEOIM;
1998}
1999
2000int
2001Gicv3CPUInterface::highestActiveGroup() const
2002{
2003 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
2004 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
2005 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
2006
2007 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
2008 return Gicv3::G1NS;
2009 }
2010
2011 if (gq_ctz < g0_ctz) {
2012 return Gicv3::G1S;
2013 }
2014
2015 if (g0_ctz < 32) {
2016 return Gicv3::G0S;
2017 }
2018
2019 return -1;
2020}
2021
2022void
2023Gicv3CPUInterface::updateDistributor()
2024{
2025 distributor->update();
2026}
2027
2028void
2029Gicv3CPUInterface::update()
2030{
2031 bool signal_IRQ = false;
2032 bool signal_FIQ = false;
2033
2034 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2035 /*
2036 * Secure enabled GIC sending a G1S IRQ to a secure disabled
2037 * CPU -> send G0 IRQ
2038 */
2039 hppi.group = Gicv3::G0S;
2040 }
2041
2042 if (hppiCanPreempt()) {
2043 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
2044 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
2045 "posting int as %d!\n", int_type);
2046 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
2047 }
2048
2049 if (signal_IRQ) {
2050 gic->postInt(cpuId, ArmISA::INT_IRQ);
2051 } else {
2052 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
2053 }
2054
2055 if (signal_FIQ) {
2056 gic->postInt(cpuId, ArmISA::INT_FIQ);
2057 } else {
2058 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
2059 }
2060}
2061
2062void
2063Gicv3CPUInterface::virtualUpdate()
2064{
2065 bool signal_IRQ = false;
2066 bool signal_FIQ = false;
2067 int lr_idx = getHPPVILR();
2068
2069 if (lr_idx >= 0) {
2070 ICH_LR_EL2 ich_lr_el2 =
2071 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2072
2073 if (hppviCanPreempt(lr_idx)) {
2074 if (ich_lr_el2.Group) {
2075 signal_IRQ = true;
2076 } else {
2077 signal_FIQ = true;
2078 }
2079 }
2080 }
2081
2082 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2083
2084 if (ich_hcr_el2.En) {
2085 if (maintenanceInterruptStatus()) {
2086 maintenanceInterrupt->raise();
2087 }
2088 }
2089
2090 if (signal_IRQ) {
2091 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2092 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2093 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2094 } else {
2095 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2096 }
2097
2098 if (signal_FIQ) {
2099 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2100 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2101 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2102 } else {
2103 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2104 }
2105}
2106
2107// Returns the index of the LR with the HPPI
2108int
2109Gicv3CPUInterface::getHPPVILR() const
2110{
2111 int idx = -1;
2112 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2113
2114 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2115 // VG0 and VG1 disabled...
2116 return idx;
2117 }
2118
2119 uint8_t highest_prio = 0xff;
2120
2121 for (int i = 0; i < 16; i++) {
2122 ICH_LR_EL2 ich_lr_el2 =
2123 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2124
2125 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2126 continue;
2127 }
2128
2129 if (ich_lr_el2.Group) {
2130 // VG1
2131 if (!ich_vmcr_el2.VENG1) {
2132 continue;
2133 }
2134 } else {
2135 // VG0
2136 if (!ich_vmcr_el2.VENG0) {
2137 continue;
2138 }
2139 }
2140
2141 uint8_t prio = ich_lr_el2.Priority;
2142
2143 if (prio < highest_prio) {
2144 highest_prio = prio;
2145 idx = i;
2146 }
2147 }
2148
2149 return idx;
2150}
2151
2152bool
2153Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2154{
2155 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2156 if (!ich_hcr_el2.En) {
2157 // virtual interface is disabled
2158 return false;
2159 }
2160
2161 ICH_LR_EL2 ich_lr_el2 =
2162 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2163 uint8_t prio = ich_lr_el2.Priority;
2164 uint8_t vpmr =
2165 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2166
2167 if (prio >= vpmr) {
2168 // prioriry masked
2169 return false;
2170 }
2171
2172 uint8_t rprio = virtualHighestActivePriority();
2173
2174 if (rprio == 0xff) {
2175 return true;
2176 }
2177
2178 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2179 uint32_t prio_mask = virtualGroupPriorityMask(group);
2180
2181 if ((prio & prio_mask) < (rprio & prio_mask)) {
2182 return true;
2183 }
2184
2185 return false;
2186}
2187
2188uint8_t
2189Gicv3CPUInterface::virtualHighestActivePriority() const
2190{
2191 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2192
2193 for (int i = 0; i < num_aprs; i++) {
2194 RegVal vapr =
2195 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2196 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2197
2198 if (!vapr) {
2199 continue;
2200 }
2201
2202 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2203 }
2204
2205 // no active interrups, return idle priority
2206 return 0xff;
2207}
2208
2209void
2210Gicv3CPUInterface::virtualIncrementEOICount()
2211{
2212 // Increment the EOICOUNT field in ICH_HCR_EL2
2213 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2214 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2215 EOI_cout++;
2216 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2217 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2218}
2219
2220// spec section 4.6.2
2221ArmISA::InterruptTypes
2222Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2223{
2224 bool is_fiq = false;
2225
2226 switch (group) {
2227 case Gicv3::G0S:
2228 is_fiq = true;
2229 break;
2230
2231 case Gicv3::G1S:
2232 is_fiq = (distributor->DS == 0) &&
2233 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2234 break;
2235
2236 case Gicv3::G1NS:
2237 is_fiq = (distributor->DS == 0) && inSecureState();
2238 break;
2239
2240 default:
2241 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2242 }
2243
2244 if (is_fiq) {
2245 return ArmISA::INT_FIQ;
2246 } else {
2247 return ArmISA::INT_IRQ;
2248 }
2249}
2250
2251bool
2252Gicv3CPUInterface::hppiCanPreempt()
2253{
2254 if (hppi.prio == 0xff) {
2255 // there is no pending interrupt
2256 return false;
2257 }
2258
2259 if (!groupEnabled(hppi.group)) {
2260 // group disabled at CPU interface
2261 return false;
2262 }
2263
2264 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2265 // priority masked
2266 return false;
2267 }
2268
2269 uint8_t rprio = highestActivePriority();
2270
2271 if (rprio == 0xff) {
2272 return true;
2273 }
2274
2275 uint32_t prio_mask = groupPriorityMask(hppi.group);
2276
2277 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2278 return true;
2279 }
2280
2281 return false;
2282}
2283
2284uint8_t
2285Gicv3CPUInterface::highestActivePriority() const
2286{
2287 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2288 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2289 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2290
2291 if (apr) {
2292 return ctz32(apr) << (GIC_MIN_BPR + 1);
2293 }
2294
2295 // no active interrups, return idle priority
2296 return 0xff;
2297}
2298
2299bool
2300Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2301{
2302 switch (group) {
2303 case Gicv3::G0S: {
2304 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2305 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2306 return icc_igrpen0_el1.Enable && distributor->EnableGrp0;
2307 }
2308
2309 case Gicv3::G1S: {
2310 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2311 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2312 return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S;
2313 }
2314
2315 case Gicv3::G1NS: {
2316 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2317 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2318 return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS;
2319 }
2320
2321 default:
2322 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2323 }
2324}
2325
2326bool
2327Gicv3CPUInterface::inSecureState() const
2328{
2329 if (!gic->getSystem()->haveSecurity()) {
2330 return false;
2331 }
2332
2333 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2334 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2335 return ArmISA::inSecureState(scr, cpsr);
2336}
2337
2338int
2339Gicv3CPUInterface::currEL() const
2340{
2341 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2342 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2343
2344 if (is_64) {
2345 return (ExceptionLevel)(uint8_t) cpsr.el;
2346 } else {
2347 switch (cpsr.mode) {
2348 case MODE_USER:
2349 return 0;
2350
2351 case MODE_HYP:
2352 return 2;
2353
2354 case MODE_MON:
2355 return 3;
2356
2357 default:
2358 return 1;
2359 }
2360 }
2361}
2362
2363bool
2364Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2365{
2366 switch (el) {
2367 case EL0:
2368 case EL1:
2369 return true;
2370
2371 case EL2:
2372 return gic->getSystem()->haveVirtualization();
2373
2374 case EL3:
2375 return gic->getSystem()->haveSecurity();
2376
2377 default:
2378 warn("Unimplemented Exception Level\n");
2379 return false;
2380 }
2381}
2382
2383bool
2384Gicv3CPUInterface::isSecureBelowEL3() const
2385{
2386 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2387 return haveEL(EL3) && scr.ns == 0;
2388}
2389
2390bool
2391Gicv3CPUInterface::isAA64() const
2392{
2393 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2394 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2395}
2396
2397bool
2398Gicv3CPUInterface::isEL3OrMon() const
2399{
2400 if (haveEL(EL3)) {
2401 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2402 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2403
2404 if (is_64 && (cpsr.el == EL3)) {
2405 return true;
2406 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2407 return true;
2408 }
2409 }
2410
2411 return false;
2412}
2413
2414// Computes ICH_EISR_EL2
2415uint64_t
2416Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2417{
2418 // ICH_EISR_EL2
2419 // Bits [63:16] - RES0
2420 // Status<n>, bit [n], for n = 0 to 15
2421 // EOI maintenance interrupt status bit for List register <n>:
2422 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2423 // maintenance interrupt.
2424 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2425 // interrupt that has not been handled.
2426 //
2427 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2428 // of the following are true:
2429 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2430 // - ICH_LR<n>_EL2.HW is 0.
2431 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2432
2433 uint64_t value = 0;
2434
2435 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2436 ICH_LR_EL2 ich_lr_el2 =
2437 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2438
2439 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2440 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2441 value |= (1 << lr_idx);
2442 }
2443 }
2444
2445 return value;
2446}
2447
2448Gicv3CPUInterface::ICH_MISR_EL2
2449Gicv3CPUInterface::maintenanceInterruptStatus() const
2450{
2451 // Comments are copied from SPEC section 9.4.7 (ID012119)
2452 ICH_MISR_EL2 ich_misr_el2 = 0;
2453 ICH_HCR_EL2 ich_hcr_el2 =
2454 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2455 ICH_VMCR_EL2 ich_vmcr_el2 =
2456 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2457
2458 // End Of Interrupt. [bit 0]
2459 // This maintenance interrupt is asserted when at least one bit in
2460 // ICH_EISR_EL2 is 1.
2461
2462 if (eoiMaintenanceInterruptStatus()) {
2463 ich_misr_el2.EOI = 1;
2464 }
2465
2466 // Underflow. [bit 1]
2467 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2468 // zero or one of the List register entries are marked as a valid
2469 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2470 // do not equal 0x0.
2471 uint32_t num_valid_interrupts = 0;
2472 uint32_t num_pending_interrupts = 0;
2473
2474 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2475 ICH_LR_EL2 ich_lr_el2 =
2476 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2477
2478 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2479 num_valid_interrupts++;
2480 }
2481
2482 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2483 num_pending_interrupts++;
2484 }
2485 }
2486
2487 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2488 ich_misr_el2.U = 1;
2489 }
2490
2491 // List Register Entry Not Present. [bit 2]
2492 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2493 // and ICH_HCR_EL2.EOIcount is non-zero.
2494 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2495 ich_misr_el2.LRENP = 1;
2496 }
2497
2498 // No Pending. [bit 3]
2499 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2500 // no List register is in pending state.
2501 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2502 ich_misr_el2.NP = 1;
2503 }
2504
2505 // vPE Group 0 Enabled. [bit 4]
2506 // This maintenance interrupt is asserted when
2507 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2508 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2509 ich_misr_el2.VGrp0E = 1;
2510 }
2511
2512 // vPE Group 0 Disabled. [bit 5]
2513 // This maintenance interrupt is asserted when
2514 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2515 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2516 ich_misr_el2.VGrp0D = 1;
2517 }
2518
2519 // vPE Group 1 Enabled. [bit 6]
2520 // This maintenance interrupt is asserted when
2521 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2522 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2523 ich_misr_el2.VGrp1E = 1;
2524 }
2525
2526 // vPE Group 1 Disabled. [bit 7]
2527 // This maintenance interrupt is asserted when
2528 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2529 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2530 ich_misr_el2.VGrp1D = 1;
2531 }
2532
2533 return ich_misr_el2;
2534}
2535
2536RegVal
2537Gicv3CPUInterface::bpr1(Gicv3::GroupId group)
2538{
2539 bool hcr_imo = getHCREL2IMO();
2540 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
2541 return readMiscReg(MISCREG_ICV_BPR1_EL1);
2542 }
2543
2544 RegVal bpr = 0;
2545
2546 if (group == Gicv3::G1S) {
2547 ICC_CTLR_EL1 icc_ctlr_el1_s =
2548 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
2549
2550 if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
2551 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
2552 } else {
2553 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S);
2554 bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR;
2555 }
2556 } else if (group == Gicv3::G1NS) {
2557 ICC_CTLR_EL1 icc_ctlr_el1_ns =
2558 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
2559
2560 // Check if EL3 is implemented and this is a non secure accesses at
2561 // EL1 and EL2
2562 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
2563 // Reads return BPR0 + 1 saturated to 7, WI
2564 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1;
2565 bpr = bpr < 7 ? bpr : 7;
2566 } else {
2567 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS);
2568 bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS;
2569 }
2570 } else {
2571 panic("Should be used with G1S and G1NS only\n");
2572 }
2573
2574 return bpr;
2575}
2576
2577void
2578Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2579{
2580 SERIALIZE_SCALAR(hppi.intid);
2581 SERIALIZE_SCALAR(hppi.prio);
2582 SERIALIZE_ENUM(hppi.group);
2583}
2584
2585void
2586Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2587{
2588 UNSERIALIZE_SCALAR(hppi.intid);
2589 UNSERIALIZE_SCALAR(hppi.prio);
2590 UNSERIALIZE_ENUM(hppi.group);
2591}
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