1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#include "dev/arm/gic_v3_cpu_interface.hh"
44
45#include "arch/arm/isa.hh"
46#include "debug/GIC.hh"
47#include "dev/arm/gic_v3.hh"
48#include "dev/arm/gic_v3_distributor.hh"
49#include "dev/arm/gic_v3_redistributor.hh"
50
51const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
52const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
53
54Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
55 : BaseISADevice(),
56 gic(gic),
57 redistributor(nullptr),
58 distributor(nullptr),
59 cpuId(cpu_id)
60{
61}
62
63void
64Gicv3CPUInterface::init()
65{
66 redistributor = gic->getRedistributor(cpuId);
67 distributor = gic->getDistributor();
68}
69
70void
71Gicv3CPUInterface::initState()
72{
73 reset();
74}
75
76void
77Gicv3CPUInterface::reset()
78{
79 hppi.prio = 0xff;
80}
81
82void
83Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
84{
85 maintenanceInterrupt = gic->params()->maint_int->get(tc);
86}
87
88bool
89Gicv3CPUInterface::getHCREL2FMO() const
90{
91 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
92
93 if (hcr.tge && hcr.e2h) {
94 return false;
95 } else if (hcr.tge) {
96 return true;
97 } else {
98 return hcr.fmo;
99 }
100}
101
102bool
103Gicv3CPUInterface::getHCREL2IMO() const
104{
105 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
106
107 if (hcr.tge && hcr.e2h) {
108 return false;
109 } else if (hcr.tge) {
110 return true;
111 } else {
112 return hcr.imo;
113 }
114}
115
116RegVal
117Gicv3CPUInterface::readMiscReg(int misc_reg)
118{
119 RegVal value = isa->readMiscRegNoEffect(misc_reg);
120 bool hcr_fmo = getHCREL2FMO();
121 bool hcr_imo = getHCREL2IMO();
122
123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
131 break;
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:
140
141 // only implemented if supporting 7 or more bits of priority
142 case MISCREG_ICC_AP1R3:
143 case MISCREG_ICC_AP1R3_EL1:
144 // only implemented if supporting 7 or more bits of priority
145 return 0;
146
147 // Active Priorities Group 0 Registers
148 case MISCREG_ICC_AP0R0:
149 case MISCREG_ICC_AP0R0_EL1: {
150 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
151 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
152 }
153
154 break;
155 }
156
157 case MISCREG_ICC_AP0R1:
158 case MISCREG_ICC_AP0R1_EL1:
159
160 // only implemented if supporting 6 or more bits of priority
161 case MISCREG_ICC_AP0R2:
162 case MISCREG_ICC_AP0R2_EL1:
163
164 // only implemented if supporting 7 or more bits of priority
165 case MISCREG_ICC_AP0R3:
166 case MISCREG_ICC_AP0R3_EL1:
167 // only implemented if supporting 7 or more bits of priority
168 return 0;
169
170 // Interrupt Group 0 Enable register EL1
171 case MISCREG_ICC_IGRPEN0:
172 case MISCREG_ICC_IGRPEN0_EL1: {
173 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
174 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
175 }
176
177 break;
178 }
179
180 case MISCREG_ICV_IGRPEN0_EL1: {
181 ICH_VMCR_EL2 ich_vmcr_el2 =
182 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
183 value = ich_vmcr_el2.VENG0;
184 break;
185 }
186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
194 break;
195 }
196
197 case MISCREG_ICV_IGRPEN1_EL1: {
198 ICH_VMCR_EL2 ich_vmcr_el2 =
199 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
200 value = ich_vmcr_el2.VENG1;
201 break;
202 }
203
204 // Interrupt Group 1 Enable register EL3
205 case MISCREG_ICC_MGRPEN1:
206 case MISCREG_ICC_IGRPEN1_EL3:
207 break;
208
209 // Running Priority Register
210 case MISCREG_ICC_RPR:
211 case MISCREG_ICC_RPR_EL1: {
212 if ((currEL() == EL1) && !inSecureState() &&
213 (hcr_imo || hcr_fmo)) {
214 return readMiscReg(MISCREG_ICV_RPR_EL1);
215 }
216
217 uint8_t rprio = highestActivePriority();
218
219 if (haveEL(EL3) && !inSecureState() &&
220 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
221 // Spec section 4.8.1
222 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
223 if ((rprio & 0x80) == 0) {
224 // If the current priority mask value is in the range of
225 // 0x00-0x7F a read access returns the value 0x0
226 rprio = 0;
227 } else if (rprio != 0xff) {
228 // If the current priority mask value is in the range of
229 // 0x80-0xFF a read access returns the Non-secure read of
230 // the current value
231 rprio = (rprio << 1) & 0xff;
232 }
233 }
234
235 value = rprio;
236 break;
237 }
238
239 // Virtual Running Priority Register
240 case MISCREG_ICV_RPR_EL1: {
241 value = virtualHighestActivePriority();
242 break;
243 }
244
245 // Highest Priority Pending Interrupt Register 0
246 case MISCREG_ICC_HPPIR0:
247 case MISCREG_ICC_HPPIR0_EL1: {
248 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
249 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
250 }
251
252 value = getHPPIR0();
253 break;
254 }
255
256 // Virtual Highest Priority Pending Interrupt Register 0
257 case MISCREG_ICV_HPPIR0_EL1: {
258 value = Gicv3::INTID_SPURIOUS;
259 int lr_idx = getHPPVILR();
260
261 if (lr_idx >= 0) {
262 ICH_LR_EL2 ich_lr_el2 =
263 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
264 Gicv3::GroupId group =
265 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
266
267 if (group == Gicv3::G0S) {
268 value = ich_lr_el2.vINTID;
269 }
270 }
271
272 break;
273 }
274
275 // Highest Priority Pending Interrupt Register 1
276 case MISCREG_ICC_HPPIR1:
277 case MISCREG_ICC_HPPIR1_EL1: {
278 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
279 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
280 }
281
282 value = getHPPIR1();
283 break;
284 }
285
286 // Virtual Highest Priority Pending Interrupt Register 1
287 case MISCREG_ICV_HPPIR1_EL1: {
288 value = Gicv3::INTID_SPURIOUS;
289 int lr_idx = getHPPVILR();
290
291 if (lr_idx >= 0) {
292 ICH_LR_EL2 ich_lr_el2 =
293 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
294 Gicv3::GroupId group =
295 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
296
297 if (group == Gicv3::G1NS) {
298 value = ich_lr_el2.vINTID;
299 }
300 }
301
302 break;
303 }
304
305 // Binary Point Register 0
306 case MISCREG_ICC_BPR0:
307 case MISCREG_ICC_BPR0_EL1:
308 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
309 return readMiscReg(MISCREG_ICV_BPR0_EL1);
310 }
311
312 M5_FALLTHROUGH;
313
314 // Binary Point Register 1
315 case MISCREG_ICC_BPR1:
316 case MISCREG_ICC_BPR1_EL1: {
317 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
318 return readMiscReg(MISCREG_ICV_BPR1_EL1);
319 }
320
321 Gicv3::GroupId group =
322 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
323
324 if (group == Gicv3::G1S && !inSecureState()) {
325 group = Gicv3::G1NS;
326 }
327
328 ICC_CTLR_EL1 icc_ctlr_el1_s =
329 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
330
331 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
332 icc_ctlr_el1_s.CBPR) {
333 group = Gicv3::G0S;
334 }
335
336 bool sat_inc = false;
337
338 ICC_CTLR_EL1 icc_ctlr_el1_ns =
339 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
340
341 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
342 icc_ctlr_el1_ns.CBPR) {
343 // Reads return BPR0 + 1 saturated to 7, WI
344 group = Gicv3::G0S;
345 sat_inc = true;
346 }
347
348 uint8_t bpr;
349
350 if (group == Gicv3::G0S) {
351 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
352 } else {
353 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
354 bpr = std::max(bpr, group == Gicv3::G1S ?
355 GIC_MIN_BPR : GIC_MIN_BPR_NS);
356 }
357
358 if (sat_inc) {
359 bpr++;
360
361 if (bpr > 7) {
362 bpr = 7;
363 }
364 }
365
366 value = bpr;
367 break;
368 }
369
370 // Virtual Binary Point Register 1
371 case MISCREG_ICV_BPR0_EL1:
372 case MISCREG_ICV_BPR1_EL1: {
373 Gicv3::GroupId group =
374 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
375 ICH_VMCR_EL2 ich_vmcr_el2 =
376 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
377 bool sat_inc = false;
378
379 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
380 // bpr0 + 1 saturated to 7, WI
381 group = Gicv3::G0S;
382 sat_inc = true;
383 }
384
385 uint8_t vbpr;
386
387 if (group == Gicv3::G0S) {
388 vbpr = ich_vmcr_el2.VBPR0;
389 } else {
390 vbpr = ich_vmcr_el2.VBPR1;
391 }
392
393 if (sat_inc) {
394 vbpr++;
395
396 if (vbpr > 7) {
397 vbpr = 7;
398 }
399 }
400
401 value = vbpr;
402 break;
403 }
404
405 // Interrupt Priority Mask Register
406 case MISCREG_ICC_PMR:
407 case MISCREG_ICC_PMR_EL1:
408 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
409 return readMiscReg(MISCREG_ICV_PMR_EL1);
410 }
411
412 if (haveEL(EL3) && !inSecureState() &&
413 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
414 // Spec section 4.8.1
415 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
416 if ((value & 0x80) == 0) {
417 // If the current priority mask value is in the range of
418 // 0x00-0x7F a read access returns the value 0x00.
419 value = 0;
420 } else if (value != 0xff) {
421 // If the current priority mask value is in the range of
422 // 0x80-0xFF a read access returns the Non-secure read of the
423 // current value.
424 value = (value << 1) & 0xff;
425 }
426 }
427
428 break;
429
430 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
431 ICH_VMCR_EL2 ich_vmcr_el2 =
432 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
433
434 value = ich_vmcr_el2.VPMR;
435 break;
436 }
437
438 // Interrupt Acknowledge Register 0
439 case MISCREG_ICC_IAR0:
440 case MISCREG_ICC_IAR0_EL1: {
441 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
442 return readMiscReg(MISCREG_ICV_IAR0_EL1);
443 }
444
445 uint32_t int_id;
446
447 if (hppiCanPreempt()) {
448 int_id = getHPPIR0();
449
450 // avoid activation for special interrupts
451 if (int_id < Gicv3::INTID_SECURE ||
452 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
453 activateIRQ(int_id, hppi.group);
454 }
455 } else {
456 int_id = Gicv3::INTID_SPURIOUS;
457 }
458
459 value = int_id;
460 break;
461 }
462
463 // Virtual Interrupt Acknowledge Register 0
464 case MISCREG_ICV_IAR0_EL1: {
465 int lr_idx = getHPPVILR();
466 uint32_t int_id = Gicv3::INTID_SPURIOUS;
467
468 if (lr_idx >= 0) {
469 ICH_LR_EL2 ich_lr_el2 =
470 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
471
472 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
473 int_id = ich_lr_el2.vINTID;
474
475 if (int_id < Gicv3::INTID_SECURE ||
476 int_id > Gicv3::INTID_SPURIOUS) {
477 virtualActivateIRQ(lr_idx);
478 } else {
479 // Bogus... Pseudocode says:
480 // - Move from pending to invalid...
481 // - Return de bogus id...
482 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
483 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
484 ich_lr_el2);
485 }
486 }
487 }
488
489 value = int_id;
490 virtualUpdate();
491 break;
492 }
493
494 // Interrupt Acknowledge Register 1
495 case MISCREG_ICC_IAR1:
496 case MISCREG_ICC_IAR1_EL1: {
497 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
498 return readMiscReg(MISCREG_ICV_IAR1_EL1);
499 }
500
501 uint32_t int_id;
502
503 if (hppiCanPreempt()) {
504 int_id = getHPPIR1();
505
506 // avoid activation for special interrupts
507 if (int_id < Gicv3::INTID_SECURE ||
508 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
509 activateIRQ(int_id, hppi.group);
510 }
511 } else {
512 int_id = Gicv3::INTID_SPURIOUS;
513 }
514
515 value = int_id;
516 break;
517 }
518
519 // Virtual Interrupt Acknowledge Register 1
520 case MISCREG_ICV_IAR1_EL1: {
521 int lr_idx = getHPPVILR();
522 uint32_t int_id = Gicv3::INTID_SPURIOUS;
523
524 if (lr_idx >= 0) {
525 ICH_LR_EL2 ich_lr_el2 =
526 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
527
528 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
529 int_id = ich_lr_el2.vINTID;
530
531 if (int_id < Gicv3::INTID_SECURE ||
532 int_id > Gicv3::INTID_SPURIOUS) {
533 virtualActivateIRQ(lr_idx);
534 } else {
535 // Bogus... Pseudocode says:
536 // - Move from pending to invalid...
537 // - Return de bogus id...
538 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
539 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
540 ich_lr_el2);
541 }
542 }
543 }
544
545 value = int_id;
546 virtualUpdate();
547 break;
548 }
549
550 // System Register Enable Register EL1
551 case MISCREG_ICC_SRE:
552 case MISCREG_ICC_SRE_EL1: {
553 /*
554 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
555 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
556 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
557 */
558 ICC_SRE_EL1 icc_sre_el1 = 0;
559 icc_sre_el1.SRE = 1;
560 icc_sre_el1.DIB = 1;
561 icc_sre_el1.DFB = 1;
562 value = icc_sre_el1;
563 break;
564 }
565
566 // System Register Enable Register EL2
567 case MISCREG_ICC_HSRE:
568 case MISCREG_ICC_SRE_EL2: {
569 /*
570 * Enable [3] == 1
571 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
572 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
573 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
574 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
575 */
576 ICC_SRE_EL2 icc_sre_el2 = 0;
577 icc_sre_el2.SRE = 1;
578 icc_sre_el2.DIB = 1;
579 icc_sre_el2.DFB = 1;
580 icc_sre_el2.Enable = 1;
581 value = icc_sre_el2;
582 break;
583 }
584
585 // System Register Enable Register EL3
586 case MISCREG_ICC_MSRE:
587 case MISCREG_ICC_SRE_EL3: {
588 /*
589 * Enable [3] == 1
590 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
591 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
592 * RAO/WI)
593 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
594 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
595 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
596 */
597 ICC_SRE_EL3 icc_sre_el3 = 0;
598 icc_sre_el3.SRE = 1;
599 icc_sre_el3.DIB = 1;
600 icc_sre_el3.DFB = 1;
601 icc_sre_el3.Enable = 1;
602 value = icc_sre_el3;
603 break;
604 }
605
606 // Control Register
607 case MISCREG_ICC_CTLR:
608 case MISCREG_ICC_CTLR_EL1: {
609 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
610 return readMiscReg(MISCREG_ICV_CTLR_EL1);
611 }
612
613 // Enforce value for RO bits
614 // ExtRange [19], INTIDs in the range 1024..8191 not supported
615 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
616 // A3V [15], supports non-zero values of the Aff3 field in SGI
617 // generation System registers
618 // SEIS [14], does not support generation of SEIs (deprecated)
619 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
620 // PRIbits [10:8], number of priority bits implemented, minus one
621 ICC_CTLR_EL1 icc_ctlr_el1 = value;
622 icc_ctlr_el1.ExtRange = 0;
623 icc_ctlr_el1.RSS = 1;
624 icc_ctlr_el1.A3V = 1;
625 icc_ctlr_el1.SEIS = 0;
626 icc_ctlr_el1.IDbits = 1;
627 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
628 value = icc_ctlr_el1;
629 break;
630 }
631
632 // Virtual Control Register
633 case MISCREG_ICV_CTLR_EL1: {
634 ICV_CTLR_EL1 icv_ctlr_el1 = value;
635 icv_ctlr_el1.RSS = 0;
636 icv_ctlr_el1.A3V = 1;
637 icv_ctlr_el1.SEIS = 0;
638 icv_ctlr_el1.IDbits = 1;
639 icv_ctlr_el1.PRIbits = 7;
640 value = icv_ctlr_el1;
641 break;
642 }
643
644 // Control Register
645 case MISCREG_ICC_MCTLR:
646 case MISCREG_ICC_CTLR_EL3: {
647 // Enforce value for RO bits
648 // ExtRange [19], INTIDs in the range 1024..8191 not supported
649 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
650 // nDS [17], supports disabling of security
651 // A3V [15], supports non-zero values of the Aff3 field in SGI
652 // generation System registers
653 // SEIS [14], does not support generation of SEIs (deprecated)
654 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
655 // PRIbits [10:8], number of priority bits implemented, minus one
656 ICC_CTLR_EL3 icc_ctlr_el3 = value;
657 icc_ctlr_el3.ExtRange = 0;
658 icc_ctlr_el3.RSS = 1;
659 icc_ctlr_el3.nDS = 0;
660 icc_ctlr_el3.A3V = 1;
661 icc_ctlr_el3.SEIS = 0;
662 icc_ctlr_el3.IDbits = 0;
663 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
664 value = icc_ctlr_el3;
665 break;
666 }
667
668 // Hyp Control Register
669 case MISCREG_ICH_HCR:
670 case MISCREG_ICH_HCR_EL2:
671 break;
672
673 // Hyp Active Priorities Group 0 Registers
674 case MISCREG_ICH_AP0R0:
675 case MISCREG_ICH_AP0R0_EL2:
676 break;
677
678 // Hyp Active Priorities Group 1 Registers
679 case MISCREG_ICH_AP1R0:
680 case MISCREG_ICH_AP1R0_EL2:
681 break;
682
683 // Maintenance Interrupt State Register
684 case MISCREG_ICH_MISR:
685 case MISCREG_ICH_MISR_EL2:
686 value = maintenanceInterruptStatus();
687 break;
688
689 // VGIC Type Register
690 case MISCREG_ICH_VTR:
691 case MISCREG_ICH_VTR_EL2: {
692 ICH_VTR_EL2 ich_vtr_el2 = value;
693
694 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
695 ich_vtr_el2.A3V = 1;
696 ich_vtr_el2.IDbits = 1;
697 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
698 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
699
700 value = ich_vtr_el2;
701 break;
702 }
703
704 // End of Interrupt Status Register
705 case MISCREG_ICH_EISR:
706 case MISCREG_ICH_EISR_EL2:
707 value = eoiMaintenanceInterruptStatus();
708 break;
709
710 // Empty List Register Status Register
711 case MISCREG_ICH_ELRSR:
712 case MISCREG_ICH_ELRSR_EL2:
713 value = 0;
714
715 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
716 ICH_LR_EL2 ich_lr_el2 =
717 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
718
719 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
720 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
721 value |= (1 << lr_idx);
722 }
723 }
724
725 break;
726
727 // List Registers
728 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
729 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
730 value = value >> 32;
731 break;
732
733 // List Registers
734 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
735 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
736 value = value & 0xffffffff;
737 break;
738
739 // List Registers
740 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
741 break;
742
743 // Virtual Machine Control Register
744 case MISCREG_ICH_VMCR:
745 case MISCREG_ICH_VMCR_EL2:
746 break;
747
748 default:
749 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
750 misc_reg, miscRegName[misc_reg]);
751 }
752
753 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
754 miscRegName[misc_reg], value);
755 return value;
756}
757
758void
759Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
760{
761 bool do_virtual_update = false;
762 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
763 miscRegName[misc_reg], val);
764 bool hcr_fmo = getHCREL2FMO();
765 bool hcr_imo = getHCREL2IMO();
766
767 switch (misc_reg) {
768 // Active Priorities Group 1 Registers
769 case MISCREG_ICC_AP1R0:
770 case MISCREG_ICC_AP1R0_EL1:
771 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
772 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
773 }
774
775 break;
776
777 case MISCREG_ICC_AP1R1:
778 case MISCREG_ICC_AP1R1_EL1:
779
780 // only implemented if supporting 6 or more bits of priority
781 case MISCREG_ICC_AP1R2:
782 case MISCREG_ICC_AP1R2_EL1:
783
784 // only implemented if supporting 7 or more bits of priority
785 case MISCREG_ICC_AP1R3:
786 case MISCREG_ICC_AP1R3_EL1:
787 // only implemented if supporting 7 or more bits of priority
788 break;
789
790 // Active Priorities Group 0 Registers
791 case MISCREG_ICC_AP0R0:
792 case MISCREG_ICC_AP0R0_EL1:
793 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
794 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
795 }
796
797 break;
798
799 case MISCREG_ICC_AP0R1:
800 case MISCREG_ICC_AP0R1_EL1:
801
802 // only implemented if supporting 6 or more bits of priority
803 case MISCREG_ICC_AP0R2:
804 case MISCREG_ICC_AP0R2_EL1:
805
806 // only implemented if supporting 7 or more bits of priority
807 case MISCREG_ICC_AP0R3:
808 case MISCREG_ICC_AP0R3_EL1:
809 // only implemented if supporting 7 or more bits of priority
810 break;
811
812 // End Of Interrupt Register 0
813 case MISCREG_ICC_EOIR0:
814 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
815 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
816 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
817 }
818
819 int int_id = val & 0xffffff;
820
821 // avoid activation for special interrupts
822 if (int_id >= Gicv3::INTID_SECURE &&
823 int_id <= Gicv3::INTID_SPURIOUS) {
824 return;
825 }
826
827 Gicv3::GroupId group = Gicv3::G0S;
828
829 if (highestActiveGroup() != group) {
830 return;
831 }
832
833 dropPriority(group);
834
835 if (!isEOISplitMode()) {
836 deactivateIRQ(int_id, group);
837 }
838
839 break;
840 }
841
842 // Virtual End Of Interrupt Register 0
843 case MISCREG_ICV_EOIR0_EL1: {
844 int int_id = val & 0xffffff;
845
846 // avoid deactivation for special interrupts
847 if (int_id >= Gicv3::INTID_SECURE &&
848 int_id <= Gicv3::INTID_SPURIOUS) {
849 return;
850 }
851
852 uint8_t drop_prio = virtualDropPriority();
853
854 if (drop_prio == 0xff) {
855 return;
856 }
857
858 int lr_idx = virtualFindActive(int_id);
859
860 if (lr_idx < 0) {
861 // No LR found matching
862 virtualIncrementEOICount();
863 } else {
864 ICH_LR_EL2 ich_lr_el2 =
865 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
866 Gicv3::GroupId lr_group =
867 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
868 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
869
870 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
871 //if (!virtualIsEOISplitMode())
872 {
873 virtualDeactivateIRQ(lr_idx);
874 }
875 }
876 }
877
878 virtualUpdate();
879 break;
880 }
881
882 // End Of Interrupt Register 1
883 case MISCREG_ICC_EOIR1:
884 case MISCREG_ICC_EOIR1_EL1: {
885 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
886 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
887 }
888
889 int int_id = val & 0xffffff;
890
891 // avoid deactivation for special interrupts
892 if (int_id >= Gicv3::INTID_SECURE &&
893 int_id <= Gicv3::INTID_SPURIOUS) {
894 return;
895 }
896
897 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
898
899 if (highestActiveGroup() == Gicv3::G0S) {
900 return;
901 }
902
903 if (distributor->DS == 0) {
904 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
905 return;
906 } else if (highestActiveGroup() == Gicv3::G1NS &&
907 !(!inSecureState() or (currEL() == EL3))) {
908 return;
909 }
910 }
911
912 dropPriority(group);
913
914 if (!isEOISplitMode()) {
915 deactivateIRQ(int_id, group);
916 }
917
918 break;
919 }
920
921 // Virtual End Of Interrupt Register 1
922 case MISCREG_ICV_EOIR1_EL1: {
923 int int_id = val & 0xffffff;
924
925 // avoid deactivation for special interrupts
926 if (int_id >= Gicv3::INTID_SECURE &&
927 int_id <= Gicv3::INTID_SPURIOUS) {
928 return;
929 }
930
931 uint8_t drop_prio = virtualDropPriority();
932
933 if (drop_prio == 0xff) {
934 return;
935 }
936
937 int lr_idx = virtualFindActive(int_id);
938
939 if (lr_idx < 0) {
940 // No matching LR found
941 virtualIncrementEOICount();
942 } else {
943 ICH_LR_EL2 ich_lr_el2 =
944 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
945 Gicv3::GroupId lr_group =
946 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
947 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
948
949 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
950 if (!virtualIsEOISplitMode()) {
951 virtualDeactivateIRQ(lr_idx);
952 }
953 }
954 }
955
956 virtualUpdate();
957 break;
958 }
959
960 // Deactivate Interrupt Register
961 case MISCREG_ICC_DIR:
962 case MISCREG_ICC_DIR_EL1: {
963 if ((currEL() == EL1) && !inSecureState() &&
964 (hcr_imo || hcr_fmo)) {
965 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
966 }
967
968 int int_id = val & 0xffffff;
969
970 // The following checks are as per spec pseudocode
971 // aarch64/support/ICC_DIR_EL1
972
973 // Check for spurious ID
974 if (int_id >= Gicv3::INTID_SECURE) {
975 return;
976 }
977
978 // EOI mode is not set, so don't deactivate
979 if (!isEOISplitMode()) {
980 return;
981 }
982
983 Gicv3::GroupId group =
984 int_id >= 32 ? distributor->getIntGroup(int_id) :
985 redistributor->getIntGroup(int_id);
986 bool irq_is_grp0 = group == Gicv3::G0S;
987 bool single_sec_state = distributor->DS;
988 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
989 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
990 bool route_fiq_to_el3 = scr_el3.fiq;
991 bool route_irq_to_el3 = scr_el3.irq;
992 bool route_fiq_to_el2 = hcr_fmo;
993 bool route_irq_to_el2 = hcr_imo;
994
995 switch (currEL()) {
996 case EL3:
997 break;
998
999 case EL2:
1000 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
1001 break;
1002 }
1003
1004 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
1005 break;
1006 }
1007
1008 return;
1009
1010 case EL1:
1011 if (!isSecureBelowEL3()) {
1012 if (single_sec_state && irq_is_grp0 &&
1013 !route_fiq_to_el3 && !route_fiq_to_el2) {
1014 break;
1015 }
1016
1017 if (!irq_is_secure && !irq_is_grp0 &&
1018 !route_irq_to_el3 && !route_irq_to_el2) {
1019 break;
1020 }
1021 } else {
1022 if (irq_is_grp0 && !route_fiq_to_el3) {
1023 break;
1024 }
1025
1026 if (!irq_is_grp0 &&
1027 (!irq_is_secure || !single_sec_state) &&
1028 !route_irq_to_el3) {
1029 break;
1030 }
1031 }
1032
1033 return;
1034
1035 default:
1036 break;
1037 }
1038
1039 deactivateIRQ(int_id, group);
1040 break;
1041 }
1042
1043 // Deactivate Virtual Interrupt Register
1044 case MISCREG_ICV_DIR_EL1: {
1045 int int_id = val & 0xffffff;
1046
1047 // avoid deactivation for special interrupts
1048 if (int_id >= Gicv3::INTID_SECURE &&
1049 int_id <= Gicv3::INTID_SPURIOUS) {
1050 return;
1051 }
1052
1053 if (!virtualIsEOISplitMode()) {
1054 return;
1055 }
1056
1057 int lr_idx = virtualFindActive(int_id);
1058
1059 if (lr_idx < 0) {
1060 // No matching LR found
1061 virtualIncrementEOICount();
1062 } else {
1063 virtualDeactivateIRQ(lr_idx);
1064 }
1065
1066 virtualUpdate();
1067 break;
1068 }
1069
1070 // Binary Point Register 0
1071 case MISCREG_ICC_BPR0:
1072 case MISCREG_ICC_BPR0_EL1:
1073 // Binary Point Register 1
1074 case MISCREG_ICC_BPR1:
1075 case MISCREG_ICC_BPR1_EL1: {
1076 if ((currEL() == EL1) && !inSecureState()) {
1077 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1078 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1079 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1080 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1081 }
1082 }
1083
1084 Gicv3::GroupId group =
1085 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1086
1087 if (group == Gicv3::G1S && !inSecureState()) {
1088 group = Gicv3::G1NS;
1089 }
1090
1091 ICC_CTLR_EL1 icc_ctlr_el1_s =
1092 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1093
1094 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1095 icc_ctlr_el1_s.CBPR) {
1096 group = Gicv3::G0S;
1097 }
1098
1099 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1100 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1101
1102 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1103 icc_ctlr_el1_ns.CBPR) {
1104 // BPR0 + 1 saturated to 7, WI
1105 return;
1106 }
1107
1108 uint8_t min_val = (group == Gicv3::G1NS) ?
1109 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1110 val &= 0x7;
1111
1112 if (val < min_val) {
1113 val = min_val;
1114 }
1115
1116 break;
1117 }
1118
1119 // Virtual Binary Point Register 0
1120 case MISCREG_ICV_BPR0_EL1:
1121 // Virtual Binary Point Register 1
1122 case MISCREG_ICV_BPR1_EL1: {
1123 Gicv3::GroupId group =
1124 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1125 ICH_VMCR_EL2 ich_vmcr_el2 =
1126 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1127
1128 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1129 // BPR0 + 1 saturated to 7, WI
1130 return;
1131 }
1132
1133 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1134
1135 if (group != Gicv3::G0S) {
1136 min_VPBR++;
1137 }
1138
1139 if (val < min_VPBR) {
1140 val = min_VPBR;
1141 }
1142
1143 if (group == Gicv3::G0S) {
1144 ich_vmcr_el2.VBPR0 = val;
1145 } else {
1146 ich_vmcr_el2.VBPR1 = val;
1147 }
1148
1149 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1150 do_virtual_update = true;
1151 break;
1152 }
1153
1154 // Control Register EL1
1155 case MISCREG_ICC_CTLR:
1156 case MISCREG_ICC_CTLR_EL1: {
1157 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1158 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1159 }
1160
1161 /*
1162 * ExtRange is RO.
1163 * RSS is RO.
1164 * A3V is RO.
1165 * SEIS is RO.
1166 * IDbits is RO.
1167 * PRIbits is RO.
1168 */
1169 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1170 ICC_CTLR_EL1 icc_ctlr_el1 =
1171 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1172
1173 ICC_CTLR_EL3 icc_ctlr_el3 =
1174 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1175
1176 // The following could be refactored but it is following
1177 // spec description section 9.2.6 point by point.
1178
1179 // PMHE
1180 if (haveEL(EL3)) {
1181 // PMHE is alias of ICC_CTLR_EL3.PMHE
1182
1183 if (distributor->DS == 0) {
1184 // PMHE is RO
1185 } else if (distributor->DS == 1) {
1186 // PMHE is RW
1187 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1188 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1189 }
1190 } else {
1191 // PMHE is RW (by implementation choice)
1192 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1193 }
1194
1195 // EOImode
1196 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1197
1198 if (inSecureState()) {
1199 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1200 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1201 } else {
1202 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1203 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1204 }
1205
1206 // CBPR
1207 if (haveEL(EL3)) {
1208 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1209
1210 if (distributor->DS == 0) {
1211 // CBPR is RO
1212 } else {
1213 // CBPR is RW
1214 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1215
1216 if (inSecureState()) {
1217 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1218 } else {
1219 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1220 }
1221 }
1222 } else {
1223 // CBPR is RW
1224 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1225 }
1226
1227 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1228
1229 val = icc_ctlr_el1;
1230 break;
1231 }
1232
1233 // Virtual Control Register
1234 case MISCREG_ICV_CTLR_EL1: {
1235 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1236 ICV_CTLR_EL1 icv_ctlr_el1 =
1237 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1238 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1239 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1240 val = icv_ctlr_el1;
1241
1242 // Aliases
1243 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1244 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1245 ICH_VMCR_EL2 ich_vmcr_el2 =
1246 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1247 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1248 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1249 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1250 break;
1251 }
1252
1253 // Control Register EL3
1254 case MISCREG_ICC_MCTLR:
1255 case MISCREG_ICC_CTLR_EL3: {
1256 /*
1257 * ExtRange is RO.
1258 * RSS is RO.
1259 * nDS is RO.
1260 * A3V is RO.
1261 * SEIS is RO.
1262 * IDbits is RO.
1263 * PRIbits is RO.
1264 * PMHE is RAO/WI, priority-based routing is always used.
1265 */
1266 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1267
1268 // Aliases
1269 if (haveEL(EL3))
1270 {
1271 ICC_CTLR_EL1 icc_ctlr_el1_s =
1272 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1273 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1274 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1275
1276 // ICC_CTLR_EL1(NS).EOImode is an alias of
1277 // ICC_CTLR_EL3.EOImode_EL1NS
1278 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1279 // ICC_CTLR_EL1(S).EOImode is an alias of
1280 // ICC_CTLR_EL3.EOImode_EL1S
1281 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1282 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1283 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1284 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1285 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1286
1287 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1288 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1289 icc_ctlr_el1_ns);
1290 }
1291
1292 ICC_CTLR_EL3 icc_ctlr_el3 =
1293 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1294
1295 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1296 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1297 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1298 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1299 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1300 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1301
1302 val = icc_ctlr_el3;
1303 break;
1304 }
1305
1306 // Priority Mask Register
1307 case MISCREG_ICC_PMR:
1308 case MISCREG_ICC_PMR_EL1: {
1309 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1310 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1311 }
1312
1313 val &= 0xff;
1314 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1315
1316 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1317 // Spec section 4.8.1
1318 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1319 RegVal old_icc_pmr_el1 =
1320 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1321
1322 if (!(old_icc_pmr_el1 & 0x80)) {
1323 // If the current priority mask value is in the range of
1324 // 0x00-0x7F then WI
1325 return;
1326 }
1327
1328 // If the current priority mask value is in the range of
1329 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1330 // based on the Non-secure read of the priority mask value
1331 // written to the register.
1332
1333 val = (val >> 1) | 0x80;
1334 }
1335
1336 val &= ~0U << (8 - PRIORITY_BITS);
1337 break;
1338 }
1339
1340 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1341 ICH_VMCR_EL2 ich_vmcr_el2 =
1342 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1343 ich_vmcr_el2.VPMR = val & 0xff;
1344
1345 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1346 virtualUpdate();
1347 return;
1348 }
1349
1350 // Interrupt Group 0 Enable Register EL1
1351 case MISCREG_ICC_IGRPEN0:
1352 case MISCREG_ICC_IGRPEN0_EL1: {
1353 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1354 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1355 }
1356
1357 break;
1358 }
1359
1360 // Virtual Interrupt Group 0 Enable register
1361 case MISCREG_ICV_IGRPEN0_EL1: {
1362 bool enable = val & 0x1;
1363 ICH_VMCR_EL2 ich_vmcr_el2 =
1364 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1365 ich_vmcr_el2.VENG0 = enable;
1366 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1367 virtualUpdate();
1368 return;
1369 }
1370
1371 // Interrupt Group 1 Enable register EL1
1372 case MISCREG_ICC_IGRPEN1:
1373 case MISCREG_ICC_IGRPEN1_EL1: {
1374 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1375 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1376 }
1377
1378 if (haveEL(EL3)) {
1379 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1380 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1381 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1382
1383 if (inSecureState()) {
1384 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1385 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1386 } else {
1387 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1388 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1389 }
1390
1391 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1392 icc_igrpen1_el3);
1393 }
1394
1395 break;
1396 }
1397
1398 // Virtual Interrupt Group 1 Enable register
1399 case MISCREG_ICV_IGRPEN1_EL1: {
1400 bool enable = val & 0x1;
1401 ICH_VMCR_EL2 ich_vmcr_el2 =
1402 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1403 ich_vmcr_el2.VENG1 = enable;
1404 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1405 virtualUpdate();
1406 return;
1407 }
1408
1409 // Interrupt Group 1 Enable register
1410 case MISCREG_ICC_MGRPEN1:
1411 case MISCREG_ICC_IGRPEN1_EL3: {
1412 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1413 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1414 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1415
1416 if (inSecureState()) {
1417 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1418 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1419 } else {
1420 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1421 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1422 }
1423
1424 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1425 break;
1426 }
1427
1428 // Software Generated Interrupt Group 0 Register
1429 case MISCREG_ICC_SGI0R:
1430 case MISCREG_ICC_SGI0R_EL1:
1431 generateSGI(val, Gicv3::G0S);
1432 break;
1433
1434 // Software Generated Interrupt Group 1 Register
1435 case MISCREG_ICC_SGI1R:
1436 case MISCREG_ICC_SGI1R_EL1: {
1437 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
1438
1439 generateSGI(val, group);
1440 break;
1441 }
1442
1443 // Alias Software Generated Interrupt Group 1 Register
1444 case MISCREG_ICC_ASGI1R:
1445 case MISCREG_ICC_ASGI1R_EL1: {
1446 Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S;
1447
1448 generateSGI(val, group);
1449 break;
1450 }
1451
1452 // System Register Enable Register EL1
1453 case MISCREG_ICC_SRE:
1454 case MISCREG_ICC_SRE_EL1:
1455 // System Register Enable Register EL2
1456 case MISCREG_ICC_HSRE:
1457 case MISCREG_ICC_SRE_EL2:
1458 // System Register Enable Register EL3
1459 case MISCREG_ICC_MSRE:
1460 case MISCREG_ICC_SRE_EL3:
1461 // All bits are RAO/WI
1462 return;
1463
1464 // Hyp Control Register
1465 case MISCREG_ICH_HCR:
1466 case MISCREG_ICH_HCR_EL2: {
1467 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1468 ICH_HCR_EL2 ich_hcr_el2 =
1469 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1470
1471 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1472 {
1473 // EOIcount - Permitted behaviors are:
1474 // - Increment EOIcount.
1475 // - Leave EOIcount unchanged.
1476 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1477 }
1478
1479 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1480 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1481 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1482 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1483 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1484 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1485 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1486 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1487 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1488 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1489 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1490 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1491 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1492 val = ich_hcr_el2;
1493 do_virtual_update = true;
1494 break;
1495 }
1496
1497 // List Registers
1498 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1499 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1500 ICH_LRC requested_ich_lrc = val;
1501 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1502
1503 ich_lrc.State = requested_ich_lrc.State;
1504 ich_lrc.HW = requested_ich_lrc.HW;
1505 ich_lrc.Group = requested_ich_lrc.Group;
1506
1507 // Priority, bits [23:16]
1508 // At least five bits must be implemented.
1509 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1510 // We implement 5 bits.
1511 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1512 (ich_lrc.Priority & 0x07);
1513
1514 // pINTID, bits [12:0]
1515 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1516 // - Bits[12:10] : RES0.
1517 // - Bit[9] : EOI.
1518 // - Bits[8:0] : RES0.
1519 // When ICH_LR<n>.HW is 1:
1520 // - This field is only required to implement enough bits to hold a
1521 // valid value for the implemented INTID size. Any unused higher
1522 // order bits are RES0.
1523 if (requested_ich_lrc.HW == 0) {
1524 ich_lrc.EOI = requested_ich_lrc.EOI;
1525 } else {
1526 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1527 }
1528
1529 val = ich_lrc;
1530 do_virtual_update = true;
1531 break;
1532 }
1533
1534 // List Registers
1535 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1536 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1537 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1538 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1539 do_virtual_update = true;
1540 break;
1541 }
1542
1543 // List Registers
1544 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1545 ICH_LR_EL2 requested_ich_lr_el2 = val;
1546 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1547
1548 ich_lr_el2.State = requested_ich_lr_el2.State;
1549 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1550 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1551
1552 // Priority, bits [55:48]
1553 // At least five bits must be implemented.
1554 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1555 // We implement 5 bits.
1556 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1557 (ich_lr_el2.Priority & 0x07);
1558
1559 // pINTID, bits [44:32]
1560 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1561 // - Bits[44:42] : RES0.
1562 // - Bit[41] : EOI.
1563 // - Bits[40:32] : RES0.
1564 // When ICH_LR<n>_EL2.HW is 1:
1565 // - This field is only required to implement enough bits to hold a
1566 // valid value for the implemented INTID size. Any unused higher
1567 // order bits are RES0.
1568 if (requested_ich_lr_el2.HW == 0) {
1569 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1570 } else {
1571 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1572 }
1573
1574 // vINTID, bits [31:0]
1575 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1576 // though at least 16 bits must be implemented.
1577 // Unimplemented bits are RES0.
1578 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1579
1580 val = ich_lr_el2;
1581 do_virtual_update = true;
1582 break;
1583 }
1584
1585 // Virtual Machine Control Register
1586 case MISCREG_ICH_VMCR:
1587 case MISCREG_ICH_VMCR_EL2: {
1588 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1589 ICH_VMCR_EL2 ich_vmcr_el2 =
1590 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1591 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1592 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1593
1594 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1595 ich_vmcr_el2.VBPR0 = min_vpr0;
1596 } else {
1597 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1598 }
1599
1600 uint8_t min_vpr1 = min_vpr0 + 1;
1601
1602 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1603 ich_vmcr_el2.VBPR1 = min_vpr1;
1604 } else {
1605 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1606 }
1607
1608 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1609 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1610 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1611 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1612 val = ich_vmcr_el2;
1613 break;
1614 }
1615
1616 // Hyp Active Priorities Group 0 Registers
1617 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1618 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1619 // Hyp Active Priorities Group 1 Registers
1620 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1621 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1622 break;
1623
1624 default:
1625 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1626 misc_reg, miscRegName[misc_reg]);
1627 }
1628
1629 isa->setMiscRegNoEffect(misc_reg, val);
1630
1631 if (do_virtual_update) {
1632 virtualUpdate();
1633 }
1634}
1635
1636int
1637Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1638{
1639 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1640 ICH_LR_EL2 ich_lr_el2 =
1641 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1642
1643 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1644 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1645 (ich_lr_el2.vINTID == int_id)) {
1646 return lr_idx;
1647 }
1648 }
1649
1650 return -1;
1651}
1652
1653uint32_t
1654Gicv3CPUInterface::getHPPIR0() const
1655{
1656 if (hppi.prio == 0xff) {
1657 return Gicv3::INTID_SPURIOUS;
1658 }
1659
1660 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1661
1662 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1663 // interrupt for the other state pending
1664 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1665 }
1666
1667 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1668 return Gicv3::INTID_SPURIOUS;
1669 }
1670
1671 if (irq_is_secure && !inSecureState()) {
1672 // Secure interrupts not visible in Non-secure
1673 return Gicv3::INTID_SPURIOUS;
1674 }
1675
1676 return hppi.intid;
1677}
1678
1679uint32_t
1680Gicv3CPUInterface::getHPPIR1() const
1681{
1682 if (hppi.prio == 0xff) {
1683 return Gicv3::INTID_SPURIOUS;
1684 }
1685
1686 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1687 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1688 if (hppi.group == Gicv3::G0S) {
1689 return Gicv3::INTID_SECURE;
1690 } else if (hppi.group == Gicv3::G1NS) {
1691 return Gicv3::INTID_NONSECURE;
1692 }
1693 }
1694
1695 if (hppi.group == Gicv3::G0S) {
1696 return Gicv3::INTID_SPURIOUS;
1697 }
1698
1699 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1700
1701 if (irq_is_secure) {
1702 if (!inSecureState()) {
1703 // Secure interrupts not visible in Non-secure
1704 return Gicv3::INTID_SPURIOUS;
1705 }
1706 } else if (!isEL3OrMon() && inSecureState()) {
1707 // Group 1 non-secure interrupts not visible in Secure EL1
1708 return Gicv3::INTID_SPURIOUS;
1709 }
1710
1711 return hppi.intid;
1712}
1713
1714void
1715Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1716{
1717 int apr_misc_reg;
1718 RegVal apr;
1719 apr_misc_reg = group == Gicv3::G0S ?
1720 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1721 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1722
1723 if (apr) {
1724 apr &= apr - 1;
1725 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1726 }
1727
1728 update();
1729}
1730
1731uint8_t
1732Gicv3CPUInterface::virtualDropPriority()
1733{
1734 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1735
1736 for (int i = 0; i < apr_max; i++) {
1737 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1738 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1739
1740 if (!vapr0 && !vapr1) {
1741 continue;
1742 }
1743
1744 int vapr0_count = ctz32(vapr0);
1745 int vapr1_count = ctz32(vapr1);
1746
1747 if (vapr0_count <= vapr1_count) {
1748 vapr0 &= vapr0 - 1;
1749 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1750 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1751 } else {
1752 vapr1 &= vapr1 - 1;
1753 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1754 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1755 }
1756 }
1757
1758 return 0xff;
1759}
1760
1761void
1762Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1763{
1764 uint8_t aff3 = bits(val, 55, 48);
1765 uint8_t aff2 = bits(val, 39, 32);
1766 uint8_t aff1 = bits(val, 23, 16);;
1767 uint16_t target_list = bits(val, 15, 0);
1768 uint32_t int_id = bits(val, 27, 24);
1769 bool irm = bits(val, 40, 40);
1770 uint8_t rs = bits(val, 47, 44);
1771
1772 bool ns = !inSecureState();
1773
1774 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1775 Gicv3Redistributor * redistributor_i =
1776 gic->getRedistributor(i);
1777 uint32_t affinity_i = redistributor_i->getAffinity();
1778
1779 if (irm) {
1780 // Interrupts routed to all PEs in the system,
1781 // excluding "self"
1782 if (affinity_i == redistributor->getAffinity()) {
1783 continue;
1784 }
1785 } else {
1786 // Interrupts routed to the PEs specified by
1787 // Aff3.Aff2.Aff1.<target list>
1788 if ((affinity_i >> 8) !=
1789 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1790 continue;
1791 }
1792
1793 uint8_t aff0_i = bits(affinity_i, 7, 0);
1794
1795 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1796 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1797 continue;
1798 }
1799 }
1800
1801 redistributor_i->sendSGI(int_id, group, ns);
1802 }
1803}
1804
1805void
1806Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1807{
1808 // Update active priority registers.
1809 uint32_t prio = hppi.prio & 0xf8;
1810 int apr_bit = prio >> (8 - PRIORITY_BITS);
1811 int reg_bit = apr_bit % 32;
1812 int apr_idx = group == Gicv3::G0S ?
1813 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1814 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1815 apr |= (1 << reg_bit);
1816 isa->setMiscRegNoEffect(apr_idx, apr);
1817
1818 // Move interrupt state from pending to active.
1819 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1820 // SGI or PPI, redistributor
1821 redistributor->activateIRQ(int_id);
| 1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#include "dev/arm/gic_v3_cpu_interface.hh"
44
45#include "arch/arm/isa.hh"
46#include "debug/GIC.hh"
47#include "dev/arm/gic_v3.hh"
48#include "dev/arm/gic_v3_distributor.hh"
49#include "dev/arm/gic_v3_redistributor.hh"
50
51const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
52const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
53
54Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
55 : BaseISADevice(),
56 gic(gic),
57 redistributor(nullptr),
58 distributor(nullptr),
59 cpuId(cpu_id)
60{
61}
62
63void
64Gicv3CPUInterface::init()
65{
66 redistributor = gic->getRedistributor(cpuId);
67 distributor = gic->getDistributor();
68}
69
70void
71Gicv3CPUInterface::initState()
72{
73 reset();
74}
75
76void
77Gicv3CPUInterface::reset()
78{
79 hppi.prio = 0xff;
80}
81
82void
83Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
84{
85 maintenanceInterrupt = gic->params()->maint_int->get(tc);
86}
87
88bool
89Gicv3CPUInterface::getHCREL2FMO() const
90{
91 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
92
93 if (hcr.tge && hcr.e2h) {
94 return false;
95 } else if (hcr.tge) {
96 return true;
97 } else {
98 return hcr.fmo;
99 }
100}
101
102bool
103Gicv3CPUInterface::getHCREL2IMO() const
104{
105 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
106
107 if (hcr.tge && hcr.e2h) {
108 return false;
109 } else if (hcr.tge) {
110 return true;
111 } else {
112 return hcr.imo;
113 }
114}
115
116RegVal
117Gicv3CPUInterface::readMiscReg(int misc_reg)
118{
119 RegVal value = isa->readMiscRegNoEffect(misc_reg);
120 bool hcr_fmo = getHCREL2FMO();
121 bool hcr_imo = getHCREL2IMO();
122
123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
131 break;
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:
140
141 // only implemented if supporting 7 or more bits of priority
142 case MISCREG_ICC_AP1R3:
143 case MISCREG_ICC_AP1R3_EL1:
144 // only implemented if supporting 7 or more bits of priority
145 return 0;
146
147 // Active Priorities Group 0 Registers
148 case MISCREG_ICC_AP0R0:
149 case MISCREG_ICC_AP0R0_EL1: {
150 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
151 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
152 }
153
154 break;
155 }
156
157 case MISCREG_ICC_AP0R1:
158 case MISCREG_ICC_AP0R1_EL1:
159
160 // only implemented if supporting 6 or more bits of priority
161 case MISCREG_ICC_AP0R2:
162 case MISCREG_ICC_AP0R2_EL1:
163
164 // only implemented if supporting 7 or more bits of priority
165 case MISCREG_ICC_AP0R3:
166 case MISCREG_ICC_AP0R3_EL1:
167 // only implemented if supporting 7 or more bits of priority
168 return 0;
169
170 // Interrupt Group 0 Enable register EL1
171 case MISCREG_ICC_IGRPEN0:
172 case MISCREG_ICC_IGRPEN0_EL1: {
173 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
174 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
175 }
176
177 break;
178 }
179
180 case MISCREG_ICV_IGRPEN0_EL1: {
181 ICH_VMCR_EL2 ich_vmcr_el2 =
182 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
183 value = ich_vmcr_el2.VENG0;
184 break;
185 }
186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
194 break;
195 }
196
197 case MISCREG_ICV_IGRPEN1_EL1: {
198 ICH_VMCR_EL2 ich_vmcr_el2 =
199 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
200 value = ich_vmcr_el2.VENG1;
201 break;
202 }
203
204 // Interrupt Group 1 Enable register EL3
205 case MISCREG_ICC_MGRPEN1:
206 case MISCREG_ICC_IGRPEN1_EL3:
207 break;
208
209 // Running Priority Register
210 case MISCREG_ICC_RPR:
211 case MISCREG_ICC_RPR_EL1: {
212 if ((currEL() == EL1) && !inSecureState() &&
213 (hcr_imo || hcr_fmo)) {
214 return readMiscReg(MISCREG_ICV_RPR_EL1);
215 }
216
217 uint8_t rprio = highestActivePriority();
218
219 if (haveEL(EL3) && !inSecureState() &&
220 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
221 // Spec section 4.8.1
222 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
223 if ((rprio & 0x80) == 0) {
224 // If the current priority mask value is in the range of
225 // 0x00-0x7F a read access returns the value 0x0
226 rprio = 0;
227 } else if (rprio != 0xff) {
228 // If the current priority mask value is in the range of
229 // 0x80-0xFF a read access returns the Non-secure read of
230 // the current value
231 rprio = (rprio << 1) & 0xff;
232 }
233 }
234
235 value = rprio;
236 break;
237 }
238
239 // Virtual Running Priority Register
240 case MISCREG_ICV_RPR_EL1: {
241 value = virtualHighestActivePriority();
242 break;
243 }
244
245 // Highest Priority Pending Interrupt Register 0
246 case MISCREG_ICC_HPPIR0:
247 case MISCREG_ICC_HPPIR0_EL1: {
248 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
249 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
250 }
251
252 value = getHPPIR0();
253 break;
254 }
255
256 // Virtual Highest Priority Pending Interrupt Register 0
257 case MISCREG_ICV_HPPIR0_EL1: {
258 value = Gicv3::INTID_SPURIOUS;
259 int lr_idx = getHPPVILR();
260
261 if (lr_idx >= 0) {
262 ICH_LR_EL2 ich_lr_el2 =
263 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
264 Gicv3::GroupId group =
265 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
266
267 if (group == Gicv3::G0S) {
268 value = ich_lr_el2.vINTID;
269 }
270 }
271
272 break;
273 }
274
275 // Highest Priority Pending Interrupt Register 1
276 case MISCREG_ICC_HPPIR1:
277 case MISCREG_ICC_HPPIR1_EL1: {
278 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
279 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
280 }
281
282 value = getHPPIR1();
283 break;
284 }
285
286 // Virtual Highest Priority Pending Interrupt Register 1
287 case MISCREG_ICV_HPPIR1_EL1: {
288 value = Gicv3::INTID_SPURIOUS;
289 int lr_idx = getHPPVILR();
290
291 if (lr_idx >= 0) {
292 ICH_LR_EL2 ich_lr_el2 =
293 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
294 Gicv3::GroupId group =
295 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
296
297 if (group == Gicv3::G1NS) {
298 value = ich_lr_el2.vINTID;
299 }
300 }
301
302 break;
303 }
304
305 // Binary Point Register 0
306 case MISCREG_ICC_BPR0:
307 case MISCREG_ICC_BPR0_EL1:
308 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
309 return readMiscReg(MISCREG_ICV_BPR0_EL1);
310 }
311
312 M5_FALLTHROUGH;
313
314 // Binary Point Register 1
315 case MISCREG_ICC_BPR1:
316 case MISCREG_ICC_BPR1_EL1: {
317 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
318 return readMiscReg(MISCREG_ICV_BPR1_EL1);
319 }
320
321 Gicv3::GroupId group =
322 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
323
324 if (group == Gicv3::G1S && !inSecureState()) {
325 group = Gicv3::G1NS;
326 }
327
328 ICC_CTLR_EL1 icc_ctlr_el1_s =
329 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
330
331 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
332 icc_ctlr_el1_s.CBPR) {
333 group = Gicv3::G0S;
334 }
335
336 bool sat_inc = false;
337
338 ICC_CTLR_EL1 icc_ctlr_el1_ns =
339 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
340
341 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
342 icc_ctlr_el1_ns.CBPR) {
343 // Reads return BPR0 + 1 saturated to 7, WI
344 group = Gicv3::G0S;
345 sat_inc = true;
346 }
347
348 uint8_t bpr;
349
350 if (group == Gicv3::G0S) {
351 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
352 } else {
353 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
354 bpr = std::max(bpr, group == Gicv3::G1S ?
355 GIC_MIN_BPR : GIC_MIN_BPR_NS);
356 }
357
358 if (sat_inc) {
359 bpr++;
360
361 if (bpr > 7) {
362 bpr = 7;
363 }
364 }
365
366 value = bpr;
367 break;
368 }
369
370 // Virtual Binary Point Register 1
371 case MISCREG_ICV_BPR0_EL1:
372 case MISCREG_ICV_BPR1_EL1: {
373 Gicv3::GroupId group =
374 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
375 ICH_VMCR_EL2 ich_vmcr_el2 =
376 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
377 bool sat_inc = false;
378
379 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
380 // bpr0 + 1 saturated to 7, WI
381 group = Gicv3::G0S;
382 sat_inc = true;
383 }
384
385 uint8_t vbpr;
386
387 if (group == Gicv3::G0S) {
388 vbpr = ich_vmcr_el2.VBPR0;
389 } else {
390 vbpr = ich_vmcr_el2.VBPR1;
391 }
392
393 if (sat_inc) {
394 vbpr++;
395
396 if (vbpr > 7) {
397 vbpr = 7;
398 }
399 }
400
401 value = vbpr;
402 break;
403 }
404
405 // Interrupt Priority Mask Register
406 case MISCREG_ICC_PMR:
407 case MISCREG_ICC_PMR_EL1:
408 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
409 return readMiscReg(MISCREG_ICV_PMR_EL1);
410 }
411
412 if (haveEL(EL3) && !inSecureState() &&
413 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
414 // Spec section 4.8.1
415 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
416 if ((value & 0x80) == 0) {
417 // If the current priority mask value is in the range of
418 // 0x00-0x7F a read access returns the value 0x00.
419 value = 0;
420 } else if (value != 0xff) {
421 // If the current priority mask value is in the range of
422 // 0x80-0xFF a read access returns the Non-secure read of the
423 // current value.
424 value = (value << 1) & 0xff;
425 }
426 }
427
428 break;
429
430 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
431 ICH_VMCR_EL2 ich_vmcr_el2 =
432 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
433
434 value = ich_vmcr_el2.VPMR;
435 break;
436 }
437
438 // Interrupt Acknowledge Register 0
439 case MISCREG_ICC_IAR0:
440 case MISCREG_ICC_IAR0_EL1: {
441 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
442 return readMiscReg(MISCREG_ICV_IAR0_EL1);
443 }
444
445 uint32_t int_id;
446
447 if (hppiCanPreempt()) {
448 int_id = getHPPIR0();
449
450 // avoid activation for special interrupts
451 if (int_id < Gicv3::INTID_SECURE ||
452 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
453 activateIRQ(int_id, hppi.group);
454 }
455 } else {
456 int_id = Gicv3::INTID_SPURIOUS;
457 }
458
459 value = int_id;
460 break;
461 }
462
463 // Virtual Interrupt Acknowledge Register 0
464 case MISCREG_ICV_IAR0_EL1: {
465 int lr_idx = getHPPVILR();
466 uint32_t int_id = Gicv3::INTID_SPURIOUS;
467
468 if (lr_idx >= 0) {
469 ICH_LR_EL2 ich_lr_el2 =
470 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
471
472 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
473 int_id = ich_lr_el2.vINTID;
474
475 if (int_id < Gicv3::INTID_SECURE ||
476 int_id > Gicv3::INTID_SPURIOUS) {
477 virtualActivateIRQ(lr_idx);
478 } else {
479 // Bogus... Pseudocode says:
480 // - Move from pending to invalid...
481 // - Return de bogus id...
482 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
483 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
484 ich_lr_el2);
485 }
486 }
487 }
488
489 value = int_id;
490 virtualUpdate();
491 break;
492 }
493
494 // Interrupt Acknowledge Register 1
495 case MISCREG_ICC_IAR1:
496 case MISCREG_ICC_IAR1_EL1: {
497 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
498 return readMiscReg(MISCREG_ICV_IAR1_EL1);
499 }
500
501 uint32_t int_id;
502
503 if (hppiCanPreempt()) {
504 int_id = getHPPIR1();
505
506 // avoid activation for special interrupts
507 if (int_id < Gicv3::INTID_SECURE ||
508 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
509 activateIRQ(int_id, hppi.group);
510 }
511 } else {
512 int_id = Gicv3::INTID_SPURIOUS;
513 }
514
515 value = int_id;
516 break;
517 }
518
519 // Virtual Interrupt Acknowledge Register 1
520 case MISCREG_ICV_IAR1_EL1: {
521 int lr_idx = getHPPVILR();
522 uint32_t int_id = Gicv3::INTID_SPURIOUS;
523
524 if (lr_idx >= 0) {
525 ICH_LR_EL2 ich_lr_el2 =
526 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
527
528 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
529 int_id = ich_lr_el2.vINTID;
530
531 if (int_id < Gicv3::INTID_SECURE ||
532 int_id > Gicv3::INTID_SPURIOUS) {
533 virtualActivateIRQ(lr_idx);
534 } else {
535 // Bogus... Pseudocode says:
536 // - Move from pending to invalid...
537 // - Return de bogus id...
538 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
539 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
540 ich_lr_el2);
541 }
542 }
543 }
544
545 value = int_id;
546 virtualUpdate();
547 break;
548 }
549
550 // System Register Enable Register EL1
551 case MISCREG_ICC_SRE:
552 case MISCREG_ICC_SRE_EL1: {
553 /*
554 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
555 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
556 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
557 */
558 ICC_SRE_EL1 icc_sre_el1 = 0;
559 icc_sre_el1.SRE = 1;
560 icc_sre_el1.DIB = 1;
561 icc_sre_el1.DFB = 1;
562 value = icc_sre_el1;
563 break;
564 }
565
566 // System Register Enable Register EL2
567 case MISCREG_ICC_HSRE:
568 case MISCREG_ICC_SRE_EL2: {
569 /*
570 * Enable [3] == 1
571 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
572 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
573 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
574 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
575 */
576 ICC_SRE_EL2 icc_sre_el2 = 0;
577 icc_sre_el2.SRE = 1;
578 icc_sre_el2.DIB = 1;
579 icc_sre_el2.DFB = 1;
580 icc_sre_el2.Enable = 1;
581 value = icc_sre_el2;
582 break;
583 }
584
585 // System Register Enable Register EL3
586 case MISCREG_ICC_MSRE:
587 case MISCREG_ICC_SRE_EL3: {
588 /*
589 * Enable [3] == 1
590 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
591 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
592 * RAO/WI)
593 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
594 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
595 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
596 */
597 ICC_SRE_EL3 icc_sre_el3 = 0;
598 icc_sre_el3.SRE = 1;
599 icc_sre_el3.DIB = 1;
600 icc_sre_el3.DFB = 1;
601 icc_sre_el3.Enable = 1;
602 value = icc_sre_el3;
603 break;
604 }
605
606 // Control Register
607 case MISCREG_ICC_CTLR:
608 case MISCREG_ICC_CTLR_EL1: {
609 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
610 return readMiscReg(MISCREG_ICV_CTLR_EL1);
611 }
612
613 // Enforce value for RO bits
614 // ExtRange [19], INTIDs in the range 1024..8191 not supported
615 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
616 // A3V [15], supports non-zero values of the Aff3 field in SGI
617 // generation System registers
618 // SEIS [14], does not support generation of SEIs (deprecated)
619 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
620 // PRIbits [10:8], number of priority bits implemented, minus one
621 ICC_CTLR_EL1 icc_ctlr_el1 = value;
622 icc_ctlr_el1.ExtRange = 0;
623 icc_ctlr_el1.RSS = 1;
624 icc_ctlr_el1.A3V = 1;
625 icc_ctlr_el1.SEIS = 0;
626 icc_ctlr_el1.IDbits = 1;
627 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
628 value = icc_ctlr_el1;
629 break;
630 }
631
632 // Virtual Control Register
633 case MISCREG_ICV_CTLR_EL1: {
634 ICV_CTLR_EL1 icv_ctlr_el1 = value;
635 icv_ctlr_el1.RSS = 0;
636 icv_ctlr_el1.A3V = 1;
637 icv_ctlr_el1.SEIS = 0;
638 icv_ctlr_el1.IDbits = 1;
639 icv_ctlr_el1.PRIbits = 7;
640 value = icv_ctlr_el1;
641 break;
642 }
643
644 // Control Register
645 case MISCREG_ICC_MCTLR:
646 case MISCREG_ICC_CTLR_EL3: {
647 // Enforce value for RO bits
648 // ExtRange [19], INTIDs in the range 1024..8191 not supported
649 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
650 // nDS [17], supports disabling of security
651 // A3V [15], supports non-zero values of the Aff3 field in SGI
652 // generation System registers
653 // SEIS [14], does not support generation of SEIs (deprecated)
654 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
655 // PRIbits [10:8], number of priority bits implemented, minus one
656 ICC_CTLR_EL3 icc_ctlr_el3 = value;
657 icc_ctlr_el3.ExtRange = 0;
658 icc_ctlr_el3.RSS = 1;
659 icc_ctlr_el3.nDS = 0;
660 icc_ctlr_el3.A3V = 1;
661 icc_ctlr_el3.SEIS = 0;
662 icc_ctlr_el3.IDbits = 0;
663 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
664 value = icc_ctlr_el3;
665 break;
666 }
667
668 // Hyp Control Register
669 case MISCREG_ICH_HCR:
670 case MISCREG_ICH_HCR_EL2:
671 break;
672
673 // Hyp Active Priorities Group 0 Registers
674 case MISCREG_ICH_AP0R0:
675 case MISCREG_ICH_AP0R0_EL2:
676 break;
677
678 // Hyp Active Priorities Group 1 Registers
679 case MISCREG_ICH_AP1R0:
680 case MISCREG_ICH_AP1R0_EL2:
681 break;
682
683 // Maintenance Interrupt State Register
684 case MISCREG_ICH_MISR:
685 case MISCREG_ICH_MISR_EL2:
686 value = maintenanceInterruptStatus();
687 break;
688
689 // VGIC Type Register
690 case MISCREG_ICH_VTR:
691 case MISCREG_ICH_VTR_EL2: {
692 ICH_VTR_EL2 ich_vtr_el2 = value;
693
694 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
695 ich_vtr_el2.A3V = 1;
696 ich_vtr_el2.IDbits = 1;
697 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
698 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
699
700 value = ich_vtr_el2;
701 break;
702 }
703
704 // End of Interrupt Status Register
705 case MISCREG_ICH_EISR:
706 case MISCREG_ICH_EISR_EL2:
707 value = eoiMaintenanceInterruptStatus();
708 break;
709
710 // Empty List Register Status Register
711 case MISCREG_ICH_ELRSR:
712 case MISCREG_ICH_ELRSR_EL2:
713 value = 0;
714
715 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
716 ICH_LR_EL2 ich_lr_el2 =
717 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
718
719 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
720 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
721 value |= (1 << lr_idx);
722 }
723 }
724
725 break;
726
727 // List Registers
728 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
729 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
730 value = value >> 32;
731 break;
732
733 // List Registers
734 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
735 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
736 value = value & 0xffffffff;
737 break;
738
739 // List Registers
740 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
741 break;
742
743 // Virtual Machine Control Register
744 case MISCREG_ICH_VMCR:
745 case MISCREG_ICH_VMCR_EL2:
746 break;
747
748 default:
749 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
750 misc_reg, miscRegName[misc_reg]);
751 }
752
753 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
754 miscRegName[misc_reg], value);
755 return value;
756}
757
758void
759Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
760{
761 bool do_virtual_update = false;
762 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
763 miscRegName[misc_reg], val);
764 bool hcr_fmo = getHCREL2FMO();
765 bool hcr_imo = getHCREL2IMO();
766
767 switch (misc_reg) {
768 // Active Priorities Group 1 Registers
769 case MISCREG_ICC_AP1R0:
770 case MISCREG_ICC_AP1R0_EL1:
771 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
772 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
773 }
774
775 break;
776
777 case MISCREG_ICC_AP1R1:
778 case MISCREG_ICC_AP1R1_EL1:
779
780 // only implemented if supporting 6 or more bits of priority
781 case MISCREG_ICC_AP1R2:
782 case MISCREG_ICC_AP1R2_EL1:
783
784 // only implemented if supporting 7 or more bits of priority
785 case MISCREG_ICC_AP1R3:
786 case MISCREG_ICC_AP1R3_EL1:
787 // only implemented if supporting 7 or more bits of priority
788 break;
789
790 // Active Priorities Group 0 Registers
791 case MISCREG_ICC_AP0R0:
792 case MISCREG_ICC_AP0R0_EL1:
793 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
794 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
795 }
796
797 break;
798
799 case MISCREG_ICC_AP0R1:
800 case MISCREG_ICC_AP0R1_EL1:
801
802 // only implemented if supporting 6 or more bits of priority
803 case MISCREG_ICC_AP0R2:
804 case MISCREG_ICC_AP0R2_EL1:
805
806 // only implemented if supporting 7 or more bits of priority
807 case MISCREG_ICC_AP0R3:
808 case MISCREG_ICC_AP0R3_EL1:
809 // only implemented if supporting 7 or more bits of priority
810 break;
811
812 // End Of Interrupt Register 0
813 case MISCREG_ICC_EOIR0:
814 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
815 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
816 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
817 }
818
819 int int_id = val & 0xffffff;
820
821 // avoid activation for special interrupts
822 if (int_id >= Gicv3::INTID_SECURE &&
823 int_id <= Gicv3::INTID_SPURIOUS) {
824 return;
825 }
826
827 Gicv3::GroupId group = Gicv3::G0S;
828
829 if (highestActiveGroup() != group) {
830 return;
831 }
832
833 dropPriority(group);
834
835 if (!isEOISplitMode()) {
836 deactivateIRQ(int_id, group);
837 }
838
839 break;
840 }
841
842 // Virtual End Of Interrupt Register 0
843 case MISCREG_ICV_EOIR0_EL1: {
844 int int_id = val & 0xffffff;
845
846 // avoid deactivation for special interrupts
847 if (int_id >= Gicv3::INTID_SECURE &&
848 int_id <= Gicv3::INTID_SPURIOUS) {
849 return;
850 }
851
852 uint8_t drop_prio = virtualDropPriority();
853
854 if (drop_prio == 0xff) {
855 return;
856 }
857
858 int lr_idx = virtualFindActive(int_id);
859
860 if (lr_idx < 0) {
861 // No LR found matching
862 virtualIncrementEOICount();
863 } else {
864 ICH_LR_EL2 ich_lr_el2 =
865 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
866 Gicv3::GroupId lr_group =
867 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
868 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
869
870 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
871 //if (!virtualIsEOISplitMode())
872 {
873 virtualDeactivateIRQ(lr_idx);
874 }
875 }
876 }
877
878 virtualUpdate();
879 break;
880 }
881
882 // End Of Interrupt Register 1
883 case MISCREG_ICC_EOIR1:
884 case MISCREG_ICC_EOIR1_EL1: {
885 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
886 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
887 }
888
889 int int_id = val & 0xffffff;
890
891 // avoid deactivation for special interrupts
892 if (int_id >= Gicv3::INTID_SECURE &&
893 int_id <= Gicv3::INTID_SPURIOUS) {
894 return;
895 }
896
897 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
898
899 if (highestActiveGroup() == Gicv3::G0S) {
900 return;
901 }
902
903 if (distributor->DS == 0) {
904 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
905 return;
906 } else if (highestActiveGroup() == Gicv3::G1NS &&
907 !(!inSecureState() or (currEL() == EL3))) {
908 return;
909 }
910 }
911
912 dropPriority(group);
913
914 if (!isEOISplitMode()) {
915 deactivateIRQ(int_id, group);
916 }
917
918 break;
919 }
920
921 // Virtual End Of Interrupt Register 1
922 case MISCREG_ICV_EOIR1_EL1: {
923 int int_id = val & 0xffffff;
924
925 // avoid deactivation for special interrupts
926 if (int_id >= Gicv3::INTID_SECURE &&
927 int_id <= Gicv3::INTID_SPURIOUS) {
928 return;
929 }
930
931 uint8_t drop_prio = virtualDropPriority();
932
933 if (drop_prio == 0xff) {
934 return;
935 }
936
937 int lr_idx = virtualFindActive(int_id);
938
939 if (lr_idx < 0) {
940 // No matching LR found
941 virtualIncrementEOICount();
942 } else {
943 ICH_LR_EL2 ich_lr_el2 =
944 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
945 Gicv3::GroupId lr_group =
946 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
947 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
948
949 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
950 if (!virtualIsEOISplitMode()) {
951 virtualDeactivateIRQ(lr_idx);
952 }
953 }
954 }
955
956 virtualUpdate();
957 break;
958 }
959
960 // Deactivate Interrupt Register
961 case MISCREG_ICC_DIR:
962 case MISCREG_ICC_DIR_EL1: {
963 if ((currEL() == EL1) && !inSecureState() &&
964 (hcr_imo || hcr_fmo)) {
965 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
966 }
967
968 int int_id = val & 0xffffff;
969
970 // The following checks are as per spec pseudocode
971 // aarch64/support/ICC_DIR_EL1
972
973 // Check for spurious ID
974 if (int_id >= Gicv3::INTID_SECURE) {
975 return;
976 }
977
978 // EOI mode is not set, so don't deactivate
979 if (!isEOISplitMode()) {
980 return;
981 }
982
983 Gicv3::GroupId group =
984 int_id >= 32 ? distributor->getIntGroup(int_id) :
985 redistributor->getIntGroup(int_id);
986 bool irq_is_grp0 = group == Gicv3::G0S;
987 bool single_sec_state = distributor->DS;
988 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
989 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
990 bool route_fiq_to_el3 = scr_el3.fiq;
991 bool route_irq_to_el3 = scr_el3.irq;
992 bool route_fiq_to_el2 = hcr_fmo;
993 bool route_irq_to_el2 = hcr_imo;
994
995 switch (currEL()) {
996 case EL3:
997 break;
998
999 case EL2:
1000 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
1001 break;
1002 }
1003
1004 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
1005 break;
1006 }
1007
1008 return;
1009
1010 case EL1:
1011 if (!isSecureBelowEL3()) {
1012 if (single_sec_state && irq_is_grp0 &&
1013 !route_fiq_to_el3 && !route_fiq_to_el2) {
1014 break;
1015 }
1016
1017 if (!irq_is_secure && !irq_is_grp0 &&
1018 !route_irq_to_el3 && !route_irq_to_el2) {
1019 break;
1020 }
1021 } else {
1022 if (irq_is_grp0 && !route_fiq_to_el3) {
1023 break;
1024 }
1025
1026 if (!irq_is_grp0 &&
1027 (!irq_is_secure || !single_sec_state) &&
1028 !route_irq_to_el3) {
1029 break;
1030 }
1031 }
1032
1033 return;
1034
1035 default:
1036 break;
1037 }
1038
1039 deactivateIRQ(int_id, group);
1040 break;
1041 }
1042
1043 // Deactivate Virtual Interrupt Register
1044 case MISCREG_ICV_DIR_EL1: {
1045 int int_id = val & 0xffffff;
1046
1047 // avoid deactivation for special interrupts
1048 if (int_id >= Gicv3::INTID_SECURE &&
1049 int_id <= Gicv3::INTID_SPURIOUS) {
1050 return;
1051 }
1052
1053 if (!virtualIsEOISplitMode()) {
1054 return;
1055 }
1056
1057 int lr_idx = virtualFindActive(int_id);
1058
1059 if (lr_idx < 0) {
1060 // No matching LR found
1061 virtualIncrementEOICount();
1062 } else {
1063 virtualDeactivateIRQ(lr_idx);
1064 }
1065
1066 virtualUpdate();
1067 break;
1068 }
1069
1070 // Binary Point Register 0
1071 case MISCREG_ICC_BPR0:
1072 case MISCREG_ICC_BPR0_EL1:
1073 // Binary Point Register 1
1074 case MISCREG_ICC_BPR1:
1075 case MISCREG_ICC_BPR1_EL1: {
1076 if ((currEL() == EL1) && !inSecureState()) {
1077 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1078 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1079 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1080 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1081 }
1082 }
1083
1084 Gicv3::GroupId group =
1085 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1086
1087 if (group == Gicv3::G1S && !inSecureState()) {
1088 group = Gicv3::G1NS;
1089 }
1090
1091 ICC_CTLR_EL1 icc_ctlr_el1_s =
1092 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1093
1094 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1095 icc_ctlr_el1_s.CBPR) {
1096 group = Gicv3::G0S;
1097 }
1098
1099 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1100 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1101
1102 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1103 icc_ctlr_el1_ns.CBPR) {
1104 // BPR0 + 1 saturated to 7, WI
1105 return;
1106 }
1107
1108 uint8_t min_val = (group == Gicv3::G1NS) ?
1109 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1110 val &= 0x7;
1111
1112 if (val < min_val) {
1113 val = min_val;
1114 }
1115
1116 break;
1117 }
1118
1119 // Virtual Binary Point Register 0
1120 case MISCREG_ICV_BPR0_EL1:
1121 // Virtual Binary Point Register 1
1122 case MISCREG_ICV_BPR1_EL1: {
1123 Gicv3::GroupId group =
1124 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1125 ICH_VMCR_EL2 ich_vmcr_el2 =
1126 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1127
1128 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1129 // BPR0 + 1 saturated to 7, WI
1130 return;
1131 }
1132
1133 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1134
1135 if (group != Gicv3::G0S) {
1136 min_VPBR++;
1137 }
1138
1139 if (val < min_VPBR) {
1140 val = min_VPBR;
1141 }
1142
1143 if (group == Gicv3::G0S) {
1144 ich_vmcr_el2.VBPR0 = val;
1145 } else {
1146 ich_vmcr_el2.VBPR1 = val;
1147 }
1148
1149 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1150 do_virtual_update = true;
1151 break;
1152 }
1153
1154 // Control Register EL1
1155 case MISCREG_ICC_CTLR:
1156 case MISCREG_ICC_CTLR_EL1: {
1157 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1158 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1159 }
1160
1161 /*
1162 * ExtRange is RO.
1163 * RSS is RO.
1164 * A3V is RO.
1165 * SEIS is RO.
1166 * IDbits is RO.
1167 * PRIbits is RO.
1168 */
1169 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1170 ICC_CTLR_EL1 icc_ctlr_el1 =
1171 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1172
1173 ICC_CTLR_EL3 icc_ctlr_el3 =
1174 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1175
1176 // The following could be refactored but it is following
1177 // spec description section 9.2.6 point by point.
1178
1179 // PMHE
1180 if (haveEL(EL3)) {
1181 // PMHE is alias of ICC_CTLR_EL3.PMHE
1182
1183 if (distributor->DS == 0) {
1184 // PMHE is RO
1185 } else if (distributor->DS == 1) {
1186 // PMHE is RW
1187 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1188 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1189 }
1190 } else {
1191 // PMHE is RW (by implementation choice)
1192 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1193 }
1194
1195 // EOImode
1196 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1197
1198 if (inSecureState()) {
1199 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1200 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1201 } else {
1202 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1203 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1204 }
1205
1206 // CBPR
1207 if (haveEL(EL3)) {
1208 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1209
1210 if (distributor->DS == 0) {
1211 // CBPR is RO
1212 } else {
1213 // CBPR is RW
1214 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1215
1216 if (inSecureState()) {
1217 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1218 } else {
1219 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1220 }
1221 }
1222 } else {
1223 // CBPR is RW
1224 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1225 }
1226
1227 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1228
1229 val = icc_ctlr_el1;
1230 break;
1231 }
1232
1233 // Virtual Control Register
1234 case MISCREG_ICV_CTLR_EL1: {
1235 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1236 ICV_CTLR_EL1 icv_ctlr_el1 =
1237 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1238 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1239 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1240 val = icv_ctlr_el1;
1241
1242 // Aliases
1243 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1244 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1245 ICH_VMCR_EL2 ich_vmcr_el2 =
1246 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1247 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1248 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1249 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1250 break;
1251 }
1252
1253 // Control Register EL3
1254 case MISCREG_ICC_MCTLR:
1255 case MISCREG_ICC_CTLR_EL3: {
1256 /*
1257 * ExtRange is RO.
1258 * RSS is RO.
1259 * nDS is RO.
1260 * A3V is RO.
1261 * SEIS is RO.
1262 * IDbits is RO.
1263 * PRIbits is RO.
1264 * PMHE is RAO/WI, priority-based routing is always used.
1265 */
1266 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1267
1268 // Aliases
1269 if (haveEL(EL3))
1270 {
1271 ICC_CTLR_EL1 icc_ctlr_el1_s =
1272 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1273 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1274 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1275
1276 // ICC_CTLR_EL1(NS).EOImode is an alias of
1277 // ICC_CTLR_EL3.EOImode_EL1NS
1278 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1279 // ICC_CTLR_EL1(S).EOImode is an alias of
1280 // ICC_CTLR_EL3.EOImode_EL1S
1281 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1282 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1283 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1284 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1285 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1286
1287 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1288 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1289 icc_ctlr_el1_ns);
1290 }
1291
1292 ICC_CTLR_EL3 icc_ctlr_el3 =
1293 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1294
1295 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1296 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1297 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1298 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1299 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1300 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1301
1302 val = icc_ctlr_el3;
1303 break;
1304 }
1305
1306 // Priority Mask Register
1307 case MISCREG_ICC_PMR:
1308 case MISCREG_ICC_PMR_EL1: {
1309 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1310 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1311 }
1312
1313 val &= 0xff;
1314 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1315
1316 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1317 // Spec section 4.8.1
1318 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1319 RegVal old_icc_pmr_el1 =
1320 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1321
1322 if (!(old_icc_pmr_el1 & 0x80)) {
1323 // If the current priority mask value is in the range of
1324 // 0x00-0x7F then WI
1325 return;
1326 }
1327
1328 // If the current priority mask value is in the range of
1329 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1330 // based on the Non-secure read of the priority mask value
1331 // written to the register.
1332
1333 val = (val >> 1) | 0x80;
1334 }
1335
1336 val &= ~0U << (8 - PRIORITY_BITS);
1337 break;
1338 }
1339
1340 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1341 ICH_VMCR_EL2 ich_vmcr_el2 =
1342 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1343 ich_vmcr_el2.VPMR = val & 0xff;
1344
1345 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1346 virtualUpdate();
1347 return;
1348 }
1349
1350 // Interrupt Group 0 Enable Register EL1
1351 case MISCREG_ICC_IGRPEN0:
1352 case MISCREG_ICC_IGRPEN0_EL1: {
1353 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1354 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1355 }
1356
1357 break;
1358 }
1359
1360 // Virtual Interrupt Group 0 Enable register
1361 case MISCREG_ICV_IGRPEN0_EL1: {
1362 bool enable = val & 0x1;
1363 ICH_VMCR_EL2 ich_vmcr_el2 =
1364 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1365 ich_vmcr_el2.VENG0 = enable;
1366 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1367 virtualUpdate();
1368 return;
1369 }
1370
1371 // Interrupt Group 1 Enable register EL1
1372 case MISCREG_ICC_IGRPEN1:
1373 case MISCREG_ICC_IGRPEN1_EL1: {
1374 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1375 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1376 }
1377
1378 if (haveEL(EL3)) {
1379 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1380 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1381 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1382
1383 if (inSecureState()) {
1384 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1385 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1386 } else {
1387 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1388 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1389 }
1390
1391 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1392 icc_igrpen1_el3);
1393 }
1394
1395 break;
1396 }
1397
1398 // Virtual Interrupt Group 1 Enable register
1399 case MISCREG_ICV_IGRPEN1_EL1: {
1400 bool enable = val & 0x1;
1401 ICH_VMCR_EL2 ich_vmcr_el2 =
1402 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1403 ich_vmcr_el2.VENG1 = enable;
1404 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1405 virtualUpdate();
1406 return;
1407 }
1408
1409 // Interrupt Group 1 Enable register
1410 case MISCREG_ICC_MGRPEN1:
1411 case MISCREG_ICC_IGRPEN1_EL3: {
1412 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1413 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1414 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1415
1416 if (inSecureState()) {
1417 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1418 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1419 } else {
1420 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1421 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1422 }
1423
1424 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1425 break;
1426 }
1427
1428 // Software Generated Interrupt Group 0 Register
1429 case MISCREG_ICC_SGI0R:
1430 case MISCREG_ICC_SGI0R_EL1:
1431 generateSGI(val, Gicv3::G0S);
1432 break;
1433
1434 // Software Generated Interrupt Group 1 Register
1435 case MISCREG_ICC_SGI1R:
1436 case MISCREG_ICC_SGI1R_EL1: {
1437 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
1438
1439 generateSGI(val, group);
1440 break;
1441 }
1442
1443 // Alias Software Generated Interrupt Group 1 Register
1444 case MISCREG_ICC_ASGI1R:
1445 case MISCREG_ICC_ASGI1R_EL1: {
1446 Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S;
1447
1448 generateSGI(val, group);
1449 break;
1450 }
1451
1452 // System Register Enable Register EL1
1453 case MISCREG_ICC_SRE:
1454 case MISCREG_ICC_SRE_EL1:
1455 // System Register Enable Register EL2
1456 case MISCREG_ICC_HSRE:
1457 case MISCREG_ICC_SRE_EL2:
1458 // System Register Enable Register EL3
1459 case MISCREG_ICC_MSRE:
1460 case MISCREG_ICC_SRE_EL3:
1461 // All bits are RAO/WI
1462 return;
1463
1464 // Hyp Control Register
1465 case MISCREG_ICH_HCR:
1466 case MISCREG_ICH_HCR_EL2: {
1467 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1468 ICH_HCR_EL2 ich_hcr_el2 =
1469 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1470
1471 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1472 {
1473 // EOIcount - Permitted behaviors are:
1474 // - Increment EOIcount.
1475 // - Leave EOIcount unchanged.
1476 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1477 }
1478
1479 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1480 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1481 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1482 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1483 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1484 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1485 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1486 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1487 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1488 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1489 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1490 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1491 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1492 val = ich_hcr_el2;
1493 do_virtual_update = true;
1494 break;
1495 }
1496
1497 // List Registers
1498 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1499 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1500 ICH_LRC requested_ich_lrc = val;
1501 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1502
1503 ich_lrc.State = requested_ich_lrc.State;
1504 ich_lrc.HW = requested_ich_lrc.HW;
1505 ich_lrc.Group = requested_ich_lrc.Group;
1506
1507 // Priority, bits [23:16]
1508 // At least five bits must be implemented.
1509 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1510 // We implement 5 bits.
1511 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1512 (ich_lrc.Priority & 0x07);
1513
1514 // pINTID, bits [12:0]
1515 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1516 // - Bits[12:10] : RES0.
1517 // - Bit[9] : EOI.
1518 // - Bits[8:0] : RES0.
1519 // When ICH_LR<n>.HW is 1:
1520 // - This field is only required to implement enough bits to hold a
1521 // valid value for the implemented INTID size. Any unused higher
1522 // order bits are RES0.
1523 if (requested_ich_lrc.HW == 0) {
1524 ich_lrc.EOI = requested_ich_lrc.EOI;
1525 } else {
1526 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1527 }
1528
1529 val = ich_lrc;
1530 do_virtual_update = true;
1531 break;
1532 }
1533
1534 // List Registers
1535 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1536 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1537 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1538 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1539 do_virtual_update = true;
1540 break;
1541 }
1542
1543 // List Registers
1544 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1545 ICH_LR_EL2 requested_ich_lr_el2 = val;
1546 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1547
1548 ich_lr_el2.State = requested_ich_lr_el2.State;
1549 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1550 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1551
1552 // Priority, bits [55:48]
1553 // At least five bits must be implemented.
1554 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1555 // We implement 5 bits.
1556 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1557 (ich_lr_el2.Priority & 0x07);
1558
1559 // pINTID, bits [44:32]
1560 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1561 // - Bits[44:42] : RES0.
1562 // - Bit[41] : EOI.
1563 // - Bits[40:32] : RES0.
1564 // When ICH_LR<n>_EL2.HW is 1:
1565 // - This field is only required to implement enough bits to hold a
1566 // valid value for the implemented INTID size. Any unused higher
1567 // order bits are RES0.
1568 if (requested_ich_lr_el2.HW == 0) {
1569 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1570 } else {
1571 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1572 }
1573
1574 // vINTID, bits [31:0]
1575 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1576 // though at least 16 bits must be implemented.
1577 // Unimplemented bits are RES0.
1578 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1579
1580 val = ich_lr_el2;
1581 do_virtual_update = true;
1582 break;
1583 }
1584
1585 // Virtual Machine Control Register
1586 case MISCREG_ICH_VMCR:
1587 case MISCREG_ICH_VMCR_EL2: {
1588 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1589 ICH_VMCR_EL2 ich_vmcr_el2 =
1590 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1591 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1592 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1593
1594 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1595 ich_vmcr_el2.VBPR0 = min_vpr0;
1596 } else {
1597 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1598 }
1599
1600 uint8_t min_vpr1 = min_vpr0 + 1;
1601
1602 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1603 ich_vmcr_el2.VBPR1 = min_vpr1;
1604 } else {
1605 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1606 }
1607
1608 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1609 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1610 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1611 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1612 val = ich_vmcr_el2;
1613 break;
1614 }
1615
1616 // Hyp Active Priorities Group 0 Registers
1617 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1618 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1619 // Hyp Active Priorities Group 1 Registers
1620 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1621 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1622 break;
1623
1624 default:
1625 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1626 misc_reg, miscRegName[misc_reg]);
1627 }
1628
1629 isa->setMiscRegNoEffect(misc_reg, val);
1630
1631 if (do_virtual_update) {
1632 virtualUpdate();
1633 }
1634}
1635
1636int
1637Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1638{
1639 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1640 ICH_LR_EL2 ich_lr_el2 =
1641 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1642
1643 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1644 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1645 (ich_lr_el2.vINTID == int_id)) {
1646 return lr_idx;
1647 }
1648 }
1649
1650 return -1;
1651}
1652
1653uint32_t
1654Gicv3CPUInterface::getHPPIR0() const
1655{
1656 if (hppi.prio == 0xff) {
1657 return Gicv3::INTID_SPURIOUS;
1658 }
1659
1660 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1661
1662 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1663 // interrupt for the other state pending
1664 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1665 }
1666
1667 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1668 return Gicv3::INTID_SPURIOUS;
1669 }
1670
1671 if (irq_is_secure && !inSecureState()) {
1672 // Secure interrupts not visible in Non-secure
1673 return Gicv3::INTID_SPURIOUS;
1674 }
1675
1676 return hppi.intid;
1677}
1678
1679uint32_t
1680Gicv3CPUInterface::getHPPIR1() const
1681{
1682 if (hppi.prio == 0xff) {
1683 return Gicv3::INTID_SPURIOUS;
1684 }
1685
1686 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1687 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1688 if (hppi.group == Gicv3::G0S) {
1689 return Gicv3::INTID_SECURE;
1690 } else if (hppi.group == Gicv3::G1NS) {
1691 return Gicv3::INTID_NONSECURE;
1692 }
1693 }
1694
1695 if (hppi.group == Gicv3::G0S) {
1696 return Gicv3::INTID_SPURIOUS;
1697 }
1698
1699 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1700
1701 if (irq_is_secure) {
1702 if (!inSecureState()) {
1703 // Secure interrupts not visible in Non-secure
1704 return Gicv3::INTID_SPURIOUS;
1705 }
1706 } else if (!isEL3OrMon() && inSecureState()) {
1707 // Group 1 non-secure interrupts not visible in Secure EL1
1708 return Gicv3::INTID_SPURIOUS;
1709 }
1710
1711 return hppi.intid;
1712}
1713
1714void
1715Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1716{
1717 int apr_misc_reg;
1718 RegVal apr;
1719 apr_misc_reg = group == Gicv3::G0S ?
1720 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1721 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1722
1723 if (apr) {
1724 apr &= apr - 1;
1725 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1726 }
1727
1728 update();
1729}
1730
1731uint8_t
1732Gicv3CPUInterface::virtualDropPriority()
1733{
1734 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1735
1736 for (int i = 0; i < apr_max; i++) {
1737 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1738 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1739
1740 if (!vapr0 && !vapr1) {
1741 continue;
1742 }
1743
1744 int vapr0_count = ctz32(vapr0);
1745 int vapr1_count = ctz32(vapr1);
1746
1747 if (vapr0_count <= vapr1_count) {
1748 vapr0 &= vapr0 - 1;
1749 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1750 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1751 } else {
1752 vapr1 &= vapr1 - 1;
1753 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1754 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1755 }
1756 }
1757
1758 return 0xff;
1759}
1760
1761void
1762Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1763{
1764 uint8_t aff3 = bits(val, 55, 48);
1765 uint8_t aff2 = bits(val, 39, 32);
1766 uint8_t aff1 = bits(val, 23, 16);;
1767 uint16_t target_list = bits(val, 15, 0);
1768 uint32_t int_id = bits(val, 27, 24);
1769 bool irm = bits(val, 40, 40);
1770 uint8_t rs = bits(val, 47, 44);
1771
1772 bool ns = !inSecureState();
1773
1774 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1775 Gicv3Redistributor * redistributor_i =
1776 gic->getRedistributor(i);
1777 uint32_t affinity_i = redistributor_i->getAffinity();
1778
1779 if (irm) {
1780 // Interrupts routed to all PEs in the system,
1781 // excluding "self"
1782 if (affinity_i == redistributor->getAffinity()) {
1783 continue;
1784 }
1785 } else {
1786 // Interrupts routed to the PEs specified by
1787 // Aff3.Aff2.Aff1.<target list>
1788 if ((affinity_i >> 8) !=
1789 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1790 continue;
1791 }
1792
1793 uint8_t aff0_i = bits(affinity_i, 7, 0);
1794
1795 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1796 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1797 continue;
1798 }
1799 }
1800
1801 redistributor_i->sendSGI(int_id, group, ns);
1802 }
1803}
1804
1805void
1806Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1807{
1808 // Update active priority registers.
1809 uint32_t prio = hppi.prio & 0xf8;
1810 int apr_bit = prio >> (8 - PRIORITY_BITS);
1811 int reg_bit = apr_bit % 32;
1812 int apr_idx = group == Gicv3::G0S ?
1813 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1814 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1815 apr |= (1 << reg_bit);
1816 isa->setMiscRegNoEffect(apr_idx, apr);
1817
1818 // Move interrupt state from pending to active.
1819 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1820 // SGI or PPI, redistributor
1821 redistributor->activateIRQ(int_id);
|
1995Gicv3CPUInterface::update()
1996{
1997 bool signal_IRQ = false;
1998 bool signal_FIQ = false;
1999
2000 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2001 /*
2002 * Secure enabled GIC sending a G1S IRQ to a secure disabled
2003 * CPU -> send G0 IRQ
2004 */
2005 hppi.group = Gicv3::G0S;
2006 }
2007
2008 if (hppiCanPreempt()) {
2009 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
2010 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
2011 "posting int as %d!\n", int_type);
2012 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
2013 }
2014
2015 if (signal_IRQ) {
2016 gic->postInt(cpuId, ArmISA::INT_IRQ);
2017 } else {
2018 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
2019 }
2020
2021 if (signal_FIQ) {
2022 gic->postInt(cpuId, ArmISA::INT_FIQ);
2023 } else {
2024 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
2025 }
2026}
2027
2028void
2029Gicv3CPUInterface::virtualUpdate()
2030{
2031 bool signal_IRQ = false;
2032 bool signal_FIQ = false;
2033 int lr_idx = getHPPVILR();
2034
2035 if (lr_idx >= 0) {
2036 ICH_LR_EL2 ich_lr_el2 =
2037 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2038
2039 if (hppviCanPreempt(lr_idx)) {
2040 if (ich_lr_el2.Group) {
2041 signal_IRQ = true;
2042 } else {
2043 signal_FIQ = true;
2044 }
2045 }
2046 }
2047
2048 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2049
2050 if (ich_hcr_el2.En) {
2051 if (maintenanceInterruptStatus()) {
2052 maintenanceInterrupt->raise();
2053 }
2054 }
2055
2056 if (signal_IRQ) {
2057 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2058 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2059 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2060 } else {
2061 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2062 }
2063
2064 if (signal_FIQ) {
2065 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2066 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2067 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2068 } else {
2069 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2070 }
2071}
2072
2073// Returns the index of the LR with the HPPI
2074int
2075Gicv3CPUInterface::getHPPVILR() const
2076{
2077 int idx = -1;
2078 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2079
2080 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2081 // VG0 and VG1 disabled...
2082 return idx;
2083 }
2084
2085 uint8_t highest_prio = 0xff;
2086
2087 for (int i = 0; i < 16; i++) {
2088 ICH_LR_EL2 ich_lr_el2 =
2089 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2090
2091 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2092 continue;
2093 }
2094
2095 if (ich_lr_el2.Group) {
2096 // VG1
2097 if (!ich_vmcr_el2.VENG1) {
2098 continue;
2099 }
2100 } else {
2101 // VG0
2102 if (!ich_vmcr_el2.VENG0) {
2103 continue;
2104 }
2105 }
2106
2107 uint8_t prio = ich_lr_el2.Priority;
2108
2109 if (prio < highest_prio) {
2110 highest_prio = prio;
2111 idx = i;
2112 }
2113 }
2114
2115 return idx;
2116}
2117
2118bool
2119Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2120{
2121 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2122 if (!ich_hcr_el2.En) {
2123 // virtual interface is disabled
2124 return false;
2125 }
2126
2127 ICH_LR_EL2 ich_lr_el2 =
2128 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2129 uint8_t prio = ich_lr_el2.Priority;
2130 uint8_t vpmr =
2131 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2132
2133 if (prio >= vpmr) {
2134 // prioriry masked
2135 return false;
2136 }
2137
2138 uint8_t rprio = virtualHighestActivePriority();
2139
2140 if (rprio == 0xff) {
2141 return true;
2142 }
2143
2144 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2145 uint32_t prio_mask = virtualGroupPriorityMask(group);
2146
2147 if ((prio & prio_mask) < (rprio & prio_mask)) {
2148 return true;
2149 }
2150
2151 return false;
2152}
2153
2154uint8_t
2155Gicv3CPUInterface::virtualHighestActivePriority() const
2156{
2157 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2158
2159 for (int i = 0; i < num_aprs; i++) {
2160 RegVal vapr =
2161 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2162 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2163
2164 if (!vapr) {
2165 continue;
2166 }
2167
2168 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2169 }
2170
2171 // no active interrups, return idle priority
2172 return 0xff;
2173}
2174
2175void
2176Gicv3CPUInterface::virtualIncrementEOICount()
2177{
2178 // Increment the EOICOUNT field in ICH_HCR_EL2
2179 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2180 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2181 EOI_cout++;
2182 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2183 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2184}
2185
2186// spec section 4.6.2
2187ArmISA::InterruptTypes
2188Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2189{
2190 bool is_fiq = false;
2191
2192 switch (group) {
2193 case Gicv3::G0S:
2194 is_fiq = true;
2195 break;
2196
2197 case Gicv3::G1S:
2198 is_fiq = (distributor->DS == 0) &&
2199 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2200 break;
2201
2202 case Gicv3::G1NS:
2203 is_fiq = (distributor->DS == 0) && inSecureState();
2204 break;
2205
2206 default:
2207 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2208 }
2209
2210 if (is_fiq) {
2211 return ArmISA::INT_FIQ;
2212 } else {
2213 return ArmISA::INT_IRQ;
2214 }
2215}
2216
2217bool
2218Gicv3CPUInterface::hppiCanPreempt()
2219{
2220 if (hppi.prio == 0xff) {
2221 // there is no pending interrupt
2222 return false;
2223 }
2224
2225 if (!groupEnabled(hppi.group)) {
2226 // group disabled at CPU interface
2227 return false;
2228 }
2229
2230 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2231 // priority masked
2232 return false;
2233 }
2234
2235 uint8_t rprio = highestActivePriority();
2236
2237 if (rprio == 0xff) {
2238 return true;
2239 }
2240
2241 uint32_t prio_mask = groupPriorityMask(hppi.group);
2242
2243 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2244 return true;
2245 }
2246
2247 return false;
2248}
2249
2250uint8_t
2251Gicv3CPUInterface::highestActivePriority() const
2252{
2253 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2254 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2255 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2256
2257 if (apr) {
2258 return ctz32(apr) << (GIC_MIN_BPR + 1);
2259 }
2260
2261 // no active interrups, return idle priority
2262 return 0xff;
2263}
2264
2265bool
2266Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2267{
2268 switch (group) {
2269 case Gicv3::G0S: {
2270 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2271 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2272 return icc_igrpen0_el1.Enable;
2273 }
2274
2275 case Gicv3::G1S: {
2276 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2277 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2278 return icc_igrpen1_el1_s.Enable;
2279 }
2280
2281 case Gicv3::G1NS: {
2282 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2283 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2284 return icc_igrpen1_el1_ns.Enable;
2285 }
2286
2287 default:
2288 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2289 }
2290}
2291
2292bool
2293Gicv3CPUInterface::inSecureState() const
2294{
2295 if (!gic->getSystem()->haveSecurity()) {
2296 return false;
2297 }
2298
2299 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2300 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2301 return ArmISA::inSecureState(scr, cpsr);
2302}
2303
2304int
2305Gicv3CPUInterface::currEL() const
2306{
2307 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2308 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2309
2310 if (is_64) {
2311 return (ExceptionLevel)(uint8_t) cpsr.el;
2312 } else {
2313 switch (cpsr.mode) {
2314 case MODE_USER:
2315 return 0;
2316
2317 case MODE_HYP:
2318 return 2;
2319
2320 case MODE_MON:
2321 return 3;
2322
2323 default:
2324 return 1;
2325 }
2326 }
2327}
2328
2329bool
2330Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2331{
2332 switch (el) {
2333 case EL0:
2334 case EL1:
2335 return true;
2336
2337 case EL2:
2338 return gic->getSystem()->haveVirtualization();
2339
2340 case EL3:
2341 return gic->getSystem()->haveSecurity();
2342
2343 default:
2344 warn("Unimplemented Exception Level\n");
2345 return false;
2346 }
2347}
2348
2349bool
2350Gicv3CPUInterface::isSecureBelowEL3() const
2351{
2352 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2353 return haveEL(EL3) && scr.ns == 0;
2354}
2355
2356bool
2357Gicv3CPUInterface::isAA64() const
2358{
2359 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2360 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2361}
2362
2363bool
2364Gicv3CPUInterface::isEL3OrMon() const
2365{
2366 if (haveEL(EL3)) {
2367 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2368 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2369
2370 if (is_64 && (cpsr.el == EL3)) {
2371 return true;
2372 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2373 return true;
2374 }
2375 }
2376
2377 return false;
2378}
2379
2380// Computes ICH_EISR_EL2
2381uint64_t
2382Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2383{
2384 // ICH_EISR_EL2
2385 // Bits [63:16] - RES0
2386 // Status<n>, bit [n], for n = 0 to 15
2387 // EOI maintenance interrupt status bit for List register <n>:
2388 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2389 // maintenance interrupt.
2390 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2391 // interrupt that has not been handled.
2392 //
2393 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2394 // of the following are true:
2395 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2396 // - ICH_LR<n>_EL2.HW is 0.
2397 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2398
2399 uint64_t value = 0;
2400
2401 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2402 ICH_LR_EL2 ich_lr_el2 =
2403 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2404
2405 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2406 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2407 value |= (1 << lr_idx);
2408 }
2409 }
2410
2411 return value;
2412}
2413
2414Gicv3CPUInterface::ICH_MISR_EL2
2415Gicv3CPUInterface::maintenanceInterruptStatus() const
2416{
2417 // Comments are copied from SPEC section 9.4.7 (ID012119)
2418 ICH_MISR_EL2 ich_misr_el2 = 0;
2419 ICH_HCR_EL2 ich_hcr_el2 =
2420 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2421 ICH_VMCR_EL2 ich_vmcr_el2 =
2422 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2423
2424 // End Of Interrupt. [bit 0]
2425 // This maintenance interrupt is asserted when at least one bit in
2426 // ICH_EISR_EL2 is 1.
2427
2428 if (eoiMaintenanceInterruptStatus()) {
2429 ich_misr_el2.EOI = 1;
2430 }
2431
2432 // Underflow. [bit 1]
2433 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2434 // zero or one of the List register entries are marked as a valid
2435 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2436 // do not equal 0x0.
2437 uint32_t num_valid_interrupts = 0;
2438 uint32_t num_pending_interrupts = 0;
2439
2440 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2441 ICH_LR_EL2 ich_lr_el2 =
2442 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2443
2444 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2445 num_valid_interrupts++;
2446 }
2447
2448 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2449 num_pending_interrupts++;
2450 }
2451 }
2452
2453 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2454 ich_misr_el2.U = 1;
2455 }
2456
2457 // List Register Entry Not Present. [bit 2]
2458 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2459 // and ICH_HCR_EL2.EOIcount is non-zero.
2460 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2461 ich_misr_el2.LRENP = 1;
2462 }
2463
2464 // No Pending. [bit 3]
2465 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2466 // no List register is in pending state.
2467 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2468 ich_misr_el2.NP = 1;
2469 }
2470
2471 // vPE Group 0 Enabled. [bit 4]
2472 // This maintenance interrupt is asserted when
2473 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2474 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2475 ich_misr_el2.VGrp0E = 1;
2476 }
2477
2478 // vPE Group 0 Disabled. [bit 5]
2479 // This maintenance interrupt is asserted when
2480 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2481 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2482 ich_misr_el2.VGrp0D = 1;
2483 }
2484
2485 // vPE Group 1 Enabled. [bit 6]
2486 // This maintenance interrupt is asserted when
2487 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2488 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2489 ich_misr_el2.VGrp1E = 1;
2490 }
2491
2492 // vPE Group 1 Disabled. [bit 7]
2493 // This maintenance interrupt is asserted when
2494 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2495 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2496 ich_misr_el2.VGrp1D = 1;
2497 }
2498
2499 return ich_misr_el2;
2500}
2501
2502void
2503Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2504{
2505 SERIALIZE_SCALAR(hppi.intid);
2506 SERIALIZE_SCALAR(hppi.prio);
2507 SERIALIZE_ENUM(hppi.group);
2508}
2509
2510void
2511Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2512{
2513 UNSERIALIZE_SCALAR(hppi.intid);
2514 UNSERIALIZE_SCALAR(hppi.prio);
2515 UNSERIALIZE_ENUM(hppi.group);
2516}
| 2002Gicv3CPUInterface::update()
2003{
2004 bool signal_IRQ = false;
2005 bool signal_FIQ = false;
2006
2007 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2008 /*
2009 * Secure enabled GIC sending a G1S IRQ to a secure disabled
2010 * CPU -> send G0 IRQ
2011 */
2012 hppi.group = Gicv3::G0S;
2013 }
2014
2015 if (hppiCanPreempt()) {
2016 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
2017 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
2018 "posting int as %d!\n", int_type);
2019 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
2020 }
2021
2022 if (signal_IRQ) {
2023 gic->postInt(cpuId, ArmISA::INT_IRQ);
2024 } else {
2025 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
2026 }
2027
2028 if (signal_FIQ) {
2029 gic->postInt(cpuId, ArmISA::INT_FIQ);
2030 } else {
2031 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
2032 }
2033}
2034
2035void
2036Gicv3CPUInterface::virtualUpdate()
2037{
2038 bool signal_IRQ = false;
2039 bool signal_FIQ = false;
2040 int lr_idx = getHPPVILR();
2041
2042 if (lr_idx >= 0) {
2043 ICH_LR_EL2 ich_lr_el2 =
2044 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2045
2046 if (hppviCanPreempt(lr_idx)) {
2047 if (ich_lr_el2.Group) {
2048 signal_IRQ = true;
2049 } else {
2050 signal_FIQ = true;
2051 }
2052 }
2053 }
2054
2055 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2056
2057 if (ich_hcr_el2.En) {
2058 if (maintenanceInterruptStatus()) {
2059 maintenanceInterrupt->raise();
2060 }
2061 }
2062
2063 if (signal_IRQ) {
2064 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2065 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2066 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2067 } else {
2068 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2069 }
2070
2071 if (signal_FIQ) {
2072 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2073 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2074 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2075 } else {
2076 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2077 }
2078}
2079
2080// Returns the index of the LR with the HPPI
2081int
2082Gicv3CPUInterface::getHPPVILR() const
2083{
2084 int idx = -1;
2085 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2086
2087 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2088 // VG0 and VG1 disabled...
2089 return idx;
2090 }
2091
2092 uint8_t highest_prio = 0xff;
2093
2094 for (int i = 0; i < 16; i++) {
2095 ICH_LR_EL2 ich_lr_el2 =
2096 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2097
2098 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2099 continue;
2100 }
2101
2102 if (ich_lr_el2.Group) {
2103 // VG1
2104 if (!ich_vmcr_el2.VENG1) {
2105 continue;
2106 }
2107 } else {
2108 // VG0
2109 if (!ich_vmcr_el2.VENG0) {
2110 continue;
2111 }
2112 }
2113
2114 uint8_t prio = ich_lr_el2.Priority;
2115
2116 if (prio < highest_prio) {
2117 highest_prio = prio;
2118 idx = i;
2119 }
2120 }
2121
2122 return idx;
2123}
2124
2125bool
2126Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2127{
2128 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2129 if (!ich_hcr_el2.En) {
2130 // virtual interface is disabled
2131 return false;
2132 }
2133
2134 ICH_LR_EL2 ich_lr_el2 =
2135 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2136 uint8_t prio = ich_lr_el2.Priority;
2137 uint8_t vpmr =
2138 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2139
2140 if (prio >= vpmr) {
2141 // prioriry masked
2142 return false;
2143 }
2144
2145 uint8_t rprio = virtualHighestActivePriority();
2146
2147 if (rprio == 0xff) {
2148 return true;
2149 }
2150
2151 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2152 uint32_t prio_mask = virtualGroupPriorityMask(group);
2153
2154 if ((prio & prio_mask) < (rprio & prio_mask)) {
2155 return true;
2156 }
2157
2158 return false;
2159}
2160
2161uint8_t
2162Gicv3CPUInterface::virtualHighestActivePriority() const
2163{
2164 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2165
2166 for (int i = 0; i < num_aprs; i++) {
2167 RegVal vapr =
2168 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2169 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2170
2171 if (!vapr) {
2172 continue;
2173 }
2174
2175 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2176 }
2177
2178 // no active interrups, return idle priority
2179 return 0xff;
2180}
2181
2182void
2183Gicv3CPUInterface::virtualIncrementEOICount()
2184{
2185 // Increment the EOICOUNT field in ICH_HCR_EL2
2186 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2187 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2188 EOI_cout++;
2189 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2190 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2191}
2192
2193// spec section 4.6.2
2194ArmISA::InterruptTypes
2195Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2196{
2197 bool is_fiq = false;
2198
2199 switch (group) {
2200 case Gicv3::G0S:
2201 is_fiq = true;
2202 break;
2203
2204 case Gicv3::G1S:
2205 is_fiq = (distributor->DS == 0) &&
2206 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2207 break;
2208
2209 case Gicv3::G1NS:
2210 is_fiq = (distributor->DS == 0) && inSecureState();
2211 break;
2212
2213 default:
2214 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2215 }
2216
2217 if (is_fiq) {
2218 return ArmISA::INT_FIQ;
2219 } else {
2220 return ArmISA::INT_IRQ;
2221 }
2222}
2223
2224bool
2225Gicv3CPUInterface::hppiCanPreempt()
2226{
2227 if (hppi.prio == 0xff) {
2228 // there is no pending interrupt
2229 return false;
2230 }
2231
2232 if (!groupEnabled(hppi.group)) {
2233 // group disabled at CPU interface
2234 return false;
2235 }
2236
2237 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2238 // priority masked
2239 return false;
2240 }
2241
2242 uint8_t rprio = highestActivePriority();
2243
2244 if (rprio == 0xff) {
2245 return true;
2246 }
2247
2248 uint32_t prio_mask = groupPriorityMask(hppi.group);
2249
2250 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2251 return true;
2252 }
2253
2254 return false;
2255}
2256
2257uint8_t
2258Gicv3CPUInterface::highestActivePriority() const
2259{
2260 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2261 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2262 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2263
2264 if (apr) {
2265 return ctz32(apr) << (GIC_MIN_BPR + 1);
2266 }
2267
2268 // no active interrups, return idle priority
2269 return 0xff;
2270}
2271
2272bool
2273Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2274{
2275 switch (group) {
2276 case Gicv3::G0S: {
2277 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2278 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2279 return icc_igrpen0_el1.Enable;
2280 }
2281
2282 case Gicv3::G1S: {
2283 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2284 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2285 return icc_igrpen1_el1_s.Enable;
2286 }
2287
2288 case Gicv3::G1NS: {
2289 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2290 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2291 return icc_igrpen1_el1_ns.Enable;
2292 }
2293
2294 default:
2295 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2296 }
2297}
2298
2299bool
2300Gicv3CPUInterface::inSecureState() const
2301{
2302 if (!gic->getSystem()->haveSecurity()) {
2303 return false;
2304 }
2305
2306 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2307 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2308 return ArmISA::inSecureState(scr, cpsr);
2309}
2310
2311int
2312Gicv3CPUInterface::currEL() const
2313{
2314 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2315 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2316
2317 if (is_64) {
2318 return (ExceptionLevel)(uint8_t) cpsr.el;
2319 } else {
2320 switch (cpsr.mode) {
2321 case MODE_USER:
2322 return 0;
2323
2324 case MODE_HYP:
2325 return 2;
2326
2327 case MODE_MON:
2328 return 3;
2329
2330 default:
2331 return 1;
2332 }
2333 }
2334}
2335
2336bool
2337Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2338{
2339 switch (el) {
2340 case EL0:
2341 case EL1:
2342 return true;
2343
2344 case EL2:
2345 return gic->getSystem()->haveVirtualization();
2346
2347 case EL3:
2348 return gic->getSystem()->haveSecurity();
2349
2350 default:
2351 warn("Unimplemented Exception Level\n");
2352 return false;
2353 }
2354}
2355
2356bool
2357Gicv3CPUInterface::isSecureBelowEL3() const
2358{
2359 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2360 return haveEL(EL3) && scr.ns == 0;
2361}
2362
2363bool
2364Gicv3CPUInterface::isAA64() const
2365{
2366 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2367 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2368}
2369
2370bool
2371Gicv3CPUInterface::isEL3OrMon() const
2372{
2373 if (haveEL(EL3)) {
2374 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2375 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2376
2377 if (is_64 && (cpsr.el == EL3)) {
2378 return true;
2379 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2380 return true;
2381 }
2382 }
2383
2384 return false;
2385}
2386
2387// Computes ICH_EISR_EL2
2388uint64_t
2389Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2390{
2391 // ICH_EISR_EL2
2392 // Bits [63:16] - RES0
2393 // Status<n>, bit [n], for n = 0 to 15
2394 // EOI maintenance interrupt status bit for List register <n>:
2395 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2396 // maintenance interrupt.
2397 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2398 // interrupt that has not been handled.
2399 //
2400 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2401 // of the following are true:
2402 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2403 // - ICH_LR<n>_EL2.HW is 0.
2404 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2405
2406 uint64_t value = 0;
2407
2408 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2409 ICH_LR_EL2 ich_lr_el2 =
2410 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2411
2412 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2413 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2414 value |= (1 << lr_idx);
2415 }
2416 }
2417
2418 return value;
2419}
2420
2421Gicv3CPUInterface::ICH_MISR_EL2
2422Gicv3CPUInterface::maintenanceInterruptStatus() const
2423{
2424 // Comments are copied from SPEC section 9.4.7 (ID012119)
2425 ICH_MISR_EL2 ich_misr_el2 = 0;
2426 ICH_HCR_EL2 ich_hcr_el2 =
2427 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2428 ICH_VMCR_EL2 ich_vmcr_el2 =
2429 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2430
2431 // End Of Interrupt. [bit 0]
2432 // This maintenance interrupt is asserted when at least one bit in
2433 // ICH_EISR_EL2 is 1.
2434
2435 if (eoiMaintenanceInterruptStatus()) {
2436 ich_misr_el2.EOI = 1;
2437 }
2438
2439 // Underflow. [bit 1]
2440 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2441 // zero or one of the List register entries are marked as a valid
2442 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2443 // do not equal 0x0.
2444 uint32_t num_valid_interrupts = 0;
2445 uint32_t num_pending_interrupts = 0;
2446
2447 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2448 ICH_LR_EL2 ich_lr_el2 =
2449 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2450
2451 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2452 num_valid_interrupts++;
2453 }
2454
2455 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2456 num_pending_interrupts++;
2457 }
2458 }
2459
2460 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2461 ich_misr_el2.U = 1;
2462 }
2463
2464 // List Register Entry Not Present. [bit 2]
2465 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2466 // and ICH_HCR_EL2.EOIcount is non-zero.
2467 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2468 ich_misr_el2.LRENP = 1;
2469 }
2470
2471 // No Pending. [bit 3]
2472 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2473 // no List register is in pending state.
2474 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2475 ich_misr_el2.NP = 1;
2476 }
2477
2478 // vPE Group 0 Enabled. [bit 4]
2479 // This maintenance interrupt is asserted when
2480 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2481 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2482 ich_misr_el2.VGrp0E = 1;
2483 }
2484
2485 // vPE Group 0 Disabled. [bit 5]
2486 // This maintenance interrupt is asserted when
2487 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2488 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2489 ich_misr_el2.VGrp0D = 1;
2490 }
2491
2492 // vPE Group 1 Enabled. [bit 6]
2493 // This maintenance interrupt is asserted when
2494 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2495 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2496 ich_misr_el2.VGrp1E = 1;
2497 }
2498
2499 // vPE Group 1 Disabled. [bit 7]
2500 // This maintenance interrupt is asserted when
2501 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2502 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2503 ich_misr_el2.VGrp1D = 1;
2504 }
2505
2506 return ich_misr_el2;
2507}
2508
2509void
2510Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2511{
2512 SERIALIZE_SCALAR(hppi.intid);
2513 SERIALIZE_SCALAR(hppi.prio);
2514 SERIALIZE_ENUM(hppi.group);
2515}
2516
2517void
2518Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2519{
2520 UNSERIALIZE_SCALAR(hppi.intid);
2521 UNSERIALIZE_SCALAR(hppi.prio);
2522 UNSERIALIZE_ENUM(hppi.group);
2523}
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