1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
40 : BaseISADevice(),
41 gic(gic),
42 redistributor(nullptr),
43 distributor(nullptr),
44 cpuId(cpu_id)
45{
46}
47
48void
49Gicv3CPUInterface::init()
50{
51 redistributor = gic->getRedistributor(cpuId);
52 distributor = gic->getDistributor();
53}
54
55void
56Gicv3CPUInterface::initState()
57{
58 reset();
59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
67void
68Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
69{
70 maintenanceInterrupt = gic->params()->maint_int->get(tc);
71}
72
73bool
74Gicv3CPUInterface::getHCREL2FMO() const
75{
76 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
77
78 if (hcr.tge && hcr.e2h) {
79 return false;
80 } else if (hcr.tge) {
81 return true;
82 } else {
83 return hcr.fmo;
84 }
85}
86
87bool
88Gicv3CPUInterface::getHCREL2IMO() const
89{
90 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
91
92 if (hcr.tge && hcr.e2h) {
93 return false;
94 } else if (hcr.tge) {
95 return true;
96 } else {
97 return hcr.imo;
98 }
99}
100
101RegVal
102Gicv3CPUInterface::readMiscReg(int misc_reg)
103{
104 RegVal value = isa->readMiscRegNoEffect(misc_reg);
105 bool hcr_fmo = getHCREL2FMO();
106 bool hcr_imo = getHCREL2IMO();
107
108 switch (misc_reg) {
109 // Active Priorities Group 1 Registers
110 case MISCREG_ICC_AP1R0:
111 case MISCREG_ICC_AP1R0_EL1: {
112 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
113 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
114 }
115
116 break;
117 }
118
119 case MISCREG_ICC_AP1R1:
120 case MISCREG_ICC_AP1R1_EL1:
121
122 // only implemented if supporting 6 or more bits of priority
123 case MISCREG_ICC_AP1R2:
124 case MISCREG_ICC_AP1R2_EL1:
125
126 // only implemented if supporting 7 or more bits of priority
127 case MISCREG_ICC_AP1R3:
128 case MISCREG_ICC_AP1R3_EL1:
129 // only implemented if supporting 7 or more bits of priority
130 return 0;
131
132 // Active Priorities Group 0 Registers
133 case MISCREG_ICC_AP0R0:
134 case MISCREG_ICC_AP0R0_EL1: {
135 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
136 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
137 }
138
139 break;
140 }
141
142 case MISCREG_ICC_AP0R1:
143 case MISCREG_ICC_AP0R1_EL1:
144
145 // only implemented if supporting 6 or more bits of priority
146 case MISCREG_ICC_AP0R2:
147 case MISCREG_ICC_AP0R2_EL1:
148
149 // only implemented if supporting 7 or more bits of priority
150 case MISCREG_ICC_AP0R3:
151 case MISCREG_ICC_AP0R3_EL1:
152 // only implemented if supporting 7 or more bits of priority
153 return 0;
154
155 // Interrupt Group 0 Enable register EL1
156 case MISCREG_ICC_IGRPEN0:
157 case MISCREG_ICC_IGRPEN0_EL1: {
158 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
159 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
160 }
161
162 break;
163 }
164
165 // Interrupt Group 1 Enable register EL1
166 case MISCREG_ICC_IGRPEN1:
167 case MISCREG_ICC_IGRPEN1_EL1: {
168 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
169 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
170 }
171
172 break;
173 }
174
175 // Interrupt Group 1 Enable register EL3
176 case MISCREG_ICC_MGRPEN1:
177 case MISCREG_ICC_IGRPEN1_EL3:
178 break;
179
180 // Running Priority Register
181 case MISCREG_ICC_RPR:
182 case MISCREG_ICC_RPR_EL1: {
183 if ((currEL() == EL1) && !inSecureState() &&
184 (hcr_imo || hcr_fmo)) {
185 return readMiscReg(MISCREG_ICV_RPR_EL1);
186 }
187
188 uint8_t rprio = highestActivePriority();
189
190 if (haveEL(EL3) && !inSecureState() &&
191 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
192 // Spec section 4.8.1
193 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
194 if ((rprio & 0x80) == 0) {
195 // If the current priority mask value is in the range of
196 // 0x00-0x7F a read access returns the value 0x0
197 rprio = 0;
198 } else if (rprio != 0xff) {
199 // If the current priority mask value is in the range of
200 // 0x80-0xFF a read access returns the Non-secure read of
201 // the current value
202 rprio = (rprio << 1) & 0xff;
203 }
204 }
205
206 value = rprio;
207 break;
208 }
209
210 // Virtual Running Priority Register
211 case MISCREG_ICV_RPR_EL1: {
212 value = virtualHighestActivePriority();
213 break;
214 }
215
216 // Highest Priority Pending Interrupt Register 0
217 case MISCREG_ICC_HPPIR0:
218 case MISCREG_ICC_HPPIR0_EL1: {
219 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
220 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
221 }
222
223 value = getHPPIR0();
224 break;
225 }
226
227 // Virtual Highest Priority Pending Interrupt Register 0
228 case MISCREG_ICV_HPPIR0_EL1: {
229 value = Gicv3::INTID_SPURIOUS;
230 int lr_idx = getHPPVILR();
231
232 if (lr_idx >= 0) {
233 ICH_LR_EL2 ich_lr_el2 =
234 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
235 Gicv3::GroupId group =
236 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
237
238 if (group == Gicv3::G0S) {
239 value = ich_lr_el2.vINTID;
240 }
241 }
242
243 break;
244 }
245
246 // Highest Priority Pending Interrupt Register 1
247 case MISCREG_ICC_HPPIR1:
248 case MISCREG_ICC_HPPIR1_EL1: {
249 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
250 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
251 }
252
253 value = getHPPIR1();
254 break;
255 }
256
257 // Virtual Highest Priority Pending Interrupt Register 1
258 case MISCREG_ICV_HPPIR1_EL1: {
259 value = Gicv3::INTID_SPURIOUS;
260 int lr_idx = getHPPVILR();
261
262 if (lr_idx >= 0) {
263 ICH_LR_EL2 ich_lr_el2 =
264 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
265 Gicv3::GroupId group =
266 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
267
268 if (group == Gicv3::G1NS) {
269 value = ich_lr_el2.vINTID;
270 }
271 }
272
273 break;
274 }
275
276 // Binary Point Register 0
277 case MISCREG_ICC_BPR0:
278 case MISCREG_ICC_BPR0_EL1:
279 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
280 return readMiscReg(MISCREG_ICV_BPR0_EL1);
281 }
282
283 M5_FALLTHROUGH;
284
285 // Binary Point Register 1
286 case MISCREG_ICC_BPR1:
287 case MISCREG_ICC_BPR1_EL1: {
288 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
289 return readMiscReg(MISCREG_ICV_BPR1_EL1);
290 }
291
292 Gicv3::GroupId group =
293 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
294
295 if (group == Gicv3::G1S && !inSecureState()) {
296 group = Gicv3::G1NS;
297 }
298
299 ICC_CTLR_EL1 icc_ctlr_el1_s =
300 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
301
302 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
303 icc_ctlr_el1_s.CBPR) {
304 group = Gicv3::G0S;
305 }
306
307 bool sat_inc = false;
308
309 ICC_CTLR_EL1 icc_ctlr_el1_ns =
310 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
311
312 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
313 icc_ctlr_el1_ns.CBPR) {
314 // Reads return BPR0 + 1 saturated to 7, WI
315 group = Gicv3::G0S;
316 sat_inc = true;
317 }
318
319 uint8_t bpr;
320
321 if (group == Gicv3::G0S) {
322 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
323 } else {
324 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
325 }
326
327 if (sat_inc) {
328 bpr++;
329
330 if (bpr > 7) {
331 bpr = 7;
332 }
333 }
334
335 value = bpr;
336 break;
337 }
338
339 // Virtual Binary Point Register 1
340 case MISCREG_ICV_BPR0_EL1:
341 case MISCREG_ICV_BPR1_EL1: {
342 Gicv3::GroupId group =
343 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
344 ICH_VMCR_EL2 ich_vmcr_el2 =
345 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
346 bool sat_inc = false;
347
348 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
349 // bpr0 + 1 saturated to 7, WI
350 group = Gicv3::G0S;
351 sat_inc = true;
352 }
353
354 uint8_t vbpr;
355
356 if (group == Gicv3::G0S) {
357 vbpr = ich_vmcr_el2.VBPR0;
358 } else {
359 vbpr = ich_vmcr_el2.VBPR1;
360 }
361
362 if (sat_inc) {
363 vbpr++;
364
365 if (vbpr > 7) {
366 vbpr = 7;
367 }
368 }
369
370 value = vbpr;
371 break;
372 }
373
374 // Interrupt Priority Mask Register
375 case MISCREG_ICC_PMR:
376 case MISCREG_ICC_PMR_EL1:
377 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
378 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
379 }
380
381 if (haveEL(EL3) && !inSecureState() &&
382 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
383 // Spec section 4.8.1
384 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
385 if ((value & 0x80) == 0) {
386 // If the current priority mask value is in the range of
387 // 0x00-0x7F a read access returns the value 0x00.
388 value = 0;
389 } else if (value != 0xff) {
390 // If the current priority mask value is in the range of
391 // 0x80-0xFF a read access returns the Non-secure read of the
392 // current value.
393 value = (value << 1) & 0xff;
394 }
395 }
396
397 break;
398
399 // Interrupt Acknowledge Register 0
400 case MISCREG_ICC_IAR0:
401 case MISCREG_ICC_IAR0_EL1: {
402 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
403 return readMiscReg(MISCREG_ICV_IAR0_EL1);
404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
| 1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
40 : BaseISADevice(),
41 gic(gic),
42 redistributor(nullptr),
43 distributor(nullptr),
44 cpuId(cpu_id)
45{
46}
47
48void
49Gicv3CPUInterface::init()
50{
51 redistributor = gic->getRedistributor(cpuId);
52 distributor = gic->getDistributor();
53}
54
55void
56Gicv3CPUInterface::initState()
57{
58 reset();
59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
67void
68Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
69{
70 maintenanceInterrupt = gic->params()->maint_int->get(tc);
71}
72
73bool
74Gicv3CPUInterface::getHCREL2FMO() const
75{
76 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
77
78 if (hcr.tge && hcr.e2h) {
79 return false;
80 } else if (hcr.tge) {
81 return true;
82 } else {
83 return hcr.fmo;
84 }
85}
86
87bool
88Gicv3CPUInterface::getHCREL2IMO() const
89{
90 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
91
92 if (hcr.tge && hcr.e2h) {
93 return false;
94 } else if (hcr.tge) {
95 return true;
96 } else {
97 return hcr.imo;
98 }
99}
100
101RegVal
102Gicv3CPUInterface::readMiscReg(int misc_reg)
103{
104 RegVal value = isa->readMiscRegNoEffect(misc_reg);
105 bool hcr_fmo = getHCREL2FMO();
106 bool hcr_imo = getHCREL2IMO();
107
108 switch (misc_reg) {
109 // Active Priorities Group 1 Registers
110 case MISCREG_ICC_AP1R0:
111 case MISCREG_ICC_AP1R0_EL1: {
112 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
113 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
114 }
115
116 break;
117 }
118
119 case MISCREG_ICC_AP1R1:
120 case MISCREG_ICC_AP1R1_EL1:
121
122 // only implemented if supporting 6 or more bits of priority
123 case MISCREG_ICC_AP1R2:
124 case MISCREG_ICC_AP1R2_EL1:
125
126 // only implemented if supporting 7 or more bits of priority
127 case MISCREG_ICC_AP1R3:
128 case MISCREG_ICC_AP1R3_EL1:
129 // only implemented if supporting 7 or more bits of priority
130 return 0;
131
132 // Active Priorities Group 0 Registers
133 case MISCREG_ICC_AP0R0:
134 case MISCREG_ICC_AP0R0_EL1: {
135 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
136 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
137 }
138
139 break;
140 }
141
142 case MISCREG_ICC_AP0R1:
143 case MISCREG_ICC_AP0R1_EL1:
144
145 // only implemented if supporting 6 or more bits of priority
146 case MISCREG_ICC_AP0R2:
147 case MISCREG_ICC_AP0R2_EL1:
148
149 // only implemented if supporting 7 or more bits of priority
150 case MISCREG_ICC_AP0R3:
151 case MISCREG_ICC_AP0R3_EL1:
152 // only implemented if supporting 7 or more bits of priority
153 return 0;
154
155 // Interrupt Group 0 Enable register EL1
156 case MISCREG_ICC_IGRPEN0:
157 case MISCREG_ICC_IGRPEN0_EL1: {
158 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
159 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
160 }
161
162 break;
163 }
164
165 // Interrupt Group 1 Enable register EL1
166 case MISCREG_ICC_IGRPEN1:
167 case MISCREG_ICC_IGRPEN1_EL1: {
168 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
169 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
170 }
171
172 break;
173 }
174
175 // Interrupt Group 1 Enable register EL3
176 case MISCREG_ICC_MGRPEN1:
177 case MISCREG_ICC_IGRPEN1_EL3:
178 break;
179
180 // Running Priority Register
181 case MISCREG_ICC_RPR:
182 case MISCREG_ICC_RPR_EL1: {
183 if ((currEL() == EL1) && !inSecureState() &&
184 (hcr_imo || hcr_fmo)) {
185 return readMiscReg(MISCREG_ICV_RPR_EL1);
186 }
187
188 uint8_t rprio = highestActivePriority();
189
190 if (haveEL(EL3) && !inSecureState() &&
191 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
192 // Spec section 4.8.1
193 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
194 if ((rprio & 0x80) == 0) {
195 // If the current priority mask value is in the range of
196 // 0x00-0x7F a read access returns the value 0x0
197 rprio = 0;
198 } else if (rprio != 0xff) {
199 // If the current priority mask value is in the range of
200 // 0x80-0xFF a read access returns the Non-secure read of
201 // the current value
202 rprio = (rprio << 1) & 0xff;
203 }
204 }
205
206 value = rprio;
207 break;
208 }
209
210 // Virtual Running Priority Register
211 case MISCREG_ICV_RPR_EL1: {
212 value = virtualHighestActivePriority();
213 break;
214 }
215
216 // Highest Priority Pending Interrupt Register 0
217 case MISCREG_ICC_HPPIR0:
218 case MISCREG_ICC_HPPIR0_EL1: {
219 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
220 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
221 }
222
223 value = getHPPIR0();
224 break;
225 }
226
227 // Virtual Highest Priority Pending Interrupt Register 0
228 case MISCREG_ICV_HPPIR0_EL1: {
229 value = Gicv3::INTID_SPURIOUS;
230 int lr_idx = getHPPVILR();
231
232 if (lr_idx >= 0) {
233 ICH_LR_EL2 ich_lr_el2 =
234 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
235 Gicv3::GroupId group =
236 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
237
238 if (group == Gicv3::G0S) {
239 value = ich_lr_el2.vINTID;
240 }
241 }
242
243 break;
244 }
245
246 // Highest Priority Pending Interrupt Register 1
247 case MISCREG_ICC_HPPIR1:
248 case MISCREG_ICC_HPPIR1_EL1: {
249 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
250 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
251 }
252
253 value = getHPPIR1();
254 break;
255 }
256
257 // Virtual Highest Priority Pending Interrupt Register 1
258 case MISCREG_ICV_HPPIR1_EL1: {
259 value = Gicv3::INTID_SPURIOUS;
260 int lr_idx = getHPPVILR();
261
262 if (lr_idx >= 0) {
263 ICH_LR_EL2 ich_lr_el2 =
264 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
265 Gicv3::GroupId group =
266 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
267
268 if (group == Gicv3::G1NS) {
269 value = ich_lr_el2.vINTID;
270 }
271 }
272
273 break;
274 }
275
276 // Binary Point Register 0
277 case MISCREG_ICC_BPR0:
278 case MISCREG_ICC_BPR0_EL1:
279 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
280 return readMiscReg(MISCREG_ICV_BPR0_EL1);
281 }
282
283 M5_FALLTHROUGH;
284
285 // Binary Point Register 1
286 case MISCREG_ICC_BPR1:
287 case MISCREG_ICC_BPR1_EL1: {
288 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
289 return readMiscReg(MISCREG_ICV_BPR1_EL1);
290 }
291
292 Gicv3::GroupId group =
293 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
294
295 if (group == Gicv3::G1S && !inSecureState()) {
296 group = Gicv3::G1NS;
297 }
298
299 ICC_CTLR_EL1 icc_ctlr_el1_s =
300 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
301
302 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
303 icc_ctlr_el1_s.CBPR) {
304 group = Gicv3::G0S;
305 }
306
307 bool sat_inc = false;
308
309 ICC_CTLR_EL1 icc_ctlr_el1_ns =
310 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
311
312 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
313 icc_ctlr_el1_ns.CBPR) {
314 // Reads return BPR0 + 1 saturated to 7, WI
315 group = Gicv3::G0S;
316 sat_inc = true;
317 }
318
319 uint8_t bpr;
320
321 if (group == Gicv3::G0S) {
322 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
323 } else {
324 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
325 }
326
327 if (sat_inc) {
328 bpr++;
329
330 if (bpr > 7) {
331 bpr = 7;
332 }
333 }
334
335 value = bpr;
336 break;
337 }
338
339 // Virtual Binary Point Register 1
340 case MISCREG_ICV_BPR0_EL1:
341 case MISCREG_ICV_BPR1_EL1: {
342 Gicv3::GroupId group =
343 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
344 ICH_VMCR_EL2 ich_vmcr_el2 =
345 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
346 bool sat_inc = false;
347
348 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
349 // bpr0 + 1 saturated to 7, WI
350 group = Gicv3::G0S;
351 sat_inc = true;
352 }
353
354 uint8_t vbpr;
355
356 if (group == Gicv3::G0S) {
357 vbpr = ich_vmcr_el2.VBPR0;
358 } else {
359 vbpr = ich_vmcr_el2.VBPR1;
360 }
361
362 if (sat_inc) {
363 vbpr++;
364
365 if (vbpr > 7) {
366 vbpr = 7;
367 }
368 }
369
370 value = vbpr;
371 break;
372 }
373
374 // Interrupt Priority Mask Register
375 case MISCREG_ICC_PMR:
376 case MISCREG_ICC_PMR_EL1:
377 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
378 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
379 }
380
381 if (haveEL(EL3) && !inSecureState() &&
382 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
383 // Spec section 4.8.1
384 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
385 if ((value & 0x80) == 0) {
386 // If the current priority mask value is in the range of
387 // 0x00-0x7F a read access returns the value 0x00.
388 value = 0;
389 } else if (value != 0xff) {
390 // If the current priority mask value is in the range of
391 // 0x80-0xFF a read access returns the Non-secure read of the
392 // current value.
393 value = (value << 1) & 0xff;
394 }
395 }
396
397 break;
398
399 // Interrupt Acknowledge Register 0
400 case MISCREG_ICC_IAR0:
401 case MISCREG_ICC_IAR0_EL1: {
402 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
403 return readMiscReg(MISCREG_ICV_IAR0_EL1);
404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
|
412 if (int_id < Gicv3::INTID_SECURE) {
| 412 if (int_id < Gicv3::INTID_SECURE ||
413 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
|
413 activateIRQ(int_id, hppi.group);
414 }
415 } else {
416 int_id = Gicv3::INTID_SPURIOUS;
417 }
418
419 value = int_id;
420 break;
421 }
422
423 // Virtual Interrupt Acknowledge Register 0
424 case MISCREG_ICV_IAR0_EL1: {
425 int lr_idx = getHPPVILR();
426 uint32_t int_id = Gicv3::INTID_SPURIOUS;
427
428 if (lr_idx >= 0) {
429 ICH_LR_EL2 ich_lr_el2 =
430 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
431
432 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
433 int_id = ich_lr_el2.vINTID;
434
435 if (int_id < Gicv3::INTID_SECURE ||
436 int_id > Gicv3::INTID_SPURIOUS) {
437 virtualActivateIRQ(lr_idx);
438 } else {
439 // Bogus... Pseudocode says:
440 // - Move from pending to invalid...
441 // - Return de bogus id...
442 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
443 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
444 ich_lr_el2);
445 }
446 }
447 }
448
449 value = int_id;
450 virtualUpdate();
451 break;
452 }
453
454 // Interrupt Acknowledge Register 1
455 case MISCREG_ICC_IAR1:
456 case MISCREG_ICC_IAR1_EL1: {
457 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
458 return readMiscReg(MISCREG_ICV_IAR1_EL1);
459 }
460
461 uint32_t int_id;
462
463 if (hppiCanPreempt()) {
464 int_id = getHPPIR1();
465
466 // avoid activation for special interrupts
| 414 activateIRQ(int_id, hppi.group);
415 }
416 } else {
417 int_id = Gicv3::INTID_SPURIOUS;
418 }
419
420 value = int_id;
421 break;
422 }
423
424 // Virtual Interrupt Acknowledge Register 0
425 case MISCREG_ICV_IAR0_EL1: {
426 int lr_idx = getHPPVILR();
427 uint32_t int_id = Gicv3::INTID_SPURIOUS;
428
429 if (lr_idx >= 0) {
430 ICH_LR_EL2 ich_lr_el2 =
431 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
432
433 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
434 int_id = ich_lr_el2.vINTID;
435
436 if (int_id < Gicv3::INTID_SECURE ||
437 int_id > Gicv3::INTID_SPURIOUS) {
438 virtualActivateIRQ(lr_idx);
439 } else {
440 // Bogus... Pseudocode says:
441 // - Move from pending to invalid...
442 // - Return de bogus id...
443 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
444 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
445 ich_lr_el2);
446 }
447 }
448 }
449
450 value = int_id;
451 virtualUpdate();
452 break;
453 }
454
455 // Interrupt Acknowledge Register 1
456 case MISCREG_ICC_IAR1:
457 case MISCREG_ICC_IAR1_EL1: {
458 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
459 return readMiscReg(MISCREG_ICV_IAR1_EL1);
460 }
461
462 uint32_t int_id;
463
464 if (hppiCanPreempt()) {
465 int_id = getHPPIR1();
466
467 // avoid activation for special interrupts
|
467 if (int_id < Gicv3::INTID_SECURE) {
| 468 if (int_id < Gicv3::INTID_SECURE ||
469 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
|
468 activateIRQ(int_id, hppi.group);
469 }
470 } else {
471 int_id = Gicv3::INTID_SPURIOUS;
472 }
473
474 value = int_id;
475 break;
476 }
477
478 // Virtual Interrupt Acknowledge Register 1
479 case MISCREG_ICV_IAR1_EL1: {
480 int lr_idx = getHPPVILR();
481 uint32_t int_id = Gicv3::INTID_SPURIOUS;
482
483 if (lr_idx >= 0) {
484 ICH_LR_EL2 ich_lr_el2 =
485 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
486
487 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
488 int_id = ich_lr_el2.vINTID;
489
490 if (int_id < Gicv3::INTID_SECURE ||
491 int_id > Gicv3::INTID_SPURIOUS) {
492 virtualActivateIRQ(lr_idx);
493 } else {
494 // Bogus... Pseudocode says:
495 // - Move from pending to invalid...
496 // - Return de bogus id...
497 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
498 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
499 ich_lr_el2);
500 }
501 }
502 }
503
504 value = int_id;
505 virtualUpdate();
506 break;
507 }
508
509 // System Register Enable Register EL1
510 case MISCREG_ICC_SRE:
511 case MISCREG_ICC_SRE_EL1: {
512 /*
513 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
514 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
515 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
516 */
517 ICC_SRE_EL1 icc_sre_el1 = 0;
518 icc_sre_el1.SRE = 1;
519 icc_sre_el1.DIB = 1;
520 icc_sre_el1.DFB = 1;
521 value = icc_sre_el1;
522 break;
523 }
524
525 // System Register Enable Register EL2
526 case MISCREG_ICC_HSRE:
527 case MISCREG_ICC_SRE_EL2: {
528 /*
529 * Enable [3] == 1
530 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
531 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
532 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
533 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
534 */
535 ICC_SRE_EL2 icc_sre_el2 = 0;
536 icc_sre_el2.SRE = 1;
537 icc_sre_el2.DIB = 1;
538 icc_sre_el2.DFB = 1;
539 icc_sre_el2.Enable = 1;
540 value = icc_sre_el2;
541 break;
542 }
543
544 // System Register Enable Register EL3
545 case MISCREG_ICC_MSRE:
546 case MISCREG_ICC_SRE_EL3: {
547 /*
548 * Enable [3] == 1
549 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
550 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
551 * RAO/WI)
552 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
553 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
554 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
555 */
556 ICC_SRE_EL3 icc_sre_el3 = 0;
557 icc_sre_el3.SRE = 1;
558 icc_sre_el3.DIB = 1;
559 icc_sre_el3.DFB = 1;
560 icc_sre_el3.Enable = 1;
561 value = icc_sre_el3;
562 break;
563 }
564
565 // Control Register
566 case MISCREG_ICC_CTLR:
567 case MISCREG_ICC_CTLR_EL1: {
568 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
569 return readMiscReg(MISCREG_ICV_CTLR_EL1);
570 }
571
572 // Enforce value for RO bits
573 // ExtRange [19], INTIDs in the range 1024..8191 not supported
574 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
575 // A3V [15], supports non-zero values of the Aff3 field in SGI
576 // generation System registers
577 // SEIS [14], does not support generation of SEIs (deprecated)
578 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
579 // PRIbits [10:8], number of priority bits implemented, minus one
580 ICC_CTLR_EL1 icc_ctlr_el1 = value;
581 icc_ctlr_el1.ExtRange = 0;
582 icc_ctlr_el1.RSS = 1;
583 icc_ctlr_el1.A3V = 1;
584 icc_ctlr_el1.SEIS = 0;
585 icc_ctlr_el1.IDbits = 1;
586 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
587 value = icc_ctlr_el1;
588 break;
589 }
590
591 // Virtual Control Register
592 case MISCREG_ICV_CTLR_EL1: {
593 ICV_CTLR_EL1 icv_ctlr_el1 = value;
594 icv_ctlr_el1.RSS = 0;
595 icv_ctlr_el1.A3V = 1;
596 icv_ctlr_el1.SEIS = 0;
597 icv_ctlr_el1.IDbits = 1;
598 icv_ctlr_el1.PRIbits = 7;
599 value = icv_ctlr_el1;
600 break;
601 }
602
603 // Control Register
604 case MISCREG_ICC_MCTLR:
605 case MISCREG_ICC_CTLR_EL3: {
606 // Enforce value for RO bits
607 // ExtRange [19], INTIDs in the range 1024..8191 not supported
608 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
609 // nDS [17], supports disabling of security
610 // A3V [15], supports non-zero values of the Aff3 field in SGI
611 // generation System registers
612 // SEIS [14], does not support generation of SEIs (deprecated)
613 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
614 // PRIbits [10:8], number of priority bits implemented, minus one
615 ICC_CTLR_EL3 icc_ctlr_el3 = value;
616 icc_ctlr_el3.ExtRange = 0;
617 icc_ctlr_el3.RSS = 1;
618 icc_ctlr_el3.nDS = 0;
619 icc_ctlr_el3.A3V = 1;
620 icc_ctlr_el3.SEIS = 0;
621 icc_ctlr_el3.IDbits = 0;
622 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
623 value = icc_ctlr_el3;
624 break;
625 }
626
627 // Hyp Control Register
628 case MISCREG_ICH_HCR:
629 case MISCREG_ICH_HCR_EL2:
630 break;
631
632 // Hyp Active Priorities Group 0 Registers
633 case MISCREG_ICH_AP0R0:
634 case MISCREG_ICH_AP0R0_EL2:
635 break;
636
637 // Hyp Active Priorities Group 1 Registers
638 case MISCREG_ICH_AP1R0:
639 case MISCREG_ICH_AP1R0_EL2:
640 break;
641
642 // Maintenance Interrupt State Register
643 case MISCREG_ICH_MISR:
644 case MISCREG_ICH_MISR_EL2:
645 value = maintenanceInterruptStatus();
646 break;
647
648 // VGIC Type Register
649 case MISCREG_ICH_VTR:
650 case MISCREG_ICH_VTR_EL2: {
651 ICH_VTR_EL2 ich_vtr_el2 = value;
652
653 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
654 ich_vtr_el2.A3V = 1;
655 ich_vtr_el2.IDbits = 1;
656 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
657 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
658
659 value = ich_vtr_el2;
660 break;
661 }
662
663 // End of Interrupt Status Register
664 case MISCREG_ICH_EISR:
665 case MISCREG_ICH_EISR_EL2:
666 value = eoiMaintenanceInterruptStatus();
667 break;
668
669 // Empty List Register Status Register
670 case MISCREG_ICH_ELRSR:
671 case MISCREG_ICH_ELRSR_EL2:
672 value = 0;
673
674 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
675 ICH_LR_EL2 ich_lr_el2 =
676 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
677
678 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
679 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
680 value |= (1 << lr_idx);
681 }
682 }
683
684 break;
685
686 // List Registers
687 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
688 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
689 value = value >> 32;
690 break;
691
692 // List Registers
693 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
694 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
695 value = value & 0xffffffff;
696 break;
697
698 // List Registers
699 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
700 break;
701
702 // Virtual Machine Control Register
703 case MISCREG_ICH_VMCR:
704 case MISCREG_ICH_VMCR_EL2:
705 break;
706
707 default:
708 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
709 misc_reg, miscRegName[misc_reg]);
710 }
711
712 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
713 miscRegName[misc_reg], value);
714 return value;
715}
716
717void
718Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
719{
720 bool do_virtual_update = false;
721 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
722 miscRegName[misc_reg], val);
723 bool hcr_fmo = getHCREL2FMO();
724 bool hcr_imo = getHCREL2IMO();
725
726 switch (misc_reg) {
727 // Active Priorities Group 1 Registers
728 case MISCREG_ICC_AP1R0:
729 case MISCREG_ICC_AP1R0_EL1:
730 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
731 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
732 }
733
734 break;
735
736 case MISCREG_ICC_AP1R1:
737 case MISCREG_ICC_AP1R1_EL1:
738
739 // only implemented if supporting 6 or more bits of priority
740 case MISCREG_ICC_AP1R2:
741 case MISCREG_ICC_AP1R2_EL1:
742
743 // only implemented if supporting 7 or more bits of priority
744 case MISCREG_ICC_AP1R3:
745 case MISCREG_ICC_AP1R3_EL1:
746 // only implemented if supporting 7 or more bits of priority
747 break;
748
749 // Active Priorities Group 0 Registers
750 case MISCREG_ICC_AP0R0:
751 case MISCREG_ICC_AP0R0_EL1:
752 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
753 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
754 }
755
756 break;
757
758 case MISCREG_ICC_AP0R1:
759 case MISCREG_ICC_AP0R1_EL1:
760
761 // only implemented if supporting 6 or more bits of priority
762 case MISCREG_ICC_AP0R2:
763 case MISCREG_ICC_AP0R2_EL1:
764
765 // only implemented if supporting 7 or more bits of priority
766 case MISCREG_ICC_AP0R3:
767 case MISCREG_ICC_AP0R3_EL1:
768 // only implemented if supporting 7 or more bits of priority
769 break;
770
771 // End Of Interrupt Register 0
772 case MISCREG_ICC_EOIR0:
773 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
774 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
775 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
776 }
777
778 int int_id = val & 0xffffff;
779
780 // avoid activation for special interrupts
| 470 activateIRQ(int_id, hppi.group);
471 }
472 } else {
473 int_id = Gicv3::INTID_SPURIOUS;
474 }
475
476 value = int_id;
477 break;
478 }
479
480 // Virtual Interrupt Acknowledge Register 1
481 case MISCREG_ICV_IAR1_EL1: {
482 int lr_idx = getHPPVILR();
483 uint32_t int_id = Gicv3::INTID_SPURIOUS;
484
485 if (lr_idx >= 0) {
486 ICH_LR_EL2 ich_lr_el2 =
487 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
488
489 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
490 int_id = ich_lr_el2.vINTID;
491
492 if (int_id < Gicv3::INTID_SECURE ||
493 int_id > Gicv3::INTID_SPURIOUS) {
494 virtualActivateIRQ(lr_idx);
495 } else {
496 // Bogus... Pseudocode says:
497 // - Move from pending to invalid...
498 // - Return de bogus id...
499 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
500 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
501 ich_lr_el2);
502 }
503 }
504 }
505
506 value = int_id;
507 virtualUpdate();
508 break;
509 }
510
511 // System Register Enable Register EL1
512 case MISCREG_ICC_SRE:
513 case MISCREG_ICC_SRE_EL1: {
514 /*
515 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
516 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
517 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
518 */
519 ICC_SRE_EL1 icc_sre_el1 = 0;
520 icc_sre_el1.SRE = 1;
521 icc_sre_el1.DIB = 1;
522 icc_sre_el1.DFB = 1;
523 value = icc_sre_el1;
524 break;
525 }
526
527 // System Register Enable Register EL2
528 case MISCREG_ICC_HSRE:
529 case MISCREG_ICC_SRE_EL2: {
530 /*
531 * Enable [3] == 1
532 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
533 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
534 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
535 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
536 */
537 ICC_SRE_EL2 icc_sre_el2 = 0;
538 icc_sre_el2.SRE = 1;
539 icc_sre_el2.DIB = 1;
540 icc_sre_el2.DFB = 1;
541 icc_sre_el2.Enable = 1;
542 value = icc_sre_el2;
543 break;
544 }
545
546 // System Register Enable Register EL3
547 case MISCREG_ICC_MSRE:
548 case MISCREG_ICC_SRE_EL3: {
549 /*
550 * Enable [3] == 1
551 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
552 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
553 * RAO/WI)
554 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
555 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
556 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
557 */
558 ICC_SRE_EL3 icc_sre_el3 = 0;
559 icc_sre_el3.SRE = 1;
560 icc_sre_el3.DIB = 1;
561 icc_sre_el3.DFB = 1;
562 icc_sre_el3.Enable = 1;
563 value = icc_sre_el3;
564 break;
565 }
566
567 // Control Register
568 case MISCREG_ICC_CTLR:
569 case MISCREG_ICC_CTLR_EL1: {
570 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
571 return readMiscReg(MISCREG_ICV_CTLR_EL1);
572 }
573
574 // Enforce value for RO bits
575 // ExtRange [19], INTIDs in the range 1024..8191 not supported
576 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
577 // A3V [15], supports non-zero values of the Aff3 field in SGI
578 // generation System registers
579 // SEIS [14], does not support generation of SEIs (deprecated)
580 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
581 // PRIbits [10:8], number of priority bits implemented, minus one
582 ICC_CTLR_EL1 icc_ctlr_el1 = value;
583 icc_ctlr_el1.ExtRange = 0;
584 icc_ctlr_el1.RSS = 1;
585 icc_ctlr_el1.A3V = 1;
586 icc_ctlr_el1.SEIS = 0;
587 icc_ctlr_el1.IDbits = 1;
588 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
589 value = icc_ctlr_el1;
590 break;
591 }
592
593 // Virtual Control Register
594 case MISCREG_ICV_CTLR_EL1: {
595 ICV_CTLR_EL1 icv_ctlr_el1 = value;
596 icv_ctlr_el1.RSS = 0;
597 icv_ctlr_el1.A3V = 1;
598 icv_ctlr_el1.SEIS = 0;
599 icv_ctlr_el1.IDbits = 1;
600 icv_ctlr_el1.PRIbits = 7;
601 value = icv_ctlr_el1;
602 break;
603 }
604
605 // Control Register
606 case MISCREG_ICC_MCTLR:
607 case MISCREG_ICC_CTLR_EL3: {
608 // Enforce value for RO bits
609 // ExtRange [19], INTIDs in the range 1024..8191 not supported
610 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
611 // nDS [17], supports disabling of security
612 // A3V [15], supports non-zero values of the Aff3 field in SGI
613 // generation System registers
614 // SEIS [14], does not support generation of SEIs (deprecated)
615 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
616 // PRIbits [10:8], number of priority bits implemented, minus one
617 ICC_CTLR_EL3 icc_ctlr_el3 = value;
618 icc_ctlr_el3.ExtRange = 0;
619 icc_ctlr_el3.RSS = 1;
620 icc_ctlr_el3.nDS = 0;
621 icc_ctlr_el3.A3V = 1;
622 icc_ctlr_el3.SEIS = 0;
623 icc_ctlr_el3.IDbits = 0;
624 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
625 value = icc_ctlr_el3;
626 break;
627 }
628
629 // Hyp Control Register
630 case MISCREG_ICH_HCR:
631 case MISCREG_ICH_HCR_EL2:
632 break;
633
634 // Hyp Active Priorities Group 0 Registers
635 case MISCREG_ICH_AP0R0:
636 case MISCREG_ICH_AP0R0_EL2:
637 break;
638
639 // Hyp Active Priorities Group 1 Registers
640 case MISCREG_ICH_AP1R0:
641 case MISCREG_ICH_AP1R0_EL2:
642 break;
643
644 // Maintenance Interrupt State Register
645 case MISCREG_ICH_MISR:
646 case MISCREG_ICH_MISR_EL2:
647 value = maintenanceInterruptStatus();
648 break;
649
650 // VGIC Type Register
651 case MISCREG_ICH_VTR:
652 case MISCREG_ICH_VTR_EL2: {
653 ICH_VTR_EL2 ich_vtr_el2 = value;
654
655 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
656 ich_vtr_el2.A3V = 1;
657 ich_vtr_el2.IDbits = 1;
658 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
659 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
660
661 value = ich_vtr_el2;
662 break;
663 }
664
665 // End of Interrupt Status Register
666 case MISCREG_ICH_EISR:
667 case MISCREG_ICH_EISR_EL2:
668 value = eoiMaintenanceInterruptStatus();
669 break;
670
671 // Empty List Register Status Register
672 case MISCREG_ICH_ELRSR:
673 case MISCREG_ICH_ELRSR_EL2:
674 value = 0;
675
676 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
677 ICH_LR_EL2 ich_lr_el2 =
678 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
679
680 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
681 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
682 value |= (1 << lr_idx);
683 }
684 }
685
686 break;
687
688 // List Registers
689 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
690 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
691 value = value >> 32;
692 break;
693
694 // List Registers
695 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
696 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
697 value = value & 0xffffffff;
698 break;
699
700 // List Registers
701 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
702 break;
703
704 // Virtual Machine Control Register
705 case MISCREG_ICH_VMCR:
706 case MISCREG_ICH_VMCR_EL2:
707 break;
708
709 default:
710 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
711 misc_reg, miscRegName[misc_reg]);
712 }
713
714 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
715 miscRegName[misc_reg], value);
716 return value;
717}
718
719void
720Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
721{
722 bool do_virtual_update = false;
723 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
724 miscRegName[misc_reg], val);
725 bool hcr_fmo = getHCREL2FMO();
726 bool hcr_imo = getHCREL2IMO();
727
728 switch (misc_reg) {
729 // Active Priorities Group 1 Registers
730 case MISCREG_ICC_AP1R0:
731 case MISCREG_ICC_AP1R0_EL1:
732 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
733 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
734 }
735
736 break;
737
738 case MISCREG_ICC_AP1R1:
739 case MISCREG_ICC_AP1R1_EL1:
740
741 // only implemented if supporting 6 or more bits of priority
742 case MISCREG_ICC_AP1R2:
743 case MISCREG_ICC_AP1R2_EL1:
744
745 // only implemented if supporting 7 or more bits of priority
746 case MISCREG_ICC_AP1R3:
747 case MISCREG_ICC_AP1R3_EL1:
748 // only implemented if supporting 7 or more bits of priority
749 break;
750
751 // Active Priorities Group 0 Registers
752 case MISCREG_ICC_AP0R0:
753 case MISCREG_ICC_AP0R0_EL1:
754 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
755 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
756 }
757
758 break;
759
760 case MISCREG_ICC_AP0R1:
761 case MISCREG_ICC_AP0R1_EL1:
762
763 // only implemented if supporting 6 or more bits of priority
764 case MISCREG_ICC_AP0R2:
765 case MISCREG_ICC_AP0R2_EL1:
766
767 // only implemented if supporting 7 or more bits of priority
768 case MISCREG_ICC_AP0R3:
769 case MISCREG_ICC_AP0R3_EL1:
770 // only implemented if supporting 7 or more bits of priority
771 break;
772
773 // End Of Interrupt Register 0
774 case MISCREG_ICC_EOIR0:
775 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
776 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
777 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
778 }
779
780 int int_id = val & 0xffffff;
781
782 // avoid activation for special interrupts
|
781 if (int_id >= Gicv3::INTID_SECURE) {
| 783 if (int_id >= Gicv3::INTID_SECURE &&
784 int_id <= Gicv3::INTID_SPURIOUS) {
|
782 return;
783 }
784
785 Gicv3::GroupId group = Gicv3::G0S;
786
787 if (highestActiveGroup() != group) {
788 return;
789 }
790
791 dropPriority(group);
792
793 if (!isEOISplitMode()) {
794 deactivateIRQ(int_id, group);
795 }
796
797 break;
798 }
799
800 // Virtual End Of Interrupt Register 0
801 case MISCREG_ICV_EOIR0_EL1: {
802 int int_id = val & 0xffffff;
803
804 // avoid deactivation for special interrupts
805 if (int_id >= Gicv3::INTID_SECURE &&
806 int_id <= Gicv3::INTID_SPURIOUS) {
807 return;
808 }
809
810 uint8_t drop_prio = virtualDropPriority();
811
812 if (drop_prio == 0xff) {
813 return;
814 }
815
816 int lr_idx = virtualFindActive(int_id);
817
818 if (lr_idx < 0) {
819 // No LR found matching
820 virtualIncrementEOICount();
821 } else {
822 ICH_LR_EL2 ich_lr_el2 =
823 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
824 Gicv3::GroupId lr_group =
825 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
826 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
827
828 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
829 //if (!virtualIsEOISplitMode())
830 {
831 virtualDeactivateIRQ(lr_idx);
832 }
833 }
834 }
835
836 virtualUpdate();
837 break;
838 }
839
840 // End Of Interrupt Register 1
841 case MISCREG_ICC_EOIR1:
842 case MISCREG_ICC_EOIR1_EL1: {
843 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
844 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
845 }
846
847 int int_id = val & 0xffffff;
848
849 // avoid deactivation for special interrupts
| 785 return;
786 }
787
788 Gicv3::GroupId group = Gicv3::G0S;
789
790 if (highestActiveGroup() != group) {
791 return;
792 }
793
794 dropPriority(group);
795
796 if (!isEOISplitMode()) {
797 deactivateIRQ(int_id, group);
798 }
799
800 break;
801 }
802
803 // Virtual End Of Interrupt Register 0
804 case MISCREG_ICV_EOIR0_EL1: {
805 int int_id = val & 0xffffff;
806
807 // avoid deactivation for special interrupts
808 if (int_id >= Gicv3::INTID_SECURE &&
809 int_id <= Gicv3::INTID_SPURIOUS) {
810 return;
811 }
812
813 uint8_t drop_prio = virtualDropPriority();
814
815 if (drop_prio == 0xff) {
816 return;
817 }
818
819 int lr_idx = virtualFindActive(int_id);
820
821 if (lr_idx < 0) {
822 // No LR found matching
823 virtualIncrementEOICount();
824 } else {
825 ICH_LR_EL2 ich_lr_el2 =
826 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
827 Gicv3::GroupId lr_group =
828 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
829 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
830
831 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
832 //if (!virtualIsEOISplitMode())
833 {
834 virtualDeactivateIRQ(lr_idx);
835 }
836 }
837 }
838
839 virtualUpdate();
840 break;
841 }
842
843 // End Of Interrupt Register 1
844 case MISCREG_ICC_EOIR1:
845 case MISCREG_ICC_EOIR1_EL1: {
846 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
847 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
848 }
849
850 int int_id = val & 0xffffff;
851
852 // avoid deactivation for special interrupts
|
850 if (int_id >= Gicv3::INTID_SECURE) {
| 853 if (int_id >= Gicv3::INTID_SECURE &&
854 int_id <= Gicv3::INTID_SPURIOUS) {
|
851 return;
852 }
853
854 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
855
856 if (highestActiveGroup() == Gicv3::G0S) {
857 return;
858 }
859
860 if (distributor->DS == 0) {
861 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
862 return;
863 } else if (highestActiveGroup() == Gicv3::G1NS &&
864 !(!inSecureState() or (currEL() == EL3))) {
865 return;
866 }
867 }
868
869 dropPriority(group);
870
871 if (!isEOISplitMode()) {
872 deactivateIRQ(int_id, group);
873 }
874
875 break;
876 }
877
878 // Virtual End Of Interrupt Register 1
879 case MISCREG_ICV_EOIR1_EL1: {
880 int int_id = val & 0xffffff;
881
882 // avoid deactivation for special interrupts
883 if (int_id >= Gicv3::INTID_SECURE &&
884 int_id <= Gicv3::INTID_SPURIOUS) {
885 return;
886 }
887
888 uint8_t drop_prio = virtualDropPriority();
889
890 if (drop_prio == 0xff) {
891 return;
892 }
893
894 int lr_idx = virtualFindActive(int_id);
895
896 if (lr_idx < 0) {
897 // No matching LR found
898 virtualIncrementEOICount();
899 } else {
900 ICH_LR_EL2 ich_lr_el2 =
901 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
902 Gicv3::GroupId lr_group =
903 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
904 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
905
906 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
907 if (!virtualIsEOISplitMode()) {
908 virtualDeactivateIRQ(lr_idx);
909 }
910 }
911 }
912
913 virtualUpdate();
914 break;
915 }
916
917 // Deactivate Interrupt Register
918 case MISCREG_ICC_DIR:
919 case MISCREG_ICC_DIR_EL1: {
920 if ((currEL() == EL1) && !inSecureState() &&
921 (hcr_imo || hcr_fmo)) {
922 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
923 }
924
925 int int_id = val & 0xffffff;
926
927 // The following checks are as per spec pseudocode
928 // aarch64/support/ICC_DIR_EL1
929
930 // Check for spurious ID
931 if (int_id >= Gicv3::INTID_SECURE) {
932 return;
933 }
934
935 // EOI mode is not set, so don't deactivate
936 if (!isEOISplitMode()) {
937 return;
938 }
939
940 Gicv3::GroupId group =
941 int_id >= 32 ? distributor->getIntGroup(int_id) :
942 redistributor->getIntGroup(int_id);
943 bool irq_is_grp0 = group == Gicv3::G0S;
944 bool single_sec_state = distributor->DS;
945 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
946 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
947 bool route_fiq_to_el3 = scr_el3.fiq;
948 bool route_irq_to_el3 = scr_el3.irq;
949 bool route_fiq_to_el2 = hcr_fmo;
950 bool route_irq_to_el2 = hcr_imo;
951
952 switch (currEL()) {
953 case EL3:
954 break;
955
956 case EL2:
957 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
958 break;
959 }
960
961 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
962 break;
963 }
964
965 return;
966
967 case EL1:
968 if (!isSecureBelowEL3()) {
969 if (single_sec_state && irq_is_grp0 &&
970 !route_fiq_to_el3 && !route_fiq_to_el2) {
971 break;
972 }
973
974 if (!irq_is_secure && !irq_is_grp0 &&
975 !route_irq_to_el3 && !route_irq_to_el2) {
976 break;
977 }
978 } else {
979 if (irq_is_grp0 && !route_fiq_to_el3) {
980 break;
981 }
982
983 if (!irq_is_grp0 &&
984 (!irq_is_secure || !single_sec_state) &&
985 !route_irq_to_el3) {
986 break;
987 }
988 }
989
990 return;
991
992 default:
993 break;
994 }
995
996 deactivateIRQ(int_id, group);
997 break;
998 }
999
1000 // Deactivate Virtual Interrupt Register
1001 case MISCREG_ICV_DIR_EL1: {
1002 int int_id = val & 0xffffff;
1003
1004 // avoid deactivation for special interrupts
1005 if (int_id >= Gicv3::INTID_SECURE &&
1006 int_id <= Gicv3::INTID_SPURIOUS) {
1007 return;
1008 }
1009
1010 if (!virtualIsEOISplitMode()) {
1011 return;
1012 }
1013
1014 int lr_idx = virtualFindActive(int_id);
1015
1016 if (lr_idx < 0) {
1017 // No matching LR found
1018 virtualIncrementEOICount();
1019 } else {
1020 virtualDeactivateIRQ(lr_idx);
1021 }
1022
1023 virtualUpdate();
1024 break;
1025 }
1026
1027 // Binary Point Register 0
1028 case MISCREG_ICC_BPR0:
1029 case MISCREG_ICC_BPR0_EL1:
1030 // Binary Point Register 1
1031 case MISCREG_ICC_BPR1:
1032 case MISCREG_ICC_BPR1_EL1: {
1033 if ((currEL() == EL1) && !inSecureState()) {
1034 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1035 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1036 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1037 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1038 }
1039 }
1040
1041 Gicv3::GroupId group =
1042 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1043
1044 if (group == Gicv3::G1S && !inSecureState()) {
1045 group = Gicv3::G1NS;
1046 }
1047
1048 ICC_CTLR_EL1 icc_ctlr_el1_s =
1049 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1050
1051 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1052 icc_ctlr_el1_s.CBPR) {
1053 group = Gicv3::G0S;
1054 }
1055
1056 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1057 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1058
1059 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1060 icc_ctlr_el1_ns.CBPR) {
1061 // BPR0 + 1 saturated to 7, WI
1062 return;
1063 }
1064
1065 uint8_t min_val = (group == Gicv3::G1NS) ?
1066 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1067 val &= 0x7;
1068
1069 if (val < min_val) {
1070 val = min_val;
1071 }
1072
1073 break;
1074 }
1075
1076 // Virtual Binary Point Register 0
1077 case MISCREG_ICV_BPR0_EL1:
1078 // Virtual Binary Point Register 1
1079 case MISCREG_ICV_BPR1_EL1: {
1080 Gicv3::GroupId group =
1081 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1082 ICH_VMCR_EL2 ich_vmcr_el2 =
1083 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1084
1085 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1086 // BPR0 + 1 saturated to 7, WI
1087 return;
1088 }
1089
1090 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1091
1092 if (group != Gicv3::G0S) {
1093 min_VPBR++;
1094 }
1095
1096 if (val < min_VPBR) {
1097 val = min_VPBR;
1098 }
1099
1100 if (group == Gicv3::G0S) {
1101 ich_vmcr_el2.VBPR0 = val;
1102 } else {
1103 ich_vmcr_el2.VBPR1 = val;
1104 }
1105
1106 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1107 do_virtual_update = true;
1108 break;
1109 }
1110
1111 // Control Register EL1
1112 case MISCREG_ICC_CTLR:
1113 case MISCREG_ICC_CTLR_EL1: {
1114 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1115 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1116 }
1117
1118 /*
1119 * ExtRange is RO.
1120 * RSS is RO.
1121 * A3V is RO.
1122 * SEIS is RO.
1123 * IDbits is RO.
1124 * PRIbits is RO.
1125 */
1126 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1127 ICC_CTLR_EL1 icc_ctlr_el1 =
1128 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1129
1130 ICC_CTLR_EL3 icc_ctlr_el3 =
1131 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1132
1133 // The following could be refactored but it is following
1134 // spec description section 9.2.6 point by point.
1135
1136 // PMHE
1137 if (haveEL(EL3)) {
1138 // PMHE is alias of ICC_CTLR_EL3.PMHE
1139
1140 if (distributor->DS == 0) {
1141 // PMHE is RO
1142 } else if (distributor->DS == 1) {
1143 // PMHE is RW
1144 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1145 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1146 }
1147 } else {
1148 // PMHE is RW (by implementation choice)
1149 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1150 }
1151
1152 // EOImode
1153 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1154
1155 if (inSecureState()) {
1156 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1157 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1158 } else {
1159 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1160 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1161 }
1162
1163 // CBPR
1164 if (haveEL(EL3)) {
1165 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1166
1167 if (distributor->DS == 0) {
1168 // CBPR is RO
1169 } else {
1170 // CBPR is RW
1171 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1172
1173 if (inSecureState()) {
1174 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1175 } else {
1176 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1177 }
1178 }
1179 } else {
1180 // CBPR is RW
1181 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1182 }
1183
1184 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1185
1186 val = icc_ctlr_el1;
1187 break;
1188 }
1189
1190 // Virtual Control Register
1191 case MISCREG_ICV_CTLR_EL1: {
1192 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1193 ICV_CTLR_EL1 icv_ctlr_el1 =
1194 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1195 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1196 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1197 val = icv_ctlr_el1;
1198
1199 // Aliases
1200 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1201 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1202 ICH_VMCR_EL2 ich_vmcr_el2 =
1203 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1204 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1205 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1206 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1207 break;
1208 }
1209
1210 // Control Register EL3
1211 case MISCREG_ICC_MCTLR:
1212 case MISCREG_ICC_CTLR_EL3: {
1213 /*
1214 * ExtRange is RO.
1215 * RSS is RO.
1216 * nDS is RO.
1217 * A3V is RO.
1218 * SEIS is RO.
1219 * IDbits is RO.
1220 * PRIbits is RO.
1221 * PMHE is RAO/WI, priority-based routing is always used.
1222 */
1223 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1224
1225 // Aliases
1226 if (haveEL(EL3))
1227 {
1228 ICC_CTLR_EL1 icc_ctlr_el1_s =
1229 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1230 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1231 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1232
1233 // ICC_CTLR_EL1(NS).EOImode is an alias of
1234 // ICC_CTLR_EL3.EOImode_EL1NS
1235 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1236 // ICC_CTLR_EL1(S).EOImode is an alias of
1237 // ICC_CTLR_EL3.EOImode_EL1S
1238 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1239 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1240 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1241 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1242 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1243
1244 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1245 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1246 icc_ctlr_el1_ns);
1247 }
1248
1249 ICC_CTLR_EL3 icc_ctlr_el3 =
1250 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1251
1252 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1253 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1254 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1255 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1256 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1257 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1258
1259 val = icc_ctlr_el3;
1260 break;
1261 }
1262
1263 // Priority Mask Register
1264 case MISCREG_ICC_PMR:
1265 case MISCREG_ICC_PMR_EL1: {
1266 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1267 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1268 }
1269
1270 val &= 0xff;
1271 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1272
1273 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1274 // Spec section 4.8.1
1275 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1276 RegVal old_icc_pmr_el1 =
1277 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1278
1279 if (!(old_icc_pmr_el1 & 0x80)) {
1280 // If the current priority mask value is in the range of
1281 // 0x00-0x7F then WI
1282 return;
1283 }
1284
1285 // If the current priority mask value is in the range of
1286 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1287 // based on the Non-secure read of the priority mask value
1288 // written to the register.
1289
1290 val = (val >> 1) | 0x80;
1291 }
1292
1293 val &= ~0U << (8 - PRIORITY_BITS);
1294 break;
1295 }
1296
1297 // Interrupt Group 0 Enable Register EL1
1298 case MISCREG_ICC_IGRPEN0:
1299 case MISCREG_ICC_IGRPEN0_EL1: {
1300 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1301 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1302 }
1303
1304 break;
1305 }
1306
1307 // Virtual Interrupt Group 0 Enable register
1308 case MISCREG_ICV_IGRPEN0_EL1: {
1309 bool enable = val & 0x1;
1310 ICH_VMCR_EL2 ich_vmcr_el2 =
1311 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1312 ich_vmcr_el2.VENG0 = enable;
1313 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1314 virtualUpdate();
1315 return;
1316 }
1317
1318 // Interrupt Group 1 Enable register EL1
1319 case MISCREG_ICC_IGRPEN1:
1320 case MISCREG_ICC_IGRPEN1_EL1: {
1321 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1322 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1323 }
1324
1325 if (haveEL(EL3)) {
1326 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1327 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1328 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1329
1330 if (inSecureState()) {
1331 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1332 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1333 } else {
1334 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1335 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1336 }
1337
1338 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1339 icc_igrpen1_el3);
1340 }
1341
1342 break;
1343 }
1344
1345 // Virtual Interrupt Group 1 Enable register
1346 case MISCREG_ICV_IGRPEN1_EL1: {
1347 bool enable = val & 0x1;
1348 ICH_VMCR_EL2 ich_vmcr_el2 =
1349 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1350 ich_vmcr_el2.VENG1 = enable;
1351 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1352 virtualUpdate();
1353 return;
1354 }
1355
1356 // Interrupt Group 1 Enable register
1357 case MISCREG_ICC_MGRPEN1:
1358 case MISCREG_ICC_IGRPEN1_EL3: {
1359 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1360 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1361 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1362
1363 if (inSecureState()) {
1364 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1365 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1366 } else {
1367 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1368 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1369 }
1370
1371 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1372 break;
1373 }
1374
1375 // Software Generated Interrupt Group 0 Register
1376 case MISCREG_ICC_SGI0R:
1377 case MISCREG_ICC_SGI0R_EL1:
1378
1379 // Software Generated Interrupt Group 1 Register
1380 case MISCREG_ICC_SGI1R:
1381 case MISCREG_ICC_SGI1R_EL1:
1382
1383 // Alias Software Generated Interrupt Group 1 Register
1384 case MISCREG_ICC_ASGI1R:
1385 case MISCREG_ICC_ASGI1R_EL1: {
1386 bool ns = !inSecureState();
1387 Gicv3::GroupId group;
1388
1389 if (misc_reg == MISCREG_ICC_SGI1R_EL1) {
1390 group = ns ? Gicv3::G1NS : Gicv3::G1S;
1391 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) {
1392 group = ns ? Gicv3::G1S : Gicv3::G1NS;
1393 } else {
1394 group = Gicv3::G0S;
1395 }
1396
1397 if (distributor->DS && group == Gicv3::G1S) {
1398 group = Gicv3::G0S;
1399 }
1400
1401 uint8_t aff3 = bits(val, 55, 48);
1402 uint8_t aff2 = bits(val, 39, 32);
1403 uint8_t aff1 = bits(val, 23, 16);;
1404 uint16_t target_list = bits(val, 15, 0);
1405 uint32_t int_id = bits(val, 27, 24);
1406 bool irm = bits(val, 40, 40);
1407 uint8_t rs = bits(val, 47, 44);
1408
1409 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1410 Gicv3Redistributor * redistributor_i =
1411 gic->getRedistributor(i);
1412 uint32_t affinity_i = redistributor_i->getAffinity();
1413
1414 if (irm) {
1415 // Interrupts routed to all PEs in the system,
1416 // excluding "self"
1417 if (affinity_i == redistributor->getAffinity()) {
1418 continue;
1419 }
1420 } else {
1421 // Interrupts routed to the PEs specified by
1422 // Aff3.Aff2.Aff1.<target list>
1423 if ((affinity_i >> 8) !=
1424 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1425 continue;
1426 }
1427
1428 uint8_t aff0_i = bits(affinity_i, 7, 0);
1429
1430 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1431 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1432 continue;
1433 }
1434 }
1435
1436 redistributor_i->sendSGI(int_id, group, ns);
1437 }
1438
1439 break;
1440 }
1441
1442 // System Register Enable Register EL1
1443 case MISCREG_ICC_SRE:
1444 case MISCREG_ICC_SRE_EL1:
1445 // System Register Enable Register EL2
1446 case MISCREG_ICC_HSRE:
1447 case MISCREG_ICC_SRE_EL2:
1448 // System Register Enable Register EL3
1449 case MISCREG_ICC_MSRE:
1450 case MISCREG_ICC_SRE_EL3:
1451 // All bits are RAO/WI
1452 return;
1453
1454 // Hyp Control Register
1455 case MISCREG_ICH_HCR:
1456 case MISCREG_ICH_HCR_EL2: {
1457 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1458 ICH_HCR_EL2 ich_hcr_el2 =
1459 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1460
1461 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1462 {
1463 // EOIcount - Permitted behaviors are:
1464 // - Increment EOIcount.
1465 // - Leave EOIcount unchanged.
1466 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1467 }
1468
1469 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1470 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1471 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1472 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1473 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1474 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1475 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1476 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1477 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1478 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1479 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1480 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1481 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1482 val = ich_hcr_el2;
1483 do_virtual_update = true;
1484 break;
1485 }
1486
1487 // List Registers
1488 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1489 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1490 ICH_LRC requested_ich_lrc = val;
1491 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1492
1493 ich_lrc.State = requested_ich_lrc.State;
1494 ich_lrc.HW = requested_ich_lrc.HW;
1495 ich_lrc.Group = requested_ich_lrc.Group;
1496
1497 // Priority, bits [23:16]
1498 // At least five bits must be implemented.
1499 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1500 // We implement 5 bits.
1501 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1502 (ich_lrc.Priority & 0x07);
1503
1504 // pINTID, bits [12:0]
1505 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1506 // - Bits[12:10] : RES0.
1507 // - Bit[9] : EOI.
1508 // - Bits[8:0] : RES0.
1509 // When ICH_LR<n>.HW is 1:
1510 // - This field is only required to implement enough bits to hold a
1511 // valid value for the implemented INTID size. Any unused higher
1512 // order bits are RES0.
1513 if (requested_ich_lrc.HW == 0) {
1514 ich_lrc.EOI = requested_ich_lrc.EOI;
1515 } else {
1516 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1517 }
1518
1519 val = ich_lrc;
1520 do_virtual_update = true;
1521 break;
1522 }
1523
1524 // List Registers
1525 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1526 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1527 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1528 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1529 do_virtual_update = true;
1530 break;
1531 }
1532
1533 // List Registers
1534 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1535 ICH_LR_EL2 requested_ich_lr_el2 = val;
1536 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1537
1538 ich_lr_el2.State = requested_ich_lr_el2.State;
1539 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1540 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1541
1542 // Priority, bits [55:48]
1543 // At least five bits must be implemented.
1544 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1545 // We implement 5 bits.
1546 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1547 (ich_lr_el2.Priority & 0x07);
1548
1549 // pINTID, bits [44:32]
1550 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1551 // - Bits[44:42] : RES0.
1552 // - Bit[41] : EOI.
1553 // - Bits[40:32] : RES0.
1554 // When ICH_LR<n>_EL2.HW is 1:
1555 // - This field is only required to implement enough bits to hold a
1556 // valid value for the implemented INTID size. Any unused higher
1557 // order bits are RES0.
1558 if (requested_ich_lr_el2.HW == 0) {
1559 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1560 } else {
1561 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1562 }
1563
1564 // vINTID, bits [31:0]
1565 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1566 // though at least 16 bits must be implemented.
1567 // Unimplemented bits are RES0.
1568 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1569
1570 val = ich_lr_el2;
1571 do_virtual_update = true;
1572 break;
1573 }
1574
1575 // Virtual Machine Control Register
1576 case MISCREG_ICH_VMCR:
1577 case MISCREG_ICH_VMCR_EL2: {
1578 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1579 ICH_VMCR_EL2 ich_vmcr_el2 =
1580 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1581 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1582 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1583
1584 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1585 ich_vmcr_el2.VBPR0 = min_vpr0;
1586 } else {
1587 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1588 }
1589
1590 uint8_t min_vpr1 = min_vpr0 + 1;
1591
1592 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1593 ich_vmcr_el2.VBPR1 = min_vpr1;
1594 } else {
1595 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1596 }
1597
1598 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1599 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1600 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1601 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1602 val = ich_vmcr_el2;
1603 break;
1604 }
1605
1606 // Hyp Active Priorities Group 0 Registers
1607 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1608 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1609 // Hyp Active Priorities Group 1 Registers
1610 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1611 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1612 break;
1613
1614 default:
1615 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1616 misc_reg, miscRegName[misc_reg]);
1617 }
1618
1619 isa->setMiscRegNoEffect(misc_reg, val);
1620
1621 if (do_virtual_update) {
1622 virtualUpdate();
1623 }
1624}
1625
1626int
1627Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1628{
1629 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1630 ICH_LR_EL2 ich_lr_el2 =
1631 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1632
1633 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1634 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1635 (ich_lr_el2.vINTID == int_id)) {
1636 return lr_idx;
1637 }
1638 }
1639
1640 return -1;
1641}
1642
1643uint32_t
1644Gicv3CPUInterface::getHPPIR0() const
1645{
1646 if (hppi.prio == 0xff) {
1647 return Gicv3::INTID_SPURIOUS;
1648 }
1649
1650 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1651
1652 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1653 // interrupt for the other state pending
1654 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1655 }
1656
1657 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1658 return Gicv3::INTID_SPURIOUS;
1659 }
1660
1661 if (irq_is_secure && !inSecureState()) {
1662 // Secure interrupts not visible in Non-secure
1663 return Gicv3::INTID_SPURIOUS;
1664 }
1665
1666 return hppi.intid;
1667}
1668
1669uint32_t
1670Gicv3CPUInterface::getHPPIR1() const
1671{
1672 if (hppi.prio == 0xff) {
1673 return Gicv3::INTID_SPURIOUS;
1674 }
1675
1676 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1677 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1678 if (hppi.group == Gicv3::G0S) {
1679 return Gicv3::INTID_SECURE;
1680 } else if (hppi.group == Gicv3::G1NS) {
1681 return Gicv3::INTID_NONSECURE;
1682 }
1683 }
1684
1685 if (hppi.group == Gicv3::G0S) {
1686 return Gicv3::INTID_SPURIOUS;
1687 }
1688
1689 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1690
1691 if (irq_is_secure) {
1692 if (!inSecureState()) {
1693 // Secure interrupts not visible in Non-secure
1694 return Gicv3::INTID_SPURIOUS;
1695 }
1696 } else if (!isEL3OrMon() && inSecureState()) {
1697 // Group 1 non-secure interrupts not visible in Secure EL1
1698 return Gicv3::INTID_SPURIOUS;
1699 }
1700
1701 return hppi.intid;
1702}
1703
1704void
1705Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1706{
1707 int apr_misc_reg;
1708 RegVal apr;
1709 apr_misc_reg = group == Gicv3::G0S ?
1710 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1711 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1712
1713 if (apr) {
1714 apr &= apr - 1;
1715 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1716 }
1717
1718 update();
1719}
1720
1721uint8_t
1722Gicv3CPUInterface::virtualDropPriority()
1723{
1724 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1725
1726 for (int i = 0; i < apr_max; i++) {
1727 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1728 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1729
1730 if (!vapr0 && !vapr1) {
1731 continue;
1732 }
1733
1734 int vapr0_count = ctz32(vapr0);
1735 int vapr1_count = ctz32(vapr1);
1736
1737 if (vapr0_count <= vapr1_count) {
1738 vapr0 &= vapr0 - 1;
1739 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1740 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1741 } else {
1742 vapr1 &= vapr1 - 1;
1743 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1744 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1745 }
1746 }
1747
1748 return 0xff;
1749}
1750
1751void
1752Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1753{
1754 // Update active priority registers.
1755 uint32_t prio = hppi.prio & 0xf8;
1756 int apr_bit = prio >> (8 - PRIORITY_BITS);
1757 int reg_bit = apr_bit % 32;
1758 int apr_idx = group == Gicv3::G0S ?
1759 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1760 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1761 apr |= (1 << reg_bit);
1762 isa->setMiscRegNoEffect(apr_idx, apr);
1763
1764 // Move interrupt state from pending to active.
1765 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1766 // SGI or PPI, redistributor
1767 redistributor->activateIRQ(int_id);
1768 redistributor->updateAndInformCPUInterface();
1769 } else if (int_id < Gicv3::INTID_SECURE) {
1770 // SPI, distributor
1771 distributor->activateIRQ(int_id);
1772 distributor->updateAndInformCPUInterfaces();
| 855 return;
856 }
857
858 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
859
860 if (highestActiveGroup() == Gicv3::G0S) {
861 return;
862 }
863
864 if (distributor->DS == 0) {
865 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
866 return;
867 } else if (highestActiveGroup() == Gicv3::G1NS &&
868 !(!inSecureState() or (currEL() == EL3))) {
869 return;
870 }
871 }
872
873 dropPriority(group);
874
875 if (!isEOISplitMode()) {
876 deactivateIRQ(int_id, group);
877 }
878
879 break;
880 }
881
882 // Virtual End Of Interrupt Register 1
883 case MISCREG_ICV_EOIR1_EL1: {
884 int int_id = val & 0xffffff;
885
886 // avoid deactivation for special interrupts
887 if (int_id >= Gicv3::INTID_SECURE &&
888 int_id <= Gicv3::INTID_SPURIOUS) {
889 return;
890 }
891
892 uint8_t drop_prio = virtualDropPriority();
893
894 if (drop_prio == 0xff) {
895 return;
896 }
897
898 int lr_idx = virtualFindActive(int_id);
899
900 if (lr_idx < 0) {
901 // No matching LR found
902 virtualIncrementEOICount();
903 } else {
904 ICH_LR_EL2 ich_lr_el2 =
905 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
906 Gicv3::GroupId lr_group =
907 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
908 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
909
910 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
911 if (!virtualIsEOISplitMode()) {
912 virtualDeactivateIRQ(lr_idx);
913 }
914 }
915 }
916
917 virtualUpdate();
918 break;
919 }
920
921 // Deactivate Interrupt Register
922 case MISCREG_ICC_DIR:
923 case MISCREG_ICC_DIR_EL1: {
924 if ((currEL() == EL1) && !inSecureState() &&
925 (hcr_imo || hcr_fmo)) {
926 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
927 }
928
929 int int_id = val & 0xffffff;
930
931 // The following checks are as per spec pseudocode
932 // aarch64/support/ICC_DIR_EL1
933
934 // Check for spurious ID
935 if (int_id >= Gicv3::INTID_SECURE) {
936 return;
937 }
938
939 // EOI mode is not set, so don't deactivate
940 if (!isEOISplitMode()) {
941 return;
942 }
943
944 Gicv3::GroupId group =
945 int_id >= 32 ? distributor->getIntGroup(int_id) :
946 redistributor->getIntGroup(int_id);
947 bool irq_is_grp0 = group == Gicv3::G0S;
948 bool single_sec_state = distributor->DS;
949 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
950 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
951 bool route_fiq_to_el3 = scr_el3.fiq;
952 bool route_irq_to_el3 = scr_el3.irq;
953 bool route_fiq_to_el2 = hcr_fmo;
954 bool route_irq_to_el2 = hcr_imo;
955
956 switch (currEL()) {
957 case EL3:
958 break;
959
960 case EL2:
961 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
962 break;
963 }
964
965 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
966 break;
967 }
968
969 return;
970
971 case EL1:
972 if (!isSecureBelowEL3()) {
973 if (single_sec_state && irq_is_grp0 &&
974 !route_fiq_to_el3 && !route_fiq_to_el2) {
975 break;
976 }
977
978 if (!irq_is_secure && !irq_is_grp0 &&
979 !route_irq_to_el3 && !route_irq_to_el2) {
980 break;
981 }
982 } else {
983 if (irq_is_grp0 && !route_fiq_to_el3) {
984 break;
985 }
986
987 if (!irq_is_grp0 &&
988 (!irq_is_secure || !single_sec_state) &&
989 !route_irq_to_el3) {
990 break;
991 }
992 }
993
994 return;
995
996 default:
997 break;
998 }
999
1000 deactivateIRQ(int_id, group);
1001 break;
1002 }
1003
1004 // Deactivate Virtual Interrupt Register
1005 case MISCREG_ICV_DIR_EL1: {
1006 int int_id = val & 0xffffff;
1007
1008 // avoid deactivation for special interrupts
1009 if (int_id >= Gicv3::INTID_SECURE &&
1010 int_id <= Gicv3::INTID_SPURIOUS) {
1011 return;
1012 }
1013
1014 if (!virtualIsEOISplitMode()) {
1015 return;
1016 }
1017
1018 int lr_idx = virtualFindActive(int_id);
1019
1020 if (lr_idx < 0) {
1021 // No matching LR found
1022 virtualIncrementEOICount();
1023 } else {
1024 virtualDeactivateIRQ(lr_idx);
1025 }
1026
1027 virtualUpdate();
1028 break;
1029 }
1030
1031 // Binary Point Register 0
1032 case MISCREG_ICC_BPR0:
1033 case MISCREG_ICC_BPR0_EL1:
1034 // Binary Point Register 1
1035 case MISCREG_ICC_BPR1:
1036 case MISCREG_ICC_BPR1_EL1: {
1037 if ((currEL() == EL1) && !inSecureState()) {
1038 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1039 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1040 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1041 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1042 }
1043 }
1044
1045 Gicv3::GroupId group =
1046 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1047
1048 if (group == Gicv3::G1S && !inSecureState()) {
1049 group = Gicv3::G1NS;
1050 }
1051
1052 ICC_CTLR_EL1 icc_ctlr_el1_s =
1053 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1054
1055 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1056 icc_ctlr_el1_s.CBPR) {
1057 group = Gicv3::G0S;
1058 }
1059
1060 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1061 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1062
1063 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1064 icc_ctlr_el1_ns.CBPR) {
1065 // BPR0 + 1 saturated to 7, WI
1066 return;
1067 }
1068
1069 uint8_t min_val = (group == Gicv3::G1NS) ?
1070 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1071 val &= 0x7;
1072
1073 if (val < min_val) {
1074 val = min_val;
1075 }
1076
1077 break;
1078 }
1079
1080 // Virtual Binary Point Register 0
1081 case MISCREG_ICV_BPR0_EL1:
1082 // Virtual Binary Point Register 1
1083 case MISCREG_ICV_BPR1_EL1: {
1084 Gicv3::GroupId group =
1085 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1086 ICH_VMCR_EL2 ich_vmcr_el2 =
1087 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1088
1089 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1090 // BPR0 + 1 saturated to 7, WI
1091 return;
1092 }
1093
1094 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1095
1096 if (group != Gicv3::G0S) {
1097 min_VPBR++;
1098 }
1099
1100 if (val < min_VPBR) {
1101 val = min_VPBR;
1102 }
1103
1104 if (group == Gicv3::G0S) {
1105 ich_vmcr_el2.VBPR0 = val;
1106 } else {
1107 ich_vmcr_el2.VBPR1 = val;
1108 }
1109
1110 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1111 do_virtual_update = true;
1112 break;
1113 }
1114
1115 // Control Register EL1
1116 case MISCREG_ICC_CTLR:
1117 case MISCREG_ICC_CTLR_EL1: {
1118 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1119 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1120 }
1121
1122 /*
1123 * ExtRange is RO.
1124 * RSS is RO.
1125 * A3V is RO.
1126 * SEIS is RO.
1127 * IDbits is RO.
1128 * PRIbits is RO.
1129 */
1130 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1131 ICC_CTLR_EL1 icc_ctlr_el1 =
1132 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1133
1134 ICC_CTLR_EL3 icc_ctlr_el3 =
1135 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1136
1137 // The following could be refactored but it is following
1138 // spec description section 9.2.6 point by point.
1139
1140 // PMHE
1141 if (haveEL(EL3)) {
1142 // PMHE is alias of ICC_CTLR_EL3.PMHE
1143
1144 if (distributor->DS == 0) {
1145 // PMHE is RO
1146 } else if (distributor->DS == 1) {
1147 // PMHE is RW
1148 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1149 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1150 }
1151 } else {
1152 // PMHE is RW (by implementation choice)
1153 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1154 }
1155
1156 // EOImode
1157 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1158
1159 if (inSecureState()) {
1160 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1161 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1162 } else {
1163 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1164 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1165 }
1166
1167 // CBPR
1168 if (haveEL(EL3)) {
1169 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1170
1171 if (distributor->DS == 0) {
1172 // CBPR is RO
1173 } else {
1174 // CBPR is RW
1175 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1176
1177 if (inSecureState()) {
1178 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1179 } else {
1180 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1181 }
1182 }
1183 } else {
1184 // CBPR is RW
1185 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1186 }
1187
1188 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1189
1190 val = icc_ctlr_el1;
1191 break;
1192 }
1193
1194 // Virtual Control Register
1195 case MISCREG_ICV_CTLR_EL1: {
1196 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1197 ICV_CTLR_EL1 icv_ctlr_el1 =
1198 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1199 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1200 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1201 val = icv_ctlr_el1;
1202
1203 // Aliases
1204 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1205 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1206 ICH_VMCR_EL2 ich_vmcr_el2 =
1207 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1208 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1209 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1210 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1211 break;
1212 }
1213
1214 // Control Register EL3
1215 case MISCREG_ICC_MCTLR:
1216 case MISCREG_ICC_CTLR_EL3: {
1217 /*
1218 * ExtRange is RO.
1219 * RSS is RO.
1220 * nDS is RO.
1221 * A3V is RO.
1222 * SEIS is RO.
1223 * IDbits is RO.
1224 * PRIbits is RO.
1225 * PMHE is RAO/WI, priority-based routing is always used.
1226 */
1227 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1228
1229 // Aliases
1230 if (haveEL(EL3))
1231 {
1232 ICC_CTLR_EL1 icc_ctlr_el1_s =
1233 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1234 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1235 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1236
1237 // ICC_CTLR_EL1(NS).EOImode is an alias of
1238 // ICC_CTLR_EL3.EOImode_EL1NS
1239 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1240 // ICC_CTLR_EL1(S).EOImode is an alias of
1241 // ICC_CTLR_EL3.EOImode_EL1S
1242 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1243 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1244 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1245 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1246 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1247
1248 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1249 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1250 icc_ctlr_el1_ns);
1251 }
1252
1253 ICC_CTLR_EL3 icc_ctlr_el3 =
1254 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1255
1256 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1257 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1258 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1259 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1260 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1261 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1262
1263 val = icc_ctlr_el3;
1264 break;
1265 }
1266
1267 // Priority Mask Register
1268 case MISCREG_ICC_PMR:
1269 case MISCREG_ICC_PMR_EL1: {
1270 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1271 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1272 }
1273
1274 val &= 0xff;
1275 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1276
1277 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1278 // Spec section 4.8.1
1279 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1280 RegVal old_icc_pmr_el1 =
1281 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1282
1283 if (!(old_icc_pmr_el1 & 0x80)) {
1284 // If the current priority mask value is in the range of
1285 // 0x00-0x7F then WI
1286 return;
1287 }
1288
1289 // If the current priority mask value is in the range of
1290 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1291 // based on the Non-secure read of the priority mask value
1292 // written to the register.
1293
1294 val = (val >> 1) | 0x80;
1295 }
1296
1297 val &= ~0U << (8 - PRIORITY_BITS);
1298 break;
1299 }
1300
1301 // Interrupt Group 0 Enable Register EL1
1302 case MISCREG_ICC_IGRPEN0:
1303 case MISCREG_ICC_IGRPEN0_EL1: {
1304 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1305 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1306 }
1307
1308 break;
1309 }
1310
1311 // Virtual Interrupt Group 0 Enable register
1312 case MISCREG_ICV_IGRPEN0_EL1: {
1313 bool enable = val & 0x1;
1314 ICH_VMCR_EL2 ich_vmcr_el2 =
1315 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1316 ich_vmcr_el2.VENG0 = enable;
1317 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1318 virtualUpdate();
1319 return;
1320 }
1321
1322 // Interrupt Group 1 Enable register EL1
1323 case MISCREG_ICC_IGRPEN1:
1324 case MISCREG_ICC_IGRPEN1_EL1: {
1325 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1326 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1327 }
1328
1329 if (haveEL(EL3)) {
1330 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1331 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1332 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1333
1334 if (inSecureState()) {
1335 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1336 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1337 } else {
1338 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1339 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1340 }
1341
1342 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1343 icc_igrpen1_el3);
1344 }
1345
1346 break;
1347 }
1348
1349 // Virtual Interrupt Group 1 Enable register
1350 case MISCREG_ICV_IGRPEN1_EL1: {
1351 bool enable = val & 0x1;
1352 ICH_VMCR_EL2 ich_vmcr_el2 =
1353 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1354 ich_vmcr_el2.VENG1 = enable;
1355 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1356 virtualUpdate();
1357 return;
1358 }
1359
1360 // Interrupt Group 1 Enable register
1361 case MISCREG_ICC_MGRPEN1:
1362 case MISCREG_ICC_IGRPEN1_EL3: {
1363 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1364 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1365 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1366
1367 if (inSecureState()) {
1368 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1369 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1370 } else {
1371 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1372 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1373 }
1374
1375 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1376 break;
1377 }
1378
1379 // Software Generated Interrupt Group 0 Register
1380 case MISCREG_ICC_SGI0R:
1381 case MISCREG_ICC_SGI0R_EL1:
1382
1383 // Software Generated Interrupt Group 1 Register
1384 case MISCREG_ICC_SGI1R:
1385 case MISCREG_ICC_SGI1R_EL1:
1386
1387 // Alias Software Generated Interrupt Group 1 Register
1388 case MISCREG_ICC_ASGI1R:
1389 case MISCREG_ICC_ASGI1R_EL1: {
1390 bool ns = !inSecureState();
1391 Gicv3::GroupId group;
1392
1393 if (misc_reg == MISCREG_ICC_SGI1R_EL1) {
1394 group = ns ? Gicv3::G1NS : Gicv3::G1S;
1395 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) {
1396 group = ns ? Gicv3::G1S : Gicv3::G1NS;
1397 } else {
1398 group = Gicv3::G0S;
1399 }
1400
1401 if (distributor->DS && group == Gicv3::G1S) {
1402 group = Gicv3::G0S;
1403 }
1404
1405 uint8_t aff3 = bits(val, 55, 48);
1406 uint8_t aff2 = bits(val, 39, 32);
1407 uint8_t aff1 = bits(val, 23, 16);;
1408 uint16_t target_list = bits(val, 15, 0);
1409 uint32_t int_id = bits(val, 27, 24);
1410 bool irm = bits(val, 40, 40);
1411 uint8_t rs = bits(val, 47, 44);
1412
1413 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1414 Gicv3Redistributor * redistributor_i =
1415 gic->getRedistributor(i);
1416 uint32_t affinity_i = redistributor_i->getAffinity();
1417
1418 if (irm) {
1419 // Interrupts routed to all PEs in the system,
1420 // excluding "self"
1421 if (affinity_i == redistributor->getAffinity()) {
1422 continue;
1423 }
1424 } else {
1425 // Interrupts routed to the PEs specified by
1426 // Aff3.Aff2.Aff1.<target list>
1427 if ((affinity_i >> 8) !=
1428 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1429 continue;
1430 }
1431
1432 uint8_t aff0_i = bits(affinity_i, 7, 0);
1433
1434 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1435 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1436 continue;
1437 }
1438 }
1439
1440 redistributor_i->sendSGI(int_id, group, ns);
1441 }
1442
1443 break;
1444 }
1445
1446 // System Register Enable Register EL1
1447 case MISCREG_ICC_SRE:
1448 case MISCREG_ICC_SRE_EL1:
1449 // System Register Enable Register EL2
1450 case MISCREG_ICC_HSRE:
1451 case MISCREG_ICC_SRE_EL2:
1452 // System Register Enable Register EL3
1453 case MISCREG_ICC_MSRE:
1454 case MISCREG_ICC_SRE_EL3:
1455 // All bits are RAO/WI
1456 return;
1457
1458 // Hyp Control Register
1459 case MISCREG_ICH_HCR:
1460 case MISCREG_ICH_HCR_EL2: {
1461 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1462 ICH_HCR_EL2 ich_hcr_el2 =
1463 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1464
1465 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1466 {
1467 // EOIcount - Permitted behaviors are:
1468 // - Increment EOIcount.
1469 // - Leave EOIcount unchanged.
1470 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1471 }
1472
1473 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1474 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1475 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1476 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1477 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1478 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1479 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1480 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1481 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1482 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1483 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1484 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1485 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1486 val = ich_hcr_el2;
1487 do_virtual_update = true;
1488 break;
1489 }
1490
1491 // List Registers
1492 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1493 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1494 ICH_LRC requested_ich_lrc = val;
1495 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1496
1497 ich_lrc.State = requested_ich_lrc.State;
1498 ich_lrc.HW = requested_ich_lrc.HW;
1499 ich_lrc.Group = requested_ich_lrc.Group;
1500
1501 // Priority, bits [23:16]
1502 // At least five bits must be implemented.
1503 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1504 // We implement 5 bits.
1505 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1506 (ich_lrc.Priority & 0x07);
1507
1508 // pINTID, bits [12:0]
1509 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1510 // - Bits[12:10] : RES0.
1511 // - Bit[9] : EOI.
1512 // - Bits[8:0] : RES0.
1513 // When ICH_LR<n>.HW is 1:
1514 // - This field is only required to implement enough bits to hold a
1515 // valid value for the implemented INTID size. Any unused higher
1516 // order bits are RES0.
1517 if (requested_ich_lrc.HW == 0) {
1518 ich_lrc.EOI = requested_ich_lrc.EOI;
1519 } else {
1520 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1521 }
1522
1523 val = ich_lrc;
1524 do_virtual_update = true;
1525 break;
1526 }
1527
1528 // List Registers
1529 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1530 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1531 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1532 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1533 do_virtual_update = true;
1534 break;
1535 }
1536
1537 // List Registers
1538 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1539 ICH_LR_EL2 requested_ich_lr_el2 = val;
1540 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1541
1542 ich_lr_el2.State = requested_ich_lr_el2.State;
1543 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1544 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1545
1546 // Priority, bits [55:48]
1547 // At least five bits must be implemented.
1548 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1549 // We implement 5 bits.
1550 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1551 (ich_lr_el2.Priority & 0x07);
1552
1553 // pINTID, bits [44:32]
1554 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1555 // - Bits[44:42] : RES0.
1556 // - Bit[41] : EOI.
1557 // - Bits[40:32] : RES0.
1558 // When ICH_LR<n>_EL2.HW is 1:
1559 // - This field is only required to implement enough bits to hold a
1560 // valid value for the implemented INTID size. Any unused higher
1561 // order bits are RES0.
1562 if (requested_ich_lr_el2.HW == 0) {
1563 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1564 } else {
1565 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1566 }
1567
1568 // vINTID, bits [31:0]
1569 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1570 // though at least 16 bits must be implemented.
1571 // Unimplemented bits are RES0.
1572 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1573
1574 val = ich_lr_el2;
1575 do_virtual_update = true;
1576 break;
1577 }
1578
1579 // Virtual Machine Control Register
1580 case MISCREG_ICH_VMCR:
1581 case MISCREG_ICH_VMCR_EL2: {
1582 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1583 ICH_VMCR_EL2 ich_vmcr_el2 =
1584 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1585 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1586 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1587
1588 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1589 ich_vmcr_el2.VBPR0 = min_vpr0;
1590 } else {
1591 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1592 }
1593
1594 uint8_t min_vpr1 = min_vpr0 + 1;
1595
1596 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1597 ich_vmcr_el2.VBPR1 = min_vpr1;
1598 } else {
1599 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1600 }
1601
1602 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1603 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1604 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1605 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1606 val = ich_vmcr_el2;
1607 break;
1608 }
1609
1610 // Hyp Active Priorities Group 0 Registers
1611 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1612 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1613 // Hyp Active Priorities Group 1 Registers
1614 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1615 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1616 break;
1617
1618 default:
1619 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1620 misc_reg, miscRegName[misc_reg]);
1621 }
1622
1623 isa->setMiscRegNoEffect(misc_reg, val);
1624
1625 if (do_virtual_update) {
1626 virtualUpdate();
1627 }
1628}
1629
1630int
1631Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1632{
1633 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1634 ICH_LR_EL2 ich_lr_el2 =
1635 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1636
1637 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1638 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1639 (ich_lr_el2.vINTID == int_id)) {
1640 return lr_idx;
1641 }
1642 }
1643
1644 return -1;
1645}
1646
1647uint32_t
1648Gicv3CPUInterface::getHPPIR0() const
1649{
1650 if (hppi.prio == 0xff) {
1651 return Gicv3::INTID_SPURIOUS;
1652 }
1653
1654 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1655
1656 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1657 // interrupt for the other state pending
1658 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1659 }
1660
1661 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1662 return Gicv3::INTID_SPURIOUS;
1663 }
1664
1665 if (irq_is_secure && !inSecureState()) {
1666 // Secure interrupts not visible in Non-secure
1667 return Gicv3::INTID_SPURIOUS;
1668 }
1669
1670 return hppi.intid;
1671}
1672
1673uint32_t
1674Gicv3CPUInterface::getHPPIR1() const
1675{
1676 if (hppi.prio == 0xff) {
1677 return Gicv3::INTID_SPURIOUS;
1678 }
1679
1680 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1681 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1682 if (hppi.group == Gicv3::G0S) {
1683 return Gicv3::INTID_SECURE;
1684 } else if (hppi.group == Gicv3::G1NS) {
1685 return Gicv3::INTID_NONSECURE;
1686 }
1687 }
1688
1689 if (hppi.group == Gicv3::G0S) {
1690 return Gicv3::INTID_SPURIOUS;
1691 }
1692
1693 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1694
1695 if (irq_is_secure) {
1696 if (!inSecureState()) {
1697 // Secure interrupts not visible in Non-secure
1698 return Gicv3::INTID_SPURIOUS;
1699 }
1700 } else if (!isEL3OrMon() && inSecureState()) {
1701 // Group 1 non-secure interrupts not visible in Secure EL1
1702 return Gicv3::INTID_SPURIOUS;
1703 }
1704
1705 return hppi.intid;
1706}
1707
1708void
1709Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1710{
1711 int apr_misc_reg;
1712 RegVal apr;
1713 apr_misc_reg = group == Gicv3::G0S ?
1714 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1715 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1716
1717 if (apr) {
1718 apr &= apr - 1;
1719 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1720 }
1721
1722 update();
1723}
1724
1725uint8_t
1726Gicv3CPUInterface::virtualDropPriority()
1727{
1728 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1729
1730 for (int i = 0; i < apr_max; i++) {
1731 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1732 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1733
1734 if (!vapr0 && !vapr1) {
1735 continue;
1736 }
1737
1738 int vapr0_count = ctz32(vapr0);
1739 int vapr1_count = ctz32(vapr1);
1740
1741 if (vapr0_count <= vapr1_count) {
1742 vapr0 &= vapr0 - 1;
1743 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1744 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1745 } else {
1746 vapr1 &= vapr1 - 1;
1747 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1748 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1749 }
1750 }
1751
1752 return 0xff;
1753}
1754
1755void
1756Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1757{
1758 // Update active priority registers.
1759 uint32_t prio = hppi.prio & 0xf8;
1760 int apr_bit = prio >> (8 - PRIORITY_BITS);
1761 int reg_bit = apr_bit % 32;
1762 int apr_idx = group == Gicv3::G0S ?
1763 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1764 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1765 apr |= (1 << reg_bit);
1766 isa->setMiscRegNoEffect(apr_idx, apr);
1767
1768 // Move interrupt state from pending to active.
1769 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1770 // SGI or PPI, redistributor
1771 redistributor->activateIRQ(int_id);
1772 redistributor->updateAndInformCPUInterface();
1773 } else if (int_id < Gicv3::INTID_SECURE) {
1774 // SPI, distributor
1775 distributor->activateIRQ(int_id);
1776 distributor->updateAndInformCPUInterfaces();
|
| 1777 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
1778 // LPI, Redistributor
1779 redistributor->setClrLPI(int_id, false);
|
1773 }
1774}
1775
1776void
1777Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1778{
1779 // Update active priority registers.
1780 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1781 lr_idx);
1782 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1783 uint8_t prio = ich_lr_el.Priority & 0xf8;
1784 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1785 int reg_no = apr_bit / 32;
1786 int reg_bit = apr_bit % 32;
1787 int apr_idx = group == Gicv3::G0S ?
1788 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1789 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1790 apr |= (1 << reg_bit);
1791 isa->setMiscRegNoEffect(apr_idx, apr);
1792 // Move interrupt state from pending to active.
1793 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1794 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1795}
1796
1797void
1798Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1799{
1800 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1801 // SGI or PPI, redistributor
1802 redistributor->deactivateIRQ(int_id);
1803 redistributor->updateAndInformCPUInterface();
1804 } else if (int_id < Gicv3::INTID_SECURE) {
1805 // SPI, distributor
1806 distributor->deactivateIRQ(int_id);
1807 distributor->updateAndInformCPUInterfaces();
1808 } else {
| 1780 }
1781}
1782
1783void
1784Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1785{
1786 // Update active priority registers.
1787 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1788 lr_idx);
1789 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1790 uint8_t prio = ich_lr_el.Priority & 0xf8;
1791 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1792 int reg_no = apr_bit / 32;
1793 int reg_bit = apr_bit % 32;
1794 int apr_idx = group == Gicv3::G0S ?
1795 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1796 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1797 apr |= (1 << reg_bit);
1798 isa->setMiscRegNoEffect(apr_idx, apr);
1799 // Move interrupt state from pending to active.
1800 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1801 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1802}
1803
1804void
1805Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1806{
1807 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1808 // SGI or PPI, redistributor
1809 redistributor->deactivateIRQ(int_id);
1810 redistributor->updateAndInformCPUInterface();
1811 } else if (int_id < Gicv3::INTID_SECURE) {
1812 // SPI, distributor
1813 distributor->deactivateIRQ(int_id);
1814 distributor->updateAndInformCPUInterfaces();
1815 } else {
|
1809 return;
| 1816 // LPI, redistributor, shouldn't deactivate
1817 redistributor->updateAndInformCPUInterface();
|
1810 }
1811}
1812
1813void
1814Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1815{
1816 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1817 lr_idx);
1818
1819 if (ich_lr_el2.HW) {
1820 // Deactivate the associated physical interrupt
1821 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1822 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1823 distributor->getIntGroup(ich_lr_el2.pINTID) :
1824 redistributor->getIntGroup(ich_lr_el2.pINTID);
1825 deactivateIRQ(ich_lr_el2.pINTID, group);
1826 }
1827 }
1828
1829 // Remove the active bit
1830 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1831 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1832}
1833
1834/*
1835 * Returns the priority group field for the current BPR value for the group.
1836 * GroupBits() Pseudocode from spec.
1837 */
1838uint32_t
1839Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
1840{
1841 ICC_CTLR_EL1 icc_ctlr_el1_s =
1842 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1843 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1844 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1845
1846 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1847 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1848 group = Gicv3::G0S;
1849 }
1850
1851 int bpr;
1852
1853 if (group == Gicv3::G0S) {
1854 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
1855 } else {
1856 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
1857 }
1858
1859 if (group == Gicv3::G1NS) {
1860 assert(bpr > 0);
1861 bpr--;
1862 }
1863
1864 return ~0U << (bpr + 1);
1865}
1866
1867uint32_t
1868Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1869{
1870 ICH_VMCR_EL2 ich_vmcr_el2 =
1871 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1872
1873 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1874 group = Gicv3::G0S;
1875 }
1876
1877 int bpr;
1878
1879 if (group == Gicv3::G0S) {
1880 bpr = ich_vmcr_el2.VBPR0;
1881 } else {
1882 bpr = ich_vmcr_el2.VBPR1;
1883 }
1884
1885 if (group == Gicv3::G1NS) {
1886 assert(bpr > 0);
1887 bpr--;
1888 }
1889
1890 return ~0U << (bpr + 1);
1891}
1892
1893bool
1894Gicv3CPUInterface::isEOISplitMode() const
1895{
1896 if (isEL3OrMon()) {
1897 ICC_CTLR_EL3 icc_ctlr_el3 =
1898 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1899 return icc_ctlr_el3.EOImode_EL3;
1900 } else {
1901 ICC_CTLR_EL1 icc_ctlr_el1 =
1902 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1903 return icc_ctlr_el1.EOImode;
1904 }
1905}
1906
1907bool
1908Gicv3CPUInterface::virtualIsEOISplitMode() const
1909{
1910 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1911 return ich_vmcr_el2.VEOIM;
1912}
1913
1914int
1915Gicv3CPUInterface::highestActiveGroup() const
1916{
1917 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1918 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
1919 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
1920
1921 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
1922 return Gicv3::G1NS;
1923 }
1924
1925 if (gq_ctz < g0_ctz) {
1926 return Gicv3::G1S;
1927 }
1928
1929 if (g0_ctz < 32) {
1930 return Gicv3::G0S;
1931 }
1932
1933 return -1;
1934}
1935
1936void
1937Gicv3CPUInterface::update()
1938{
1939 bool signal_IRQ = false;
1940 bool signal_FIQ = false;
1941
1942 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
1943 /*
1944 * Secure enabled GIC sending a G1S IRQ to a secure disabled
1945 * CPU -> send G0 IRQ
1946 */
1947 hppi.group = Gicv3::G0S;
1948 }
1949
1950 if (hppiCanPreempt()) {
1951 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
1952 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
1953 "posting int as %d!\n", int_type);
1954 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
1955 }
1956
1957 if (signal_IRQ) {
1958 gic->postInt(cpuId, ArmISA::INT_IRQ);
1959 } else {
1960 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
1961 }
1962
1963 if (signal_FIQ) {
1964 gic->postInt(cpuId, ArmISA::INT_FIQ);
1965 } else {
1966 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
1967 }
1968}
1969
1970void
1971Gicv3CPUInterface::virtualUpdate()
1972{
1973 bool signal_IRQ = false;
1974 bool signal_FIQ = false;
1975 int lr_idx = getHPPVILR();
1976
1977 if (lr_idx >= 0) {
1978 ICH_LR_EL2 ich_lr_el2 =
1979 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1980
1981 if (hppviCanPreempt(lr_idx)) {
1982 if (ich_lr_el2.Group) {
1983 signal_IRQ = true;
1984 } else {
1985 signal_FIQ = true;
1986 }
1987 }
1988 }
1989
1990 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1991
1992 if (ich_hcr_el2.En) {
1993 if (maintenanceInterruptStatus()) {
1994 maintenanceInterrupt->raise();
1995 }
1996 }
1997
1998 if (signal_IRQ) {
1999 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2000 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2001 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2002 } else {
2003 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2004 }
2005
2006 if (signal_FIQ) {
2007 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2008 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2009 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2010 } else {
2011 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2012 }
2013}
2014
2015// Returns the index of the LR with the HPPI
2016int
2017Gicv3CPUInterface::getHPPVILR() const
2018{
2019 int idx = -1;
2020 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2021
2022 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2023 // VG0 and VG1 disabled...
2024 return idx;
2025 }
2026
2027 uint8_t highest_prio = 0xff;
2028
2029 for (int i = 0; i < 16; i++) {
2030 ICH_LR_EL2 ich_lr_el2 =
2031 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2032
2033 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2034 continue;
2035 }
2036
2037 if (ich_lr_el2.Group) {
2038 // VG1
2039 if (!ich_vmcr_el2.VENG1) {
2040 continue;
2041 }
2042 } else {
2043 // VG0
2044 if (!ich_vmcr_el2.VENG0) {
2045 continue;
2046 }
2047 }
2048
2049 uint8_t prio = ich_lr_el2.Priority;
2050
2051 if (prio < highest_prio) {
2052 highest_prio = prio;
2053 idx = i;
2054 }
2055 }
2056
2057 return idx;
2058}
2059
2060bool
2061Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2062{
2063 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2064 if (!ich_hcr_el2.En) {
2065 // virtual interface is disabled
2066 return false;
2067 }
2068
2069 ICH_LR_EL2 ich_lr_el2 =
2070 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2071 uint8_t prio = ich_lr_el2.Priority;
2072 uint8_t vpmr =
2073 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2074
2075 if (prio >= vpmr) {
2076 // prioriry masked
2077 return false;
2078 }
2079
2080 uint8_t rprio = virtualHighestActivePriority();
2081
2082 if (rprio == 0xff) {
2083 return true;
2084 }
2085
2086 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2087 uint32_t prio_mask = virtualGroupPriorityMask(group);
2088
2089 if ((prio & prio_mask) < (rprio & prio_mask)) {
2090 return true;
2091 }
2092
2093 return false;
2094}
2095
2096uint8_t
2097Gicv3CPUInterface::virtualHighestActivePriority() const
2098{
2099 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2100
2101 for (int i = 0; i < num_aprs; i++) {
2102 RegVal vapr =
2103 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2104 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2105
2106 if (!vapr) {
2107 continue;
2108 }
2109
2110 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2111 }
2112
2113 // no active interrups, return idle priority
2114 return 0xff;
2115}
2116
2117void
2118Gicv3CPUInterface::virtualIncrementEOICount()
2119{
2120 // Increment the EOICOUNT field in ICH_HCR_EL2
2121 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2122 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2123 EOI_cout++;
2124 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2125 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2126}
2127
2128// spec section 4.6.2
2129ArmISA::InterruptTypes
2130Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2131{
2132 bool is_fiq = false;
2133
2134 switch (group) {
2135 case Gicv3::G0S:
2136 is_fiq = true;
2137 break;
2138
2139 case Gicv3::G1S:
2140 is_fiq = (distributor->DS == 0) &&
2141 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2142 break;
2143
2144 case Gicv3::G1NS:
2145 is_fiq = (distributor->DS == 0) && inSecureState();
2146 break;
2147
2148 default:
2149 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2150 }
2151
2152 if (is_fiq) {
2153 return ArmISA::INT_FIQ;
2154 } else {
2155 return ArmISA::INT_IRQ;
2156 }
2157}
2158
2159bool
2160Gicv3CPUInterface::hppiCanPreempt() const
2161{
2162 if (hppi.prio == 0xff) {
2163 // there is no pending interrupt
2164 return false;
2165 }
2166
2167 if (!groupEnabled(hppi.group)) {
2168 // group disabled at CPU interface
2169 return false;
2170 }
2171
2172 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2173 // priority masked
2174 return false;
2175 }
2176
2177 uint8_t rprio = highestActivePriority();
2178
2179 if (rprio == 0xff) {
2180 return true;
2181 }
2182
2183 uint32_t prio_mask = groupPriorityMask(hppi.group);
2184
2185 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2186 return true;
2187 }
2188
2189 return false;
2190}
2191
2192uint8_t
2193Gicv3CPUInterface::highestActivePriority() const
2194{
2195 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2196 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2197 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2198
2199 if (apr) {
2200 return ctz32(apr) << (GIC_MIN_BPR + 1);
2201 }
2202
2203 // no active interrups, return idle priority
2204 return 0xff;
2205}
2206
2207bool
2208Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2209{
2210 switch (group) {
2211 case Gicv3::G0S: {
2212 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2213 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2214 return icc_igrpen0_el1.Enable;
2215 }
2216
2217 case Gicv3::G1S: {
2218 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2219 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2220 return icc_igrpen1_el1_s.Enable;
2221 }
2222
2223 case Gicv3::G1NS: {
2224 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2225 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2226 return icc_igrpen1_el1_ns.Enable;
2227 }
2228
2229 default:
2230 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2231 }
2232}
2233
2234bool
2235Gicv3CPUInterface::inSecureState() const
2236{
2237 if (!gic->getSystem()->haveSecurity()) {
2238 return false;
2239 }
2240
2241 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2242 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2243 return ArmISA::inSecureState(scr, cpsr);
2244}
2245
2246int
2247Gicv3CPUInterface::currEL() const
2248{
2249 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2250 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2251
2252 if (is_64) {
2253 return (ExceptionLevel)(uint8_t) cpsr.el;
2254 } else {
2255 switch (cpsr.mode) {
2256 case MODE_USER:
2257 return 0;
2258
2259 case MODE_HYP:
2260 return 2;
2261
2262 case MODE_MON:
2263 return 3;
2264
2265 default:
2266 return 1;
2267 }
2268 }
2269}
2270
2271bool
2272Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2273{
2274 switch (el) {
2275 case EL0:
2276 case EL1:
2277 return true;
2278
2279 case EL2:
2280 return gic->getSystem()->haveVirtualization();
2281
2282 case EL3:
2283 return gic->getSystem()->haveSecurity();
2284
2285 default:
2286 warn("Unimplemented Exception Level\n");
2287 return false;
2288 }
2289}
2290
2291bool
2292Gicv3CPUInterface::isSecureBelowEL3() const
2293{
2294 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2295 return haveEL(EL3) && scr.ns == 0;
2296}
2297
2298bool
2299Gicv3CPUInterface::isAA64() const
2300{
2301 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2302 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2303}
2304
2305bool
2306Gicv3CPUInterface::isEL3OrMon() const
2307{
2308 if (haveEL(EL3)) {
2309 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2310 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2311
2312 if (is_64 && (cpsr.el == EL3)) {
2313 return true;
2314 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2315 return true;
2316 }
2317 }
2318
2319 return false;
2320}
2321
2322// Computes ICH_EISR_EL2
2323uint64_t
2324Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2325{
2326 // ICH_EISR_EL2
2327 // Bits [63:16] - RES0
2328 // Status<n>, bit [n], for n = 0 to 15
2329 // EOI maintenance interrupt status bit for List register <n>:
2330 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2331 // maintenance interrupt.
2332 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2333 // interrupt that has not been handled.
2334 //
2335 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2336 // of the following are true:
2337 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2338 // - ICH_LR<n>_EL2.HW is 0.
2339 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2340
2341 uint64_t value = 0;
2342
2343 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2344 ICH_LR_EL2 ich_lr_el2 =
2345 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2346
2347 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2348 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2349 value |= (1 << lr_idx);
2350 }
2351 }
2352
2353 return value;
2354}
2355
2356Gicv3CPUInterface::ICH_MISR_EL2
2357Gicv3CPUInterface::maintenanceInterruptStatus() const
2358{
2359 // Comments are copied from SPEC section 9.4.7 (ID012119)
2360 ICH_MISR_EL2 ich_misr_el2 = 0;
2361 ICH_HCR_EL2 ich_hcr_el2 =
2362 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2363 ICH_VMCR_EL2 ich_vmcr_el2 =
2364 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2365
2366 // End Of Interrupt. [bit 0]
2367 // This maintenance interrupt is asserted when at least one bit in
2368 // ICH_EISR_EL2 is 1.
2369
2370 if (eoiMaintenanceInterruptStatus()) {
2371 ich_misr_el2.EOI = 1;
2372 }
2373
2374 // Underflow. [bit 1]
2375 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2376 // zero or one of the List register entries are marked as a valid
2377 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2378 // do not equal 0x0.
2379 uint32_t num_valid_interrupts = 0;
2380 uint32_t num_pending_interrupts = 0;
2381
2382 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2383 ICH_LR_EL2 ich_lr_el2 =
2384 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2385
2386 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2387 num_valid_interrupts++;
2388 }
2389
2390 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2391 num_pending_interrupts++;
2392 }
2393 }
2394
2395 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2396 ich_misr_el2.U = 1;
2397 }
2398
2399 // List Register Entry Not Present. [bit 2]
2400 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2401 // and ICH_HCR_EL2.EOIcount is non-zero.
2402 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2403 ich_misr_el2.LRENP = 1;
2404 }
2405
2406 // No Pending. [bit 3]
2407 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2408 // no List register is in pending state.
2409 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2410 ich_misr_el2.NP = 1;
2411 }
2412
2413 // vPE Group 0 Enabled. [bit 4]
2414 // This maintenance interrupt is asserted when
2415 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2416 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2417 ich_misr_el2.VGrp0E = 1;
2418 }
2419
2420 // vPE Group 0 Disabled. [bit 5]
2421 // This maintenance interrupt is asserted when
2422 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2423 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2424 ich_misr_el2.VGrp0D = 1;
2425 }
2426
2427 // vPE Group 1 Enabled. [bit 6]
2428 // This maintenance interrupt is asserted when
2429 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2430 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2431 ich_misr_el2.VGrp1E = 1;
2432 }
2433
2434 // vPE Group 1 Disabled. [bit 7]
2435 // This maintenance interrupt is asserted when
2436 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2437 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2438 ich_misr_el2.VGrp1D = 1;
2439 }
2440
2441 return ich_misr_el2;
2442}
2443
2444void
2445Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2446{
2447 SERIALIZE_SCALAR(hppi.intid);
2448 SERIALIZE_SCALAR(hppi.prio);
2449 SERIALIZE_ENUM(hppi.group);
2450}
2451
2452void
2453Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2454{
2455 UNSERIALIZE_SCALAR(hppi.intid);
2456 UNSERIALIZE_SCALAR(hppi.prio);
2457 UNSERIALIZE_ENUM(hppi.group);
2458}
| 1818 }
1819}
1820
1821void
1822Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1823{
1824 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1825 lr_idx);
1826
1827 if (ich_lr_el2.HW) {
1828 // Deactivate the associated physical interrupt
1829 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1830 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1831 distributor->getIntGroup(ich_lr_el2.pINTID) :
1832 redistributor->getIntGroup(ich_lr_el2.pINTID);
1833 deactivateIRQ(ich_lr_el2.pINTID, group);
1834 }
1835 }
1836
1837 // Remove the active bit
1838 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1839 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1840}
1841
1842/*
1843 * Returns the priority group field for the current BPR value for the group.
1844 * GroupBits() Pseudocode from spec.
1845 */
1846uint32_t
1847Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
1848{
1849 ICC_CTLR_EL1 icc_ctlr_el1_s =
1850 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1851 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1852 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1853
1854 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1855 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1856 group = Gicv3::G0S;
1857 }
1858
1859 int bpr;
1860
1861 if (group == Gicv3::G0S) {
1862 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
1863 } else {
1864 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
1865 }
1866
1867 if (group == Gicv3::G1NS) {
1868 assert(bpr > 0);
1869 bpr--;
1870 }
1871
1872 return ~0U << (bpr + 1);
1873}
1874
1875uint32_t
1876Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1877{
1878 ICH_VMCR_EL2 ich_vmcr_el2 =
1879 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1880
1881 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1882 group = Gicv3::G0S;
1883 }
1884
1885 int bpr;
1886
1887 if (group == Gicv3::G0S) {
1888 bpr = ich_vmcr_el2.VBPR0;
1889 } else {
1890 bpr = ich_vmcr_el2.VBPR1;
1891 }
1892
1893 if (group == Gicv3::G1NS) {
1894 assert(bpr > 0);
1895 bpr--;
1896 }
1897
1898 return ~0U << (bpr + 1);
1899}
1900
1901bool
1902Gicv3CPUInterface::isEOISplitMode() const
1903{
1904 if (isEL3OrMon()) {
1905 ICC_CTLR_EL3 icc_ctlr_el3 =
1906 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1907 return icc_ctlr_el3.EOImode_EL3;
1908 } else {
1909 ICC_CTLR_EL1 icc_ctlr_el1 =
1910 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1911 return icc_ctlr_el1.EOImode;
1912 }
1913}
1914
1915bool
1916Gicv3CPUInterface::virtualIsEOISplitMode() const
1917{
1918 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1919 return ich_vmcr_el2.VEOIM;
1920}
1921
1922int
1923Gicv3CPUInterface::highestActiveGroup() const
1924{
1925 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1926 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
1927 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
1928
1929 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
1930 return Gicv3::G1NS;
1931 }
1932
1933 if (gq_ctz < g0_ctz) {
1934 return Gicv3::G1S;
1935 }
1936
1937 if (g0_ctz < 32) {
1938 return Gicv3::G0S;
1939 }
1940
1941 return -1;
1942}
1943
1944void
1945Gicv3CPUInterface::update()
1946{
1947 bool signal_IRQ = false;
1948 bool signal_FIQ = false;
1949
1950 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
1951 /*
1952 * Secure enabled GIC sending a G1S IRQ to a secure disabled
1953 * CPU -> send G0 IRQ
1954 */
1955 hppi.group = Gicv3::G0S;
1956 }
1957
1958 if (hppiCanPreempt()) {
1959 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
1960 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
1961 "posting int as %d!\n", int_type);
1962 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
1963 }
1964
1965 if (signal_IRQ) {
1966 gic->postInt(cpuId, ArmISA::INT_IRQ);
1967 } else {
1968 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
1969 }
1970
1971 if (signal_FIQ) {
1972 gic->postInt(cpuId, ArmISA::INT_FIQ);
1973 } else {
1974 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
1975 }
1976}
1977
1978void
1979Gicv3CPUInterface::virtualUpdate()
1980{
1981 bool signal_IRQ = false;
1982 bool signal_FIQ = false;
1983 int lr_idx = getHPPVILR();
1984
1985 if (lr_idx >= 0) {
1986 ICH_LR_EL2 ich_lr_el2 =
1987 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1988
1989 if (hppviCanPreempt(lr_idx)) {
1990 if (ich_lr_el2.Group) {
1991 signal_IRQ = true;
1992 } else {
1993 signal_FIQ = true;
1994 }
1995 }
1996 }
1997
1998 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1999
2000 if (ich_hcr_el2.En) {
2001 if (maintenanceInterruptStatus()) {
2002 maintenanceInterrupt->raise();
2003 }
2004 }
2005
2006 if (signal_IRQ) {
2007 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2008 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2009 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2010 } else {
2011 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2012 }
2013
2014 if (signal_FIQ) {
2015 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2016 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2017 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2018 } else {
2019 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2020 }
2021}
2022
2023// Returns the index of the LR with the HPPI
2024int
2025Gicv3CPUInterface::getHPPVILR() const
2026{
2027 int idx = -1;
2028 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2029
2030 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2031 // VG0 and VG1 disabled...
2032 return idx;
2033 }
2034
2035 uint8_t highest_prio = 0xff;
2036
2037 for (int i = 0; i < 16; i++) {
2038 ICH_LR_EL2 ich_lr_el2 =
2039 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2040
2041 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2042 continue;
2043 }
2044
2045 if (ich_lr_el2.Group) {
2046 // VG1
2047 if (!ich_vmcr_el2.VENG1) {
2048 continue;
2049 }
2050 } else {
2051 // VG0
2052 if (!ich_vmcr_el2.VENG0) {
2053 continue;
2054 }
2055 }
2056
2057 uint8_t prio = ich_lr_el2.Priority;
2058
2059 if (prio < highest_prio) {
2060 highest_prio = prio;
2061 idx = i;
2062 }
2063 }
2064
2065 return idx;
2066}
2067
2068bool
2069Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2070{
2071 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2072 if (!ich_hcr_el2.En) {
2073 // virtual interface is disabled
2074 return false;
2075 }
2076
2077 ICH_LR_EL2 ich_lr_el2 =
2078 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2079 uint8_t prio = ich_lr_el2.Priority;
2080 uint8_t vpmr =
2081 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2082
2083 if (prio >= vpmr) {
2084 // prioriry masked
2085 return false;
2086 }
2087
2088 uint8_t rprio = virtualHighestActivePriority();
2089
2090 if (rprio == 0xff) {
2091 return true;
2092 }
2093
2094 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2095 uint32_t prio_mask = virtualGroupPriorityMask(group);
2096
2097 if ((prio & prio_mask) < (rprio & prio_mask)) {
2098 return true;
2099 }
2100
2101 return false;
2102}
2103
2104uint8_t
2105Gicv3CPUInterface::virtualHighestActivePriority() const
2106{
2107 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2108
2109 for (int i = 0; i < num_aprs; i++) {
2110 RegVal vapr =
2111 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2112 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2113
2114 if (!vapr) {
2115 continue;
2116 }
2117
2118 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2119 }
2120
2121 // no active interrups, return idle priority
2122 return 0xff;
2123}
2124
2125void
2126Gicv3CPUInterface::virtualIncrementEOICount()
2127{
2128 // Increment the EOICOUNT field in ICH_HCR_EL2
2129 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2130 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2131 EOI_cout++;
2132 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2133 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2134}
2135
2136// spec section 4.6.2
2137ArmISA::InterruptTypes
2138Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2139{
2140 bool is_fiq = false;
2141
2142 switch (group) {
2143 case Gicv3::G0S:
2144 is_fiq = true;
2145 break;
2146
2147 case Gicv3::G1S:
2148 is_fiq = (distributor->DS == 0) &&
2149 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2150 break;
2151
2152 case Gicv3::G1NS:
2153 is_fiq = (distributor->DS == 0) && inSecureState();
2154 break;
2155
2156 default:
2157 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2158 }
2159
2160 if (is_fiq) {
2161 return ArmISA::INT_FIQ;
2162 } else {
2163 return ArmISA::INT_IRQ;
2164 }
2165}
2166
2167bool
2168Gicv3CPUInterface::hppiCanPreempt() const
2169{
2170 if (hppi.prio == 0xff) {
2171 // there is no pending interrupt
2172 return false;
2173 }
2174
2175 if (!groupEnabled(hppi.group)) {
2176 // group disabled at CPU interface
2177 return false;
2178 }
2179
2180 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2181 // priority masked
2182 return false;
2183 }
2184
2185 uint8_t rprio = highestActivePriority();
2186
2187 if (rprio == 0xff) {
2188 return true;
2189 }
2190
2191 uint32_t prio_mask = groupPriorityMask(hppi.group);
2192
2193 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2194 return true;
2195 }
2196
2197 return false;
2198}
2199
2200uint8_t
2201Gicv3CPUInterface::highestActivePriority() const
2202{
2203 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2204 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2205 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2206
2207 if (apr) {
2208 return ctz32(apr) << (GIC_MIN_BPR + 1);
2209 }
2210
2211 // no active interrups, return idle priority
2212 return 0xff;
2213}
2214
2215bool
2216Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2217{
2218 switch (group) {
2219 case Gicv3::G0S: {
2220 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2221 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2222 return icc_igrpen0_el1.Enable;
2223 }
2224
2225 case Gicv3::G1S: {
2226 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2227 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2228 return icc_igrpen1_el1_s.Enable;
2229 }
2230
2231 case Gicv3::G1NS: {
2232 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2233 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2234 return icc_igrpen1_el1_ns.Enable;
2235 }
2236
2237 default:
2238 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2239 }
2240}
2241
2242bool
2243Gicv3CPUInterface::inSecureState() const
2244{
2245 if (!gic->getSystem()->haveSecurity()) {
2246 return false;
2247 }
2248
2249 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2250 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2251 return ArmISA::inSecureState(scr, cpsr);
2252}
2253
2254int
2255Gicv3CPUInterface::currEL() const
2256{
2257 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2258 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2259
2260 if (is_64) {
2261 return (ExceptionLevel)(uint8_t) cpsr.el;
2262 } else {
2263 switch (cpsr.mode) {
2264 case MODE_USER:
2265 return 0;
2266
2267 case MODE_HYP:
2268 return 2;
2269
2270 case MODE_MON:
2271 return 3;
2272
2273 default:
2274 return 1;
2275 }
2276 }
2277}
2278
2279bool
2280Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2281{
2282 switch (el) {
2283 case EL0:
2284 case EL1:
2285 return true;
2286
2287 case EL2:
2288 return gic->getSystem()->haveVirtualization();
2289
2290 case EL3:
2291 return gic->getSystem()->haveSecurity();
2292
2293 default:
2294 warn("Unimplemented Exception Level\n");
2295 return false;
2296 }
2297}
2298
2299bool
2300Gicv3CPUInterface::isSecureBelowEL3() const
2301{
2302 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2303 return haveEL(EL3) && scr.ns == 0;
2304}
2305
2306bool
2307Gicv3CPUInterface::isAA64() const
2308{
2309 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2310 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2311}
2312
2313bool
2314Gicv3CPUInterface::isEL3OrMon() const
2315{
2316 if (haveEL(EL3)) {
2317 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2318 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2319
2320 if (is_64 && (cpsr.el == EL3)) {
2321 return true;
2322 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2323 return true;
2324 }
2325 }
2326
2327 return false;
2328}
2329
2330// Computes ICH_EISR_EL2
2331uint64_t
2332Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2333{
2334 // ICH_EISR_EL2
2335 // Bits [63:16] - RES0
2336 // Status<n>, bit [n], for n = 0 to 15
2337 // EOI maintenance interrupt status bit for List register <n>:
2338 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2339 // maintenance interrupt.
2340 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2341 // interrupt that has not been handled.
2342 //
2343 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2344 // of the following are true:
2345 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2346 // - ICH_LR<n>_EL2.HW is 0.
2347 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2348
2349 uint64_t value = 0;
2350
2351 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2352 ICH_LR_EL2 ich_lr_el2 =
2353 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2354
2355 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2356 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2357 value |= (1 << lr_idx);
2358 }
2359 }
2360
2361 return value;
2362}
2363
2364Gicv3CPUInterface::ICH_MISR_EL2
2365Gicv3CPUInterface::maintenanceInterruptStatus() const
2366{
2367 // Comments are copied from SPEC section 9.4.7 (ID012119)
2368 ICH_MISR_EL2 ich_misr_el2 = 0;
2369 ICH_HCR_EL2 ich_hcr_el2 =
2370 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2371 ICH_VMCR_EL2 ich_vmcr_el2 =
2372 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2373
2374 // End Of Interrupt. [bit 0]
2375 // This maintenance interrupt is asserted when at least one bit in
2376 // ICH_EISR_EL2 is 1.
2377
2378 if (eoiMaintenanceInterruptStatus()) {
2379 ich_misr_el2.EOI = 1;
2380 }
2381
2382 // Underflow. [bit 1]
2383 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2384 // zero or one of the List register entries are marked as a valid
2385 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2386 // do not equal 0x0.
2387 uint32_t num_valid_interrupts = 0;
2388 uint32_t num_pending_interrupts = 0;
2389
2390 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2391 ICH_LR_EL2 ich_lr_el2 =
2392 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2393
2394 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2395 num_valid_interrupts++;
2396 }
2397
2398 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2399 num_pending_interrupts++;
2400 }
2401 }
2402
2403 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2404 ich_misr_el2.U = 1;
2405 }
2406
2407 // List Register Entry Not Present. [bit 2]
2408 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2409 // and ICH_HCR_EL2.EOIcount is non-zero.
2410 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2411 ich_misr_el2.LRENP = 1;
2412 }
2413
2414 // No Pending. [bit 3]
2415 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2416 // no List register is in pending state.
2417 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2418 ich_misr_el2.NP = 1;
2419 }
2420
2421 // vPE Group 0 Enabled. [bit 4]
2422 // This maintenance interrupt is asserted when
2423 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2424 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2425 ich_misr_el2.VGrp0E = 1;
2426 }
2427
2428 // vPE Group 0 Disabled. [bit 5]
2429 // This maintenance interrupt is asserted when
2430 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2431 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2432 ich_misr_el2.VGrp0D = 1;
2433 }
2434
2435 // vPE Group 1 Enabled. [bit 6]
2436 // This maintenance interrupt is asserted when
2437 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2438 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2439 ich_misr_el2.VGrp1E = 1;
2440 }
2441
2442 // vPE Group 1 Disabled. [bit 7]
2443 // This maintenance interrupt is asserted when
2444 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2445 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2446 ich_misr_el2.VGrp1D = 1;
2447 }
2448
2449 return ich_misr_el2;
2450}
2451
2452void
2453Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2454{
2455 SERIALIZE_SCALAR(hppi.intid);
2456 SERIALIZE_SCALAR(hppi.prio);
2457 SERIALIZE_ENUM(hppi.group);
2458}
2459
2460void
2461Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2462{
2463 UNSERIALIZE_SCALAR(hppi.intid);
2464 UNSERIALIZE_SCALAR(hppi.prio);
2465 UNSERIALIZE_ENUM(hppi.group);
2466}
|