1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
40 : BaseISADevice(),
41 gic(gic),
42 redistributor(nullptr),
43 distributor(nullptr),
44 cpuId(cpu_id)
45{
46}
47
48void
49Gicv3CPUInterface::init()
50{
51 redistributor = gic->getRedistributor(cpuId);
52 distributor = gic->getDistributor();
53}
54
55void
56Gicv3CPUInterface::initState()
57{
58 reset();
59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
| 1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
40 : BaseISADevice(),
41 gic(gic),
42 redistributor(nullptr),
43 distributor(nullptr),
44 cpuId(cpu_id)
45{
46}
47
48void
49Gicv3CPUInterface::init()
50{
51 redistributor = gic->getRedistributor(cpuId);
52 distributor = gic->getDistributor();
53}
54
55void
56Gicv3CPUInterface::initState()
57{
58 reset();
59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
|
67bool
68Gicv3CPUInterface::getHCREL2FMO() const
69{
70 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
71
72 if (hcr.tge && hcr.e2h) {
73 return false;
74 } else if (hcr.tge) {
75 return true;
76 } else {
77 return hcr.fmo;
78 }
79}
80
81bool
82Gicv3CPUInterface::getHCREL2IMO() const
83{
84 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
85
86 if (hcr.tge && hcr.e2h) {
87 return false;
88 } else if (hcr.tge) {
89 return true;
90 } else {
91 return hcr.imo;
92 }
93}
94
95RegVal
96Gicv3CPUInterface::readMiscReg(int misc_reg)
97{
98 RegVal value = isa->readMiscRegNoEffect(misc_reg);
99 bool hcr_fmo = getHCREL2FMO();
100 bool hcr_imo = getHCREL2IMO();
101
102 switch (misc_reg) {
103 // Active Priorities Group 1 Registers
104 case MISCREG_ICC_AP1R0:
105 case MISCREG_ICC_AP1R0_EL1: {
106 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
107 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
108 }
109
110 break;
111 }
112
113 case MISCREG_ICC_AP1R1:
114 case MISCREG_ICC_AP1R1_EL1:
115
116 // only implemented if supporting 6 or more bits of priority
117 case MISCREG_ICC_AP1R2:
118 case MISCREG_ICC_AP1R2_EL1:
119
120 // only implemented if supporting 7 or more bits of priority
121 case MISCREG_ICC_AP1R3:
122 case MISCREG_ICC_AP1R3_EL1:
123 // only implemented if supporting 7 or more bits of priority
124 return 0;
125
126 // Active Priorities Group 0 Registers
127 case MISCREG_ICC_AP0R0:
128 case MISCREG_ICC_AP0R0_EL1: {
129 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
130 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
131 }
132
133 break;
134 }
135
136 case MISCREG_ICC_AP0R1:
137 case MISCREG_ICC_AP0R1_EL1:
138
139 // only implemented if supporting 6 or more bits of priority
140 case MISCREG_ICC_AP0R2:
141 case MISCREG_ICC_AP0R2_EL1:
142
143 // only implemented if supporting 7 or more bits of priority
144 case MISCREG_ICC_AP0R3:
145 case MISCREG_ICC_AP0R3_EL1:
146 // only implemented if supporting 7 or more bits of priority
147 return 0;
148
149 // Interrupt Group 0 Enable register EL1
150 case MISCREG_ICC_IGRPEN0:
151 case MISCREG_ICC_IGRPEN0_EL1: {
152 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
153 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
154 }
155
156 break;
157 }
158
159 // Interrupt Group 1 Enable register EL1
160 case MISCREG_ICC_IGRPEN1:
161 case MISCREG_ICC_IGRPEN1_EL1: {
162 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
163 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
164 }
165
166 break;
167 }
168
169 // Interrupt Group 1 Enable register EL3
170 case MISCREG_ICC_MGRPEN1:
171 case MISCREG_ICC_IGRPEN1_EL3:
172 break;
173
174 // Running Priority Register
175 case MISCREG_ICC_RPR:
176 case MISCREG_ICC_RPR_EL1: {
177 if ((currEL() == EL1) && !inSecureState() &&
178 (hcr_imo || hcr_fmo)) {
179 return readMiscReg(MISCREG_ICV_RPR_EL1);
180 }
181
182 uint8_t rprio = highestActivePriority();
183
184 if (haveEL(EL3) && !inSecureState() &&
185 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
186 // Spec section 4.8.1
187 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
188 if ((rprio & 0x80) == 0) {
189 // If the current priority mask value is in the range of
190 // 0x00-0x7F a read access returns the value 0x0
191 rprio = 0;
192 } else if (rprio != 0xff) {
193 // If the current priority mask value is in the range of
194 // 0x80-0xFF a read access returns the Non-secure read of
195 // the current value
196 rprio = (rprio << 1) & 0xff;
197 }
198 }
199
200 value = rprio;
201 break;
202 }
203
204 // Virtual Running Priority Register
205 case MISCREG_ICV_RPR_EL1: {
206 value = virtualHighestActivePriority();
207 break;
208 }
209
210 // Highest Priority Pending Interrupt Register 0
211 case MISCREG_ICC_HPPIR0:
212 case MISCREG_ICC_HPPIR0_EL1: {
213 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
214 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
215 }
216
217 value = getHPPIR0();
218 break;
219 }
220
221 // Virtual Highest Priority Pending Interrupt Register 0
222 case MISCREG_ICV_HPPIR0_EL1: {
223 value = Gicv3::INTID_SPURIOUS;
224 int lr_idx = getHPPVILR();
225
226 if (lr_idx >= 0) {
227 ICH_LR_EL2 ich_lr_el2 =
228 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
229 Gicv3::GroupId group =
230 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
231
232 if (group == Gicv3::G0S) {
233 value = ich_lr_el2.vINTID;
234 }
235 }
236
237 break;
238 }
239
240 // Highest Priority Pending Interrupt Register 1
241 case MISCREG_ICC_HPPIR1:
242 case MISCREG_ICC_HPPIR1_EL1: {
243 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
244 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
245 }
246
247 value = getHPPIR1();
248 break;
249 }
250
251 // Virtual Highest Priority Pending Interrupt Register 1
252 case MISCREG_ICV_HPPIR1_EL1: {
253 value = Gicv3::INTID_SPURIOUS;
254 int lr_idx = getHPPVILR();
255
256 if (lr_idx >= 0) {
257 ICH_LR_EL2 ich_lr_el2 =
258 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
259 Gicv3::GroupId group =
260 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
261
262 if (group == Gicv3::G1NS) {
263 value = ich_lr_el2.vINTID;
264 }
265 }
266
267 break;
268 }
269
270 // Binary Point Register 0
271 case MISCREG_ICC_BPR0:
272 case MISCREG_ICC_BPR0_EL1:
273 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
274 return readMiscReg(MISCREG_ICV_BPR0_EL1);
275 }
276
277 M5_FALLTHROUGH;
278
279 // Binary Point Register 1
280 case MISCREG_ICC_BPR1:
281 case MISCREG_ICC_BPR1_EL1: {
282 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
283 return readMiscReg(MISCREG_ICV_BPR1_EL1);
284 }
285
286 Gicv3::GroupId group =
287 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
288
289 if (group == Gicv3::G1S && !inSecureState()) {
290 group = Gicv3::G1NS;
291 }
292
293 ICC_CTLR_EL1 icc_ctlr_el1_s =
294 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
295
296 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
297 icc_ctlr_el1_s.CBPR) {
298 group = Gicv3::G0S;
299 }
300
301 bool sat_inc = false;
302
303 ICC_CTLR_EL1 icc_ctlr_el1_ns =
304 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
305
306 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
307 icc_ctlr_el1_ns.CBPR) {
308 // Reads return BPR0 + 1 saturated to 7, WI
309 group = Gicv3::G0S;
310 sat_inc = true;
311 }
312
313 uint8_t bpr;
314
315 if (group == Gicv3::G0S) {
316 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
317 } else {
318 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
319 }
320
321 if (sat_inc) {
322 bpr++;
323
324 if (bpr > 7) {
325 bpr = 7;
326 }
327 }
328
329 value = bpr;
330 break;
331 }
332
333 // Virtual Binary Point Register 1
334 case MISCREG_ICV_BPR0_EL1:
335 case MISCREG_ICV_BPR1_EL1: {
336 Gicv3::GroupId group =
337 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
338 ICH_VMCR_EL2 ich_vmcr_el2 =
339 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
340 bool sat_inc = false;
341
342 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
343 // bpr0 + 1 saturated to 7, WI
344 group = Gicv3::G0S;
345 sat_inc = true;
346 }
347
348 uint8_t vbpr;
349
350 if (group == Gicv3::G0S) {
351 vbpr = ich_vmcr_el2.VBPR0;
352 } else {
353 vbpr = ich_vmcr_el2.VBPR1;
354 }
355
356 if (sat_inc) {
357 vbpr++;
358
359 if (vbpr > 7) {
360 vbpr = 7;
361 }
362 }
363
364 value = vbpr;
365 break;
366 }
367
368 // Interrupt Priority Mask Register
369 case MISCREG_ICC_PMR:
370 case MISCREG_ICC_PMR_EL1:
371 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
372 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
373 }
374
375 if (haveEL(EL3) && !inSecureState() &&
376 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
377 // Spec section 4.8.1
378 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
379 if ((value & 0x80) == 0) {
380 // If the current priority mask value is in the range of
381 // 0x00-0x7F a read access returns the value 0x00.
382 value = 0;
383 } else if (value != 0xff) {
384 // If the current priority mask value is in the range of
385 // 0x80-0xFF a read access returns the Non-secure read of the
386 // current value.
387 value = (value << 1) & 0xff;
388 }
389 }
390
391 break;
392
393 // Interrupt Acknowledge Register 0
394 case MISCREG_ICC_IAR0:
395 case MISCREG_ICC_IAR0_EL1: {
396 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
397 return readMiscReg(MISCREG_ICV_IAR0_EL1);
398 }
399
400 uint32_t int_id;
401
402 if (hppiCanPreempt()) {
403 int_id = getHPPIR0();
404
405 // avoid activation for special interrupts
406 if (int_id < Gicv3::INTID_SECURE) {
407 activateIRQ(int_id, hppi.group);
408 }
409 } else {
410 int_id = Gicv3::INTID_SPURIOUS;
411 }
412
413 value = int_id;
414 break;
415 }
416
417 // Virtual Interrupt Acknowledge Register 0
418 case MISCREG_ICV_IAR0_EL1: {
419 int lr_idx = getHPPVILR();
420 uint32_t int_id = Gicv3::INTID_SPURIOUS;
421
422 if (lr_idx >= 0) {
423 ICH_LR_EL2 ich_lr_el2 =
424 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
425
426 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
427 int_id = ich_lr_el2.vINTID;
428
429 if (int_id < Gicv3::INTID_SECURE ||
430 int_id > Gicv3::INTID_SPURIOUS) {
431 virtualActivateIRQ(lr_idx);
432 } else {
433 // Bogus... Pseudocode says:
434 // - Move from pending to invalid...
435 // - Return de bogus id...
436 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
437 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
438 ich_lr_el2);
439 }
440 }
441 }
442
443 value = int_id;
444 virtualUpdate();
445 break;
446 }
447
448 // Interrupt Acknowledge Register 1
449 case MISCREG_ICC_IAR1:
450 case MISCREG_ICC_IAR1_EL1: {
451 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
452 return readMiscReg(MISCREG_ICV_IAR1_EL1);
453 }
454
455 uint32_t int_id;
456
457 if (hppiCanPreempt()) {
458 int_id = getHPPIR1();
459
460 // avoid activation for special interrupts
461 if (int_id < Gicv3::INTID_SECURE) {
462 activateIRQ(int_id, hppi.group);
463 }
464 } else {
465 int_id = Gicv3::INTID_SPURIOUS;
466 }
467
468 value = int_id;
469 break;
470 }
471
472 // Virtual Interrupt Acknowledge Register 1
473 case MISCREG_ICV_IAR1_EL1: {
474 int lr_idx = getHPPVILR();
475 uint32_t int_id = Gicv3::INTID_SPURIOUS;
476
477 if (lr_idx >= 0) {
478 ICH_LR_EL2 ich_lr_el2 =
479 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
480
481 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
482 int_id = ich_lr_el2.vINTID;
483
484 if (int_id < Gicv3::INTID_SECURE ||
485 int_id > Gicv3::INTID_SPURIOUS) {
486 virtualActivateIRQ(lr_idx);
487 } else {
488 // Bogus... Pseudocode says:
489 // - Move from pending to invalid...
490 // - Return de bogus id...
491 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
492 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
493 ich_lr_el2);
494 }
495 }
496 }
497
498 value = int_id;
499 virtualUpdate();
500 break;
501 }
502
503 // System Register Enable Register EL1
504 case MISCREG_ICC_SRE:
505 case MISCREG_ICC_SRE_EL1: {
506 /*
507 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
508 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
509 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
510 */
511 ICC_SRE_EL1 icc_sre_el1 = 0;
512 icc_sre_el1.SRE = 1;
513 icc_sre_el1.DIB = 1;
514 icc_sre_el1.DFB = 1;
515 value = icc_sre_el1;
516 break;
517 }
518
519 // System Register Enable Register EL2
520 case MISCREG_ICC_HSRE:
521 case MISCREG_ICC_SRE_EL2: {
522 /*
523 * Enable [3] == 1
524 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
525 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
526 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
527 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
528 */
529 ICC_SRE_EL2 icc_sre_el2 = 0;
530 icc_sre_el2.SRE = 1;
531 icc_sre_el2.DIB = 1;
532 icc_sre_el2.DFB = 1;
533 icc_sre_el2.Enable = 1;
534 value = icc_sre_el2;
535 break;
536 }
537
538 // System Register Enable Register EL3
539 case MISCREG_ICC_MSRE:
540 case MISCREG_ICC_SRE_EL3: {
541 /*
542 * Enable [3] == 1
543 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
544 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
545 * RAO/WI)
546 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
547 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
548 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
549 */
550 ICC_SRE_EL3 icc_sre_el3 = 0;
551 icc_sre_el3.SRE = 1;
552 icc_sre_el3.DIB = 1;
553 icc_sre_el3.DFB = 1;
554 icc_sre_el3.Enable = 1;
555 value = icc_sre_el3;
556 break;
557 }
558
559 // Control Register
560 case MISCREG_ICC_CTLR:
561 case MISCREG_ICC_CTLR_EL1: {
562 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
563 return readMiscReg(MISCREG_ICV_CTLR_EL1);
564 }
565
566 // Enforce value for RO bits
567 // ExtRange [19], INTIDs in the range 1024..8191 not supported
568 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
569 // A3V [15], supports non-zero values of the Aff3 field in SGI
570 // generation System registers
571 // SEIS [14], does not support generation of SEIs (deprecated)
572 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
573 // PRIbits [10:8], number of priority bits implemented, minus one
574 ICC_CTLR_EL1 icc_ctlr_el1 = value;
575 icc_ctlr_el1.ExtRange = 0;
576 icc_ctlr_el1.RSS = 1;
577 icc_ctlr_el1.A3V = 1;
578 icc_ctlr_el1.SEIS = 0;
579 icc_ctlr_el1.IDbits = 1;
580 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
581 value = icc_ctlr_el1;
582 break;
583 }
584
585 // Virtual Control Register
586 case MISCREG_ICV_CTLR_EL1: {
587 ICV_CTLR_EL1 icv_ctlr_el1 = value;
588 icv_ctlr_el1.RSS = 0;
589 icv_ctlr_el1.A3V = 1;
590 icv_ctlr_el1.SEIS = 0;
591 icv_ctlr_el1.IDbits = 1;
592 icv_ctlr_el1.PRIbits = 7;
593 value = icv_ctlr_el1;
594 break;
595 }
596
597 // Control Register
598 case MISCREG_ICC_MCTLR:
599 case MISCREG_ICC_CTLR_EL3: {
600 // Enforce value for RO bits
601 // ExtRange [19], INTIDs in the range 1024..8191 not supported
602 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
603 // nDS [17], supports disabling of security
604 // A3V [15], supports non-zero values of the Aff3 field in SGI
605 // generation System registers
606 // SEIS [14], does not support generation of SEIs (deprecated)
607 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
608 // PRIbits [10:8], number of priority bits implemented, minus one
609 ICC_CTLR_EL3 icc_ctlr_el3 = value;
610 icc_ctlr_el3.ExtRange = 0;
611 icc_ctlr_el3.RSS = 1;
612 icc_ctlr_el3.nDS = 0;
613 icc_ctlr_el3.A3V = 1;
614 icc_ctlr_el3.SEIS = 0;
615 icc_ctlr_el3.IDbits = 0;
616 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
617 value = icc_ctlr_el3;
618 break;
619 }
620
621 // Hyp Control Register
622 case MISCREG_ICH_HCR:
623 case MISCREG_ICH_HCR_EL2:
624 break;
625
626 // Hyp Active Priorities Group 0 Registers
627 case MISCREG_ICH_AP0R0:
628 case MISCREG_ICH_AP0R0_EL2:
629 break;
630
631 // Hyp Active Priorities Group 1 Registers
632 case MISCREG_ICH_AP1R0:
633 case MISCREG_ICH_AP1R0_EL2:
634 break;
635
636 // Maintenance Interrupt State Register
637 case MISCREG_ICH_MISR:
638 case MISCREG_ICH_MISR_EL2:
639 value = maintenanceInterruptStatus();
640 break;
641
642 // VGIC Type Register
643 case MISCREG_ICH_VTR:
644 case MISCREG_ICH_VTR_EL2: {
645 ICH_VTR_EL2 ich_vtr_el2 = value;
646
647 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
648 ich_vtr_el2.A3V = 1;
649 ich_vtr_el2.IDbits = 1;
650 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
651 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
652
653 value = ich_vtr_el2;
654 break;
655 }
656
657 // End of Interrupt Status Register
658 case MISCREG_ICH_EISR:
659 case MISCREG_ICH_EISR_EL2:
660 value = eoiMaintenanceInterruptStatus();
661 break;
662
663 // Empty List Register Status Register
664 case MISCREG_ICH_ELRSR:
665 case MISCREG_ICH_ELRSR_EL2:
666 value = 0;
667
668 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
669 ICH_LR_EL2 ich_lr_el2 =
670 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
671
672 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
673 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
674 value |= (1 << lr_idx);
675 }
676 }
677
678 break;
679
680 // List Registers
681 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
682 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
683 value = value >> 32;
684 break;
685
686 // List Registers
687 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
688 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
689 value = value & 0xffffffff;
690 break;
691
692 // List Registers
693 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
694 break;
695
696 // Virtual Machine Control Register
697 case MISCREG_ICH_VMCR:
698 case MISCREG_ICH_VMCR_EL2:
699 break;
700
701 default:
702 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
703 misc_reg, miscRegName[misc_reg]);
704 }
705
706 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
707 miscRegName[misc_reg], value);
708 return value;
709}
710
711void
712Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
713{
714 bool do_virtual_update = false;
715 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
716 miscRegName[misc_reg], val);
717 bool hcr_fmo = getHCREL2FMO();
718 bool hcr_imo = getHCREL2IMO();
719
720 switch (misc_reg) {
721 // Active Priorities Group 1 Registers
722 case MISCREG_ICC_AP1R0:
723 case MISCREG_ICC_AP1R0_EL1:
724 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
725 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
726 }
727
728 break;
729
730 case MISCREG_ICC_AP1R1:
731 case MISCREG_ICC_AP1R1_EL1:
732
733 // only implemented if supporting 6 or more bits of priority
734 case MISCREG_ICC_AP1R2:
735 case MISCREG_ICC_AP1R2_EL1:
736
737 // only implemented if supporting 7 or more bits of priority
738 case MISCREG_ICC_AP1R3:
739 case MISCREG_ICC_AP1R3_EL1:
740 // only implemented if supporting 7 or more bits of priority
741 break;
742
743 // Active Priorities Group 0 Registers
744 case MISCREG_ICC_AP0R0:
745 case MISCREG_ICC_AP0R0_EL1:
746 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
747 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
748 }
749
750 break;
751
752 case MISCREG_ICC_AP0R1:
753 case MISCREG_ICC_AP0R1_EL1:
754
755 // only implemented if supporting 6 or more bits of priority
756 case MISCREG_ICC_AP0R2:
757 case MISCREG_ICC_AP0R2_EL1:
758
759 // only implemented if supporting 7 or more bits of priority
760 case MISCREG_ICC_AP0R3:
761 case MISCREG_ICC_AP0R3_EL1:
762 // only implemented if supporting 7 or more bits of priority
763 break;
764
765 // End Of Interrupt Register 0
766 case MISCREG_ICC_EOIR0:
767 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
768 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
769 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
770 }
771
772 int int_id = val & 0xffffff;
773
774 // avoid activation for special interrupts
775 if (int_id >= Gicv3::INTID_SECURE) {
776 return;
777 }
778
779 Gicv3::GroupId group = Gicv3::G0S;
780
781 if (highestActiveGroup() != group) {
782 return;
783 }
784
785 dropPriority(group);
786
787 if (!isEOISplitMode()) {
788 deactivateIRQ(int_id, group);
789 }
790
791 break;
792 }
793
794 // Virtual End Of Interrupt Register 0
795 case MISCREG_ICV_EOIR0_EL1: {
796 int int_id = val & 0xffffff;
797
798 // avoid deactivation for special interrupts
799 if (int_id >= Gicv3::INTID_SECURE &&
800 int_id <= Gicv3::INTID_SPURIOUS) {
801 return;
802 }
803
804 uint8_t drop_prio = virtualDropPriority();
805
806 if (drop_prio == 0xff) {
807 return;
808 }
809
810 int lr_idx = virtualFindActive(int_id);
811
812 if (lr_idx < 0) {
813 // No LR found matching
814 virtualIncrementEOICount();
815 } else {
816 ICH_LR_EL2 ich_lr_el2 =
817 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
818 Gicv3::GroupId lr_group =
819 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
820 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
821
822 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
823 //if (!virtualIsEOISplitMode())
824 {
825 virtualDeactivateIRQ(lr_idx);
826 }
827 }
828 }
829
830 virtualUpdate();
831 break;
832 }
833
834 // End Of Interrupt Register 1
835 case MISCREG_ICC_EOIR1:
836 case MISCREG_ICC_EOIR1_EL1: {
837 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
838 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
839 }
840
841 int int_id = val & 0xffffff;
842
843 // avoid deactivation for special interrupts
844 if (int_id >= Gicv3::INTID_SECURE) {
845 return;
846 }
847
848 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
849
850 if (highestActiveGroup() == Gicv3::G0S) {
851 return;
852 }
853
854 if (distributor->DS == 0) {
855 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
856 return;
857 } else if (highestActiveGroup() == Gicv3::G1NS &&
858 !(!inSecureState() or (currEL() == EL3))) {
859 return;
860 }
861 }
862
863 dropPriority(group);
864
865 if (!isEOISplitMode()) {
866 deactivateIRQ(int_id, group);
867 }
868
869 break;
870 }
871
872 // Virtual End Of Interrupt Register 1
873 case MISCREG_ICV_EOIR1_EL1: {
874 int int_id = val & 0xffffff;
875
876 // avoid deactivation for special interrupts
877 if (int_id >= Gicv3::INTID_SECURE &&
878 int_id <= Gicv3::INTID_SPURIOUS) {
879 return;
880 }
881
882 uint8_t drop_prio = virtualDropPriority();
883
884 if (drop_prio == 0xff) {
885 return;
886 }
887
888 int lr_idx = virtualFindActive(int_id);
889
890 if (lr_idx < 0) {
891 // No matching LR found
892 virtualIncrementEOICount();
893 } else {
894 ICH_LR_EL2 ich_lr_el2 =
895 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
896 Gicv3::GroupId lr_group =
897 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
898 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
899
900 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
901 if (!virtualIsEOISplitMode()) {
902 virtualDeactivateIRQ(lr_idx);
903 }
904 }
905 }
906
907 virtualUpdate();
908 break;
909 }
910
911 // Deactivate Interrupt Register
912 case MISCREG_ICC_DIR:
913 case MISCREG_ICC_DIR_EL1: {
914 if ((currEL() == EL1) && !inSecureState() &&
915 (hcr_imo || hcr_fmo)) {
916 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
917 }
918
919 int int_id = val & 0xffffff;
920
921 // The following checks are as per spec pseudocode
922 // aarch64/support/ICC_DIR_EL1
923
924 // Check for spurious ID
925 if (int_id >= Gicv3::INTID_SECURE) {
926 return;
927 }
928
929 // EOI mode is not set, so don't deactivate
930 if (!isEOISplitMode()) {
931 return;
932 }
933
934 Gicv3::GroupId group =
935 int_id >= 32 ? distributor->getIntGroup(int_id) :
936 redistributor->getIntGroup(int_id);
937 bool irq_is_grp0 = group == Gicv3::G0S;
938 bool single_sec_state = distributor->DS;
939 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
940 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
941 bool route_fiq_to_el3 = scr_el3.fiq;
942 bool route_irq_to_el3 = scr_el3.irq;
943 bool route_fiq_to_el2 = hcr_fmo;
944 bool route_irq_to_el2 = hcr_imo;
945
946 switch (currEL()) {
947 case EL3:
948 break;
949
950 case EL2:
951 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
952 break;
953 }
954
955 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
956 break;
957 }
958
959 return;
960
961 case EL1:
962 if (!isSecureBelowEL3()) {
963 if (single_sec_state && irq_is_grp0 &&
964 !route_fiq_to_el3 && !route_fiq_to_el2) {
965 break;
966 }
967
968 if (!irq_is_secure && !irq_is_grp0 &&
969 !route_irq_to_el3 && !route_irq_to_el2) {
970 break;
971 }
972 } else {
973 if (irq_is_grp0 && !route_fiq_to_el3) {
974 break;
975 }
976
977 if (!irq_is_grp0 &&
978 (!irq_is_secure || !single_sec_state) &&
979 !route_irq_to_el3) {
980 break;
981 }
982 }
983
984 return;
985
986 default:
987 break;
988 }
989
990 deactivateIRQ(int_id, group);
991 break;
992 }
993
994 // Deactivate Virtual Interrupt Register
995 case MISCREG_ICV_DIR_EL1: {
996 int int_id = val & 0xffffff;
997
998 // avoid deactivation for special interrupts
999 if (int_id >= Gicv3::INTID_SECURE &&
1000 int_id <= Gicv3::INTID_SPURIOUS) {
1001 return;
1002 }
1003
1004 if (!virtualIsEOISplitMode()) {
1005 return;
1006 }
1007
1008 int lr_idx = virtualFindActive(int_id);
1009
1010 if (lr_idx < 0) {
1011 // No matching LR found
1012 virtualIncrementEOICount();
1013 } else {
1014 virtualDeactivateIRQ(lr_idx);
1015 }
1016
1017 virtualUpdate();
1018 break;
1019 }
1020
1021 // Binary Point Register 0
1022 case MISCREG_ICC_BPR0:
1023 case MISCREG_ICC_BPR0_EL1:
1024 // Binary Point Register 1
1025 case MISCREG_ICC_BPR1:
1026 case MISCREG_ICC_BPR1_EL1: {
1027 if ((currEL() == EL1) && !inSecureState()) {
1028 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1029 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1030 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1031 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1032 }
1033 }
1034
1035 Gicv3::GroupId group =
1036 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1037
1038 if (group == Gicv3::G1S && !inSecureState()) {
1039 group = Gicv3::G1NS;
1040 }
1041
1042 ICC_CTLR_EL1 icc_ctlr_el1_s =
1043 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1044
1045 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1046 icc_ctlr_el1_s.CBPR) {
1047 group = Gicv3::G0S;
1048 }
1049
1050 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1051 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1052
1053 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1054 icc_ctlr_el1_ns.CBPR) {
1055 // BPR0 + 1 saturated to 7, WI
1056 return;
1057 }
1058
1059 uint8_t min_val = (group == Gicv3::G1NS) ?
1060 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1061 val &= 0x7;
1062
1063 if (val < min_val) {
1064 val = min_val;
1065 }
1066
1067 break;
1068 }
1069
1070 // Virtual Binary Point Register 0
1071 case MISCREG_ICV_BPR0_EL1:
1072 // Virtual Binary Point Register 1
1073 case MISCREG_ICV_BPR1_EL1: {
1074 Gicv3::GroupId group =
1075 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1076 ICH_VMCR_EL2 ich_vmcr_el2 =
1077 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1078
1079 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1080 // BPR0 + 1 saturated to 7, WI
1081 return;
1082 }
1083
1084 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1085
1086 if (group != Gicv3::G0S) {
1087 min_VPBR++;
1088 }
1089
1090 if (val < min_VPBR) {
1091 val = min_VPBR;
1092 }
1093
1094 if (group == Gicv3::G0S) {
1095 ich_vmcr_el2.VBPR0 = val;
1096 } else {
1097 ich_vmcr_el2.VBPR1 = val;
1098 }
1099
1100 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1101 do_virtual_update = true;
1102 break;
1103 }
1104
1105 // Control Register EL1
1106 case MISCREG_ICC_CTLR:
1107 case MISCREG_ICC_CTLR_EL1: {
1108 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1109 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1110 }
1111
1112 /*
1113 * ExtRange is RO.
1114 * RSS is RO.
1115 * A3V is RO.
1116 * SEIS is RO.
1117 * IDbits is RO.
1118 * PRIbits is RO.
1119 */
1120 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1121 ICC_CTLR_EL1 icc_ctlr_el1 =
1122 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1123
1124 ICC_CTLR_EL3 icc_ctlr_el3 =
1125 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1126
1127 // The following could be refactored but it is following
1128 // spec description section 9.2.6 point by point.
1129
1130 // PMHE
1131 if (haveEL(EL3)) {
1132 // PMHE is alias of ICC_CTLR_EL3.PMHE
1133
1134 if (distributor->DS == 0) {
1135 // PMHE is RO
1136 } else if (distributor->DS == 1) {
1137 // PMHE is RW
1138 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1139 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1140 }
1141 } else {
1142 // PMHE is RW (by implementation choice)
1143 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1144 }
1145
1146 // EOImode
1147 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1148
1149 if (inSecureState()) {
1150 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1151 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1152 } else {
1153 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1154 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1155 }
1156
1157 // CBPR
1158 if (haveEL(EL3)) {
1159 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1160
1161 if (distributor->DS == 0) {
1162 // CBPR is RO
1163 } else {
1164 // CBPR is RW
1165 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1166
1167 if (inSecureState()) {
1168 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1169 } else {
1170 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1171 }
1172 }
1173 } else {
1174 // CBPR is RW
1175 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1176 }
1177
1178 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1179
1180 val = icc_ctlr_el1;
1181 break;
1182 }
1183
1184 // Virtual Control Register
1185 case MISCREG_ICV_CTLR_EL1: {
1186 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1187 ICV_CTLR_EL1 icv_ctlr_el1 =
1188 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1189 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1190 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1191 val = icv_ctlr_el1;
1192
1193 // Aliases
1194 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1195 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1196 ICH_VMCR_EL2 ich_vmcr_el2 =
1197 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1198 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1199 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1200 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1201 break;
1202 }
1203
1204 // Control Register EL3
1205 case MISCREG_ICC_MCTLR:
1206 case MISCREG_ICC_CTLR_EL3: {
1207 /*
1208 * ExtRange is RO.
1209 * RSS is RO.
1210 * nDS is RO.
1211 * A3V is RO.
1212 * SEIS is RO.
1213 * IDbits is RO.
1214 * PRIbits is RO.
1215 * PMHE is RAO/WI, priority-based routing is always used.
1216 */
1217 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1218
1219 // Aliases
1220 if (haveEL(EL3))
1221 {
1222 ICC_CTLR_EL1 icc_ctlr_el1_s =
1223 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1224 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1225 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1226
1227 // ICC_CTLR_EL1(NS).EOImode is an alias of
1228 // ICC_CTLR_EL3.EOImode_EL1NS
1229 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1230 // ICC_CTLR_EL1(S).EOImode is an alias of
1231 // ICC_CTLR_EL3.EOImode_EL1S
1232 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1233 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1234 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1235 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1236 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1237
1238 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1239 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1240 icc_ctlr_el1_ns);
1241 }
1242
1243 ICC_CTLR_EL3 icc_ctlr_el3 =
1244 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1245
1246 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1247 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1248 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1249 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1250 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1251 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1252
1253 val = icc_ctlr_el3;
1254 break;
1255 }
1256
1257 // Priority Mask Register
1258 case MISCREG_ICC_PMR:
1259 case MISCREG_ICC_PMR_EL1: {
1260 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1261 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1262 }
1263
1264 val &= 0xff;
1265 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1266
1267 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1268 // Spec section 4.8.1
1269 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1270 RegVal old_icc_pmr_el1 =
1271 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1272
1273 if (!(old_icc_pmr_el1 & 0x80)) {
1274 // If the current priority mask value is in the range of
1275 // 0x00-0x7F then WI
1276 return;
1277 }
1278
1279 // If the current priority mask value is in the range of
1280 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1281 // based on the Non-secure read of the priority mask value
1282 // written to the register.
1283
1284 val = (val >> 1) | 0x80;
1285 }
1286
1287 val &= ~0U << (8 - PRIORITY_BITS);
1288 break;
1289 }
1290
1291 // Interrupt Group 0 Enable Register EL1
1292 case MISCREG_ICC_IGRPEN0:
1293 case MISCREG_ICC_IGRPEN0_EL1: {
1294 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1295 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1296 }
1297
1298 break;
1299 }
1300
1301 // Virtual Interrupt Group 0 Enable register
1302 case MISCREG_ICV_IGRPEN0_EL1: {
1303 bool enable = val & 0x1;
1304 ICH_VMCR_EL2 ich_vmcr_el2 =
1305 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1306 ich_vmcr_el2.VENG0 = enable;
1307 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1308 virtualUpdate();
1309 return;
1310 }
1311
1312 // Interrupt Group 1 Enable register EL1
1313 case MISCREG_ICC_IGRPEN1:
1314 case MISCREG_ICC_IGRPEN1_EL1: {
1315 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1316 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1317 }
1318
1319 if (haveEL(EL3)) {
1320 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1321 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1322 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1323
1324 if (inSecureState()) {
1325 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1326 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1327 } else {
1328 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1329 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1330 }
1331
1332 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1333 icc_igrpen1_el3);
1334 }
1335
1336 break;
1337 }
1338
1339 // Virtual Interrupt Group 1 Enable register
1340 case MISCREG_ICV_IGRPEN1_EL1: {
1341 bool enable = val & 0x1;
1342 ICH_VMCR_EL2 ich_vmcr_el2 =
1343 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1344 ich_vmcr_el2.VENG1 = enable;
1345 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1346 virtualUpdate();
1347 return;
1348 }
1349
1350 // Interrupt Group 1 Enable register
1351 case MISCREG_ICC_MGRPEN1:
1352 case MISCREG_ICC_IGRPEN1_EL3: {
1353 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1354 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1355 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1356
1357 if (inSecureState()) {
1358 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1359 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1360 } else {
1361 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1362 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1363 }
1364
1365 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1366 break;
1367 }
1368
1369 // Software Generated Interrupt Group 0 Register
1370 case MISCREG_ICC_SGI0R:
1371 case MISCREG_ICC_SGI0R_EL1:
1372
1373 // Software Generated Interrupt Group 1 Register
1374 case MISCREG_ICC_SGI1R:
1375 case MISCREG_ICC_SGI1R_EL1:
1376
1377 // Alias Software Generated Interrupt Group 1 Register
1378 case MISCREG_ICC_ASGI1R:
1379 case MISCREG_ICC_ASGI1R_EL1: {
1380 bool ns = !inSecureState();
1381 Gicv3::GroupId group;
1382
1383 if (misc_reg == MISCREG_ICC_SGI1R_EL1) {
1384 group = ns ? Gicv3::G1NS : Gicv3::G1S;
1385 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) {
1386 group = ns ? Gicv3::G1S : Gicv3::G1NS;
1387 } else {
1388 group = Gicv3::G0S;
1389 }
1390
1391 if (distributor->DS && group == Gicv3::G1S) {
1392 group = Gicv3::G0S;
1393 }
1394
1395 uint8_t aff3 = bits(val, 55, 48);
1396 uint8_t aff2 = bits(val, 39, 32);
1397 uint8_t aff1 = bits(val, 23, 16);;
1398 uint16_t target_list = bits(val, 15, 0);
1399 uint32_t int_id = bits(val, 27, 24);
1400 bool irm = bits(val, 40, 40);
1401 uint8_t rs = bits(val, 47, 44);
1402
1403 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1404 Gicv3Redistributor * redistributor_i =
1405 gic->getRedistributor(i);
1406 uint32_t affinity_i = redistributor_i->getAffinity();
1407
1408 if (irm) {
1409 // Interrupts routed to all PEs in the system,
1410 // excluding "self"
1411 if (affinity_i == redistributor->getAffinity()) {
1412 continue;
1413 }
1414 } else {
1415 // Interrupts routed to the PEs specified by
1416 // Aff3.Aff2.Aff1.<target list>
1417 if ((affinity_i >> 8) !=
1418 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1419 continue;
1420 }
1421
1422 uint8_t aff0_i = bits(affinity_i, 7, 0);
1423
1424 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1425 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1426 continue;
1427 }
1428 }
1429
1430 redistributor_i->sendSGI(int_id, group, ns);
1431 }
1432
1433 break;
1434 }
1435
1436 // System Register Enable Register EL1
1437 case MISCREG_ICC_SRE:
1438 case MISCREG_ICC_SRE_EL1:
1439 // System Register Enable Register EL2
1440 case MISCREG_ICC_HSRE:
1441 case MISCREG_ICC_SRE_EL2:
1442 // System Register Enable Register EL3
1443 case MISCREG_ICC_MSRE:
1444 case MISCREG_ICC_SRE_EL3:
1445 // All bits are RAO/WI
1446 return;
1447
1448 // Hyp Control Register
1449 case MISCREG_ICH_HCR:
1450 case MISCREG_ICH_HCR_EL2: {
1451 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1452 ICH_HCR_EL2 ich_hcr_el2 =
1453 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1454
1455 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1456 {
1457 // EOIcount - Permitted behaviors are:
1458 // - Increment EOIcount.
1459 // - Leave EOIcount unchanged.
1460 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1461 }
1462
1463 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1464 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1465 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1466 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1467 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1468 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1469 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1470 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1471 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1472 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1473 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1474 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1475 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1476 val = ich_hcr_el2;
1477 do_virtual_update = true;
1478 break;
1479 }
1480
1481 // List Registers
1482 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1483 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1484 ICH_LRC requested_ich_lrc = val;
1485 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1486
1487 ich_lrc.State = requested_ich_lrc.State;
1488 ich_lrc.HW = requested_ich_lrc.HW;
1489 ich_lrc.Group = requested_ich_lrc.Group;
1490
1491 // Priority, bits [23:16]
1492 // At least five bits must be implemented.
1493 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1494 // We implement 5 bits.
1495 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1496 (ich_lrc.Priority & 0x07);
1497
1498 // pINTID, bits [12:0]
1499 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1500 // - Bits[12:10] : RES0.
1501 // - Bit[9] : EOI.
1502 // - Bits[8:0] : RES0.
1503 // When ICH_LR<n>.HW is 1:
1504 // - This field is only required to implement enough bits to hold a
1505 // valid value for the implemented INTID size. Any unused higher
1506 // order bits are RES0.
1507 if (requested_ich_lrc.HW == 0) {
1508 ich_lrc.EOI = requested_ich_lrc.EOI;
1509 } else {
1510 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1511 }
1512
1513 val = ich_lrc;
1514 do_virtual_update = true;
1515 break;
1516 }
1517
1518 // List Registers
1519 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1520 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1521 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1522 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1523 do_virtual_update = true;
1524 break;
1525 }
1526
1527 // List Registers
1528 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1529 ICH_LR_EL2 requested_ich_lr_el2 = val;
1530 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1531
1532 ich_lr_el2.State = requested_ich_lr_el2.State;
1533 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1534 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1535
1536 // Priority, bits [55:48]
1537 // At least five bits must be implemented.
1538 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1539 // We implement 5 bits.
1540 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1541 (ich_lr_el2.Priority & 0x07);
1542
1543 // pINTID, bits [44:32]
1544 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1545 // - Bits[44:42] : RES0.
1546 // - Bit[41] : EOI.
1547 // - Bits[40:32] : RES0.
1548 // When ICH_LR<n>_EL2.HW is 1:
1549 // - This field is only required to implement enough bits to hold a
1550 // valid value for the implemented INTID size. Any unused higher
1551 // order bits are RES0.
1552 if (requested_ich_lr_el2.HW == 0) {
1553 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1554 } else {
1555 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1556 }
1557
1558 // vINTID, bits [31:0]
1559 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1560 // though at least 16 bits must be implemented.
1561 // Unimplemented bits are RES0.
1562 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1563
1564 val = ich_lr_el2;
1565 do_virtual_update = true;
1566 break;
1567 }
1568
1569 // Virtual Machine Control Register
1570 case MISCREG_ICH_VMCR:
1571 case MISCREG_ICH_VMCR_EL2: {
1572 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1573 ICH_VMCR_EL2 ich_vmcr_el2 =
1574 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1575 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1576 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1577
1578 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1579 ich_vmcr_el2.VBPR0 = min_vpr0;
1580 } else {
1581 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1582 }
1583
1584 uint8_t min_vpr1 = min_vpr0 + 1;
1585
1586 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1587 ich_vmcr_el2.VBPR1 = min_vpr1;
1588 } else {
1589 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1590 }
1591
1592 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1593 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1594 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1595 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1596 val = ich_vmcr_el2;
1597 break;
1598 }
1599
1600 // Hyp Active Priorities Group 0 Registers
1601 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1602 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1603 // Hyp Active Priorities Group 1 Registers
1604 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1605 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1606 break;
1607
1608 default:
1609 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1610 misc_reg, miscRegName[misc_reg]);
1611 }
1612
1613 isa->setMiscRegNoEffect(misc_reg, val);
1614
1615 if (do_virtual_update) {
1616 virtualUpdate();
1617 }
1618}
1619
1620int
1621Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1622{
1623 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1624 ICH_LR_EL2 ich_lr_el2 =
1625 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1626
1627 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1628 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1629 (ich_lr_el2.vINTID == int_id)) {
1630 return lr_idx;
1631 }
1632 }
1633
1634 return -1;
1635}
1636
1637uint32_t
1638Gicv3CPUInterface::getHPPIR0() const
1639{
1640 if (hppi.prio == 0xff) {
1641 return Gicv3::INTID_SPURIOUS;
1642 }
1643
1644 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1645
1646 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1647 // interrupt for the other state pending
1648 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1649 }
1650
1651 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1652 return Gicv3::INTID_SPURIOUS;
1653 }
1654
1655 if (irq_is_secure && !inSecureState()) {
1656 // Secure interrupts not visible in Non-secure
1657 return Gicv3::INTID_SPURIOUS;
1658 }
1659
1660 return hppi.intid;
1661}
1662
1663uint32_t
1664Gicv3CPUInterface::getHPPIR1() const
1665{
1666 if (hppi.prio == 0xff) {
1667 return Gicv3::INTID_SPURIOUS;
1668 }
1669
1670 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1671 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1672 if (hppi.group == Gicv3::G0S) {
1673 return Gicv3::INTID_SECURE;
1674 } else if (hppi.group == Gicv3::G1NS) {
1675 return Gicv3::INTID_NONSECURE;
1676 }
1677 }
1678
1679 if (hppi.group == Gicv3::G0S) {
1680 return Gicv3::INTID_SPURIOUS;
1681 }
1682
1683 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1684
1685 if (irq_is_secure) {
1686 if (!inSecureState()) {
1687 // Secure interrupts not visible in Non-secure
1688 return Gicv3::INTID_SPURIOUS;
1689 }
1690 } else if (!isEL3OrMon() && inSecureState()) {
1691 // Group 1 non-secure interrupts not visible in Secure EL1
1692 return Gicv3::INTID_SPURIOUS;
1693 }
1694
1695 return hppi.intid;
1696}
1697
1698void
1699Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1700{
1701 int apr_misc_reg;
1702 RegVal apr;
1703 apr_misc_reg = group == Gicv3::G0S ?
1704 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1705 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1706
1707 if (apr) {
1708 apr &= apr - 1;
1709 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1710 }
1711
1712 update();
1713}
1714
1715uint8_t
1716Gicv3CPUInterface::virtualDropPriority()
1717{
1718 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1719
1720 for (int i = 0; i < apr_max; i++) {
1721 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1722 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1723
1724 if (!vapr0 && !vapr1) {
1725 continue;
1726 }
1727
1728 int vapr0_count = ctz32(vapr0);
1729 int vapr1_count = ctz32(vapr1);
1730
1731 if (vapr0_count <= vapr1_count) {
1732 vapr0 &= vapr0 - 1;
1733 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1734 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1735 } else {
1736 vapr1 &= vapr1 - 1;
1737 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1738 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1739 }
1740 }
1741
1742 return 0xff;
1743}
1744
1745void
1746Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1747{
1748 // Update active priority registers.
1749 uint32_t prio = hppi.prio & 0xf8;
1750 int apr_bit = prio >> (8 - PRIORITY_BITS);
1751 int reg_bit = apr_bit % 32;
1752 int apr_idx = group == Gicv3::G0S ?
1753 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1754 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1755 apr |= (1 << reg_bit);
1756 isa->setMiscRegNoEffect(apr_idx, apr);
1757
1758 // Move interrupt state from pending to active.
1759 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1760 // SGI or PPI, redistributor
1761 redistributor->activateIRQ(int_id);
1762 redistributor->updateAndInformCPUInterface();
1763 } else if (int_id < Gicv3::INTID_SECURE) {
1764 // SPI, distributor
1765 distributor->activateIRQ(int_id);
1766 distributor->updateAndInformCPUInterfaces();
1767 }
1768}
1769
1770void
1771Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1772{
1773 // Update active priority registers.
1774 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1775 lr_idx);
1776 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1777 uint8_t prio = ich_lr_el.Priority & 0xf8;
1778 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1779 int reg_no = apr_bit / 32;
1780 int reg_bit = apr_bit % 32;
1781 int apr_idx = group == Gicv3::G0S ?
1782 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1783 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1784 apr |= (1 << reg_bit);
1785 isa->setMiscRegNoEffect(apr_idx, apr);
1786 // Move interrupt state from pending to active.
1787 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1788 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1789}
1790
1791void
1792Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1793{
1794 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1795 // SGI or PPI, redistributor
1796 redistributor->deactivateIRQ(int_id);
1797 redistributor->updateAndInformCPUInterface();
1798 } else if (int_id < Gicv3::INTID_SECURE) {
1799 // SPI, distributor
1800 distributor->deactivateIRQ(int_id);
1801 distributor->updateAndInformCPUInterfaces();
1802 } else {
1803 return;
1804 }
1805}
1806
1807void
1808Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1809{
1810 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1811 lr_idx);
1812
1813 if (ich_lr_el2.HW) {
1814 // Deactivate the associated physical interrupt
1815 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1816 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1817 distributor->getIntGroup(ich_lr_el2.pINTID) :
1818 redistributor->getIntGroup(ich_lr_el2.pINTID);
1819 deactivateIRQ(ich_lr_el2.pINTID, group);
1820 }
1821 }
1822
1823 // Remove the active bit
1824 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1825 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1826}
1827
1828/*
1829 * Returns the priority group field for the current BPR value for the group.
1830 * GroupBits() Pseudocode from spec.
1831 */
1832uint32_t
1833Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
1834{
1835 ICC_CTLR_EL1 icc_ctlr_el1_s =
1836 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1837 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1838 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1839
1840 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1841 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1842 group = Gicv3::G0S;
1843 }
1844
1845 int bpr;
1846
1847 if (group == Gicv3::G0S) {
1848 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
1849 } else {
1850 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
1851 }
1852
1853 if (group == Gicv3::G1NS) {
1854 assert(bpr > 0);
1855 bpr--;
1856 }
1857
1858 return ~0U << (bpr + 1);
1859}
1860
1861uint32_t
1862Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1863{
1864 ICH_VMCR_EL2 ich_vmcr_el2 =
1865 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1866
1867 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1868 group = Gicv3::G0S;
1869 }
1870
1871 int bpr;
1872
1873 if (group == Gicv3::G0S) {
1874 bpr = ich_vmcr_el2.VBPR0;
1875 } else {
1876 bpr = ich_vmcr_el2.VBPR1;
1877 }
1878
1879 if (group == Gicv3::G1NS) {
1880 assert(bpr > 0);
1881 bpr--;
1882 }
1883
1884 return ~0U << (bpr + 1);
1885}
1886
1887bool
1888Gicv3CPUInterface::isEOISplitMode() const
1889{
1890 if (isEL3OrMon()) {
1891 ICC_CTLR_EL3 icc_ctlr_el3 =
1892 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1893 return icc_ctlr_el3.EOImode_EL3;
1894 } else {
1895 ICC_CTLR_EL1 icc_ctlr_el1 =
1896 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1897 return icc_ctlr_el1.EOImode;
1898 }
1899}
1900
1901bool
1902Gicv3CPUInterface::virtualIsEOISplitMode() const
1903{
1904 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1905 return ich_vmcr_el2.VEOIM;
1906}
1907
1908int
1909Gicv3CPUInterface::highestActiveGroup() const
1910{
1911 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1912 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
1913 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
1914
1915 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
1916 return Gicv3::G1NS;
1917 }
1918
1919 if (gq_ctz < g0_ctz) {
1920 return Gicv3::G1S;
1921 }
1922
1923 if (g0_ctz < 32) {
1924 return Gicv3::G0S;
1925 }
1926
1927 return -1;
1928}
1929
1930void
1931Gicv3CPUInterface::update()
1932{
1933 bool signal_IRQ = false;
1934 bool signal_FIQ = false;
1935
1936 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
1937 /*
1938 * Secure enabled GIC sending a G1S IRQ to a secure disabled
1939 * CPU -> send G0 IRQ
1940 */
1941 hppi.group = Gicv3::G0S;
1942 }
1943
1944 if (hppiCanPreempt()) {
1945 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
1946 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
1947 "posting int as %d!\n", int_type);
1948 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
1949 }
1950
1951 if (signal_IRQ) {
1952 gic->postInt(cpuId, ArmISA::INT_IRQ);
1953 } else {
1954 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
1955 }
1956
1957 if (signal_FIQ) {
1958 gic->postInt(cpuId, ArmISA::INT_FIQ);
1959 } else {
1960 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
1961 }
1962}
1963
1964void
1965Gicv3CPUInterface::virtualUpdate()
1966{
1967 bool signal_IRQ = false;
1968 bool signal_FIQ = false;
1969 int lr_idx = getHPPVILR();
1970
1971 if (lr_idx >= 0) {
1972 ICH_LR_EL2 ich_lr_el2 =
1973 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1974
1975 if (hppviCanPreempt(lr_idx)) {
1976 if (ich_lr_el2.Group) {
1977 signal_IRQ = true;
1978 } else {
1979 signal_FIQ = true;
1980 }
1981 }
1982 }
1983
1984 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1985
1986 if (ich_hcr_el2.En) {
1987 if (maintenanceInterruptStatus()) {
| 73bool
74Gicv3CPUInterface::getHCREL2FMO() const
75{
76 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
77
78 if (hcr.tge && hcr.e2h) {
79 return false;
80 } else if (hcr.tge) {
81 return true;
82 } else {
83 return hcr.fmo;
84 }
85}
86
87bool
88Gicv3CPUInterface::getHCREL2IMO() const
89{
90 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
91
92 if (hcr.tge && hcr.e2h) {
93 return false;
94 } else if (hcr.tge) {
95 return true;
96 } else {
97 return hcr.imo;
98 }
99}
100
101RegVal
102Gicv3CPUInterface::readMiscReg(int misc_reg)
103{
104 RegVal value = isa->readMiscRegNoEffect(misc_reg);
105 bool hcr_fmo = getHCREL2FMO();
106 bool hcr_imo = getHCREL2IMO();
107
108 switch (misc_reg) {
109 // Active Priorities Group 1 Registers
110 case MISCREG_ICC_AP1R0:
111 case MISCREG_ICC_AP1R0_EL1: {
112 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
113 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
114 }
115
116 break;
117 }
118
119 case MISCREG_ICC_AP1R1:
120 case MISCREG_ICC_AP1R1_EL1:
121
122 // only implemented if supporting 6 or more bits of priority
123 case MISCREG_ICC_AP1R2:
124 case MISCREG_ICC_AP1R2_EL1:
125
126 // only implemented if supporting 7 or more bits of priority
127 case MISCREG_ICC_AP1R3:
128 case MISCREG_ICC_AP1R3_EL1:
129 // only implemented if supporting 7 or more bits of priority
130 return 0;
131
132 // Active Priorities Group 0 Registers
133 case MISCREG_ICC_AP0R0:
134 case MISCREG_ICC_AP0R0_EL1: {
135 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
136 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
137 }
138
139 break;
140 }
141
142 case MISCREG_ICC_AP0R1:
143 case MISCREG_ICC_AP0R1_EL1:
144
145 // only implemented if supporting 6 or more bits of priority
146 case MISCREG_ICC_AP0R2:
147 case MISCREG_ICC_AP0R2_EL1:
148
149 // only implemented if supporting 7 or more bits of priority
150 case MISCREG_ICC_AP0R3:
151 case MISCREG_ICC_AP0R3_EL1:
152 // only implemented if supporting 7 or more bits of priority
153 return 0;
154
155 // Interrupt Group 0 Enable register EL1
156 case MISCREG_ICC_IGRPEN0:
157 case MISCREG_ICC_IGRPEN0_EL1: {
158 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
159 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
160 }
161
162 break;
163 }
164
165 // Interrupt Group 1 Enable register EL1
166 case MISCREG_ICC_IGRPEN1:
167 case MISCREG_ICC_IGRPEN1_EL1: {
168 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
169 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
170 }
171
172 break;
173 }
174
175 // Interrupt Group 1 Enable register EL3
176 case MISCREG_ICC_MGRPEN1:
177 case MISCREG_ICC_IGRPEN1_EL3:
178 break;
179
180 // Running Priority Register
181 case MISCREG_ICC_RPR:
182 case MISCREG_ICC_RPR_EL1: {
183 if ((currEL() == EL1) && !inSecureState() &&
184 (hcr_imo || hcr_fmo)) {
185 return readMiscReg(MISCREG_ICV_RPR_EL1);
186 }
187
188 uint8_t rprio = highestActivePriority();
189
190 if (haveEL(EL3) && !inSecureState() &&
191 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
192 // Spec section 4.8.1
193 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
194 if ((rprio & 0x80) == 0) {
195 // If the current priority mask value is in the range of
196 // 0x00-0x7F a read access returns the value 0x0
197 rprio = 0;
198 } else if (rprio != 0xff) {
199 // If the current priority mask value is in the range of
200 // 0x80-0xFF a read access returns the Non-secure read of
201 // the current value
202 rprio = (rprio << 1) & 0xff;
203 }
204 }
205
206 value = rprio;
207 break;
208 }
209
210 // Virtual Running Priority Register
211 case MISCREG_ICV_RPR_EL1: {
212 value = virtualHighestActivePriority();
213 break;
214 }
215
216 // Highest Priority Pending Interrupt Register 0
217 case MISCREG_ICC_HPPIR0:
218 case MISCREG_ICC_HPPIR0_EL1: {
219 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
220 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
221 }
222
223 value = getHPPIR0();
224 break;
225 }
226
227 // Virtual Highest Priority Pending Interrupt Register 0
228 case MISCREG_ICV_HPPIR0_EL1: {
229 value = Gicv3::INTID_SPURIOUS;
230 int lr_idx = getHPPVILR();
231
232 if (lr_idx >= 0) {
233 ICH_LR_EL2 ich_lr_el2 =
234 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
235 Gicv3::GroupId group =
236 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
237
238 if (group == Gicv3::G0S) {
239 value = ich_lr_el2.vINTID;
240 }
241 }
242
243 break;
244 }
245
246 // Highest Priority Pending Interrupt Register 1
247 case MISCREG_ICC_HPPIR1:
248 case MISCREG_ICC_HPPIR1_EL1: {
249 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
250 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
251 }
252
253 value = getHPPIR1();
254 break;
255 }
256
257 // Virtual Highest Priority Pending Interrupt Register 1
258 case MISCREG_ICV_HPPIR1_EL1: {
259 value = Gicv3::INTID_SPURIOUS;
260 int lr_idx = getHPPVILR();
261
262 if (lr_idx >= 0) {
263 ICH_LR_EL2 ich_lr_el2 =
264 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
265 Gicv3::GroupId group =
266 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
267
268 if (group == Gicv3::G1NS) {
269 value = ich_lr_el2.vINTID;
270 }
271 }
272
273 break;
274 }
275
276 // Binary Point Register 0
277 case MISCREG_ICC_BPR0:
278 case MISCREG_ICC_BPR0_EL1:
279 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
280 return readMiscReg(MISCREG_ICV_BPR0_EL1);
281 }
282
283 M5_FALLTHROUGH;
284
285 // Binary Point Register 1
286 case MISCREG_ICC_BPR1:
287 case MISCREG_ICC_BPR1_EL1: {
288 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
289 return readMiscReg(MISCREG_ICV_BPR1_EL1);
290 }
291
292 Gicv3::GroupId group =
293 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
294
295 if (group == Gicv3::G1S && !inSecureState()) {
296 group = Gicv3::G1NS;
297 }
298
299 ICC_CTLR_EL1 icc_ctlr_el1_s =
300 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
301
302 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
303 icc_ctlr_el1_s.CBPR) {
304 group = Gicv3::G0S;
305 }
306
307 bool sat_inc = false;
308
309 ICC_CTLR_EL1 icc_ctlr_el1_ns =
310 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
311
312 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
313 icc_ctlr_el1_ns.CBPR) {
314 // Reads return BPR0 + 1 saturated to 7, WI
315 group = Gicv3::G0S;
316 sat_inc = true;
317 }
318
319 uint8_t bpr;
320
321 if (group == Gicv3::G0S) {
322 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
323 } else {
324 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
325 }
326
327 if (sat_inc) {
328 bpr++;
329
330 if (bpr > 7) {
331 bpr = 7;
332 }
333 }
334
335 value = bpr;
336 break;
337 }
338
339 // Virtual Binary Point Register 1
340 case MISCREG_ICV_BPR0_EL1:
341 case MISCREG_ICV_BPR1_EL1: {
342 Gicv3::GroupId group =
343 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
344 ICH_VMCR_EL2 ich_vmcr_el2 =
345 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
346 bool sat_inc = false;
347
348 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
349 // bpr0 + 1 saturated to 7, WI
350 group = Gicv3::G0S;
351 sat_inc = true;
352 }
353
354 uint8_t vbpr;
355
356 if (group == Gicv3::G0S) {
357 vbpr = ich_vmcr_el2.VBPR0;
358 } else {
359 vbpr = ich_vmcr_el2.VBPR1;
360 }
361
362 if (sat_inc) {
363 vbpr++;
364
365 if (vbpr > 7) {
366 vbpr = 7;
367 }
368 }
369
370 value = vbpr;
371 break;
372 }
373
374 // Interrupt Priority Mask Register
375 case MISCREG_ICC_PMR:
376 case MISCREG_ICC_PMR_EL1:
377 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
378 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
379 }
380
381 if (haveEL(EL3) && !inSecureState() &&
382 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
383 // Spec section 4.8.1
384 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
385 if ((value & 0x80) == 0) {
386 // If the current priority mask value is in the range of
387 // 0x00-0x7F a read access returns the value 0x00.
388 value = 0;
389 } else if (value != 0xff) {
390 // If the current priority mask value is in the range of
391 // 0x80-0xFF a read access returns the Non-secure read of the
392 // current value.
393 value = (value << 1) & 0xff;
394 }
395 }
396
397 break;
398
399 // Interrupt Acknowledge Register 0
400 case MISCREG_ICC_IAR0:
401 case MISCREG_ICC_IAR0_EL1: {
402 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
403 return readMiscReg(MISCREG_ICV_IAR0_EL1);
404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
412 if (int_id < Gicv3::INTID_SECURE) {
413 activateIRQ(int_id, hppi.group);
414 }
415 } else {
416 int_id = Gicv3::INTID_SPURIOUS;
417 }
418
419 value = int_id;
420 break;
421 }
422
423 // Virtual Interrupt Acknowledge Register 0
424 case MISCREG_ICV_IAR0_EL1: {
425 int lr_idx = getHPPVILR();
426 uint32_t int_id = Gicv3::INTID_SPURIOUS;
427
428 if (lr_idx >= 0) {
429 ICH_LR_EL2 ich_lr_el2 =
430 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
431
432 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
433 int_id = ich_lr_el2.vINTID;
434
435 if (int_id < Gicv3::INTID_SECURE ||
436 int_id > Gicv3::INTID_SPURIOUS) {
437 virtualActivateIRQ(lr_idx);
438 } else {
439 // Bogus... Pseudocode says:
440 // - Move from pending to invalid...
441 // - Return de bogus id...
442 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
443 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
444 ich_lr_el2);
445 }
446 }
447 }
448
449 value = int_id;
450 virtualUpdate();
451 break;
452 }
453
454 // Interrupt Acknowledge Register 1
455 case MISCREG_ICC_IAR1:
456 case MISCREG_ICC_IAR1_EL1: {
457 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
458 return readMiscReg(MISCREG_ICV_IAR1_EL1);
459 }
460
461 uint32_t int_id;
462
463 if (hppiCanPreempt()) {
464 int_id = getHPPIR1();
465
466 // avoid activation for special interrupts
467 if (int_id < Gicv3::INTID_SECURE) {
468 activateIRQ(int_id, hppi.group);
469 }
470 } else {
471 int_id = Gicv3::INTID_SPURIOUS;
472 }
473
474 value = int_id;
475 break;
476 }
477
478 // Virtual Interrupt Acknowledge Register 1
479 case MISCREG_ICV_IAR1_EL1: {
480 int lr_idx = getHPPVILR();
481 uint32_t int_id = Gicv3::INTID_SPURIOUS;
482
483 if (lr_idx >= 0) {
484 ICH_LR_EL2 ich_lr_el2 =
485 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
486
487 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
488 int_id = ich_lr_el2.vINTID;
489
490 if (int_id < Gicv3::INTID_SECURE ||
491 int_id > Gicv3::INTID_SPURIOUS) {
492 virtualActivateIRQ(lr_idx);
493 } else {
494 // Bogus... Pseudocode says:
495 // - Move from pending to invalid...
496 // - Return de bogus id...
497 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
498 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
499 ich_lr_el2);
500 }
501 }
502 }
503
504 value = int_id;
505 virtualUpdate();
506 break;
507 }
508
509 // System Register Enable Register EL1
510 case MISCREG_ICC_SRE:
511 case MISCREG_ICC_SRE_EL1: {
512 /*
513 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
514 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
515 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
516 */
517 ICC_SRE_EL1 icc_sre_el1 = 0;
518 icc_sre_el1.SRE = 1;
519 icc_sre_el1.DIB = 1;
520 icc_sre_el1.DFB = 1;
521 value = icc_sre_el1;
522 break;
523 }
524
525 // System Register Enable Register EL2
526 case MISCREG_ICC_HSRE:
527 case MISCREG_ICC_SRE_EL2: {
528 /*
529 * Enable [3] == 1
530 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
531 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
532 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
533 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
534 */
535 ICC_SRE_EL2 icc_sre_el2 = 0;
536 icc_sre_el2.SRE = 1;
537 icc_sre_el2.DIB = 1;
538 icc_sre_el2.DFB = 1;
539 icc_sre_el2.Enable = 1;
540 value = icc_sre_el2;
541 break;
542 }
543
544 // System Register Enable Register EL3
545 case MISCREG_ICC_MSRE:
546 case MISCREG_ICC_SRE_EL3: {
547 /*
548 * Enable [3] == 1
549 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
550 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
551 * RAO/WI)
552 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
553 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
554 * SRE [0] == 1 (Only system register interface supported, RAO/WI)
555 */
556 ICC_SRE_EL3 icc_sre_el3 = 0;
557 icc_sre_el3.SRE = 1;
558 icc_sre_el3.DIB = 1;
559 icc_sre_el3.DFB = 1;
560 icc_sre_el3.Enable = 1;
561 value = icc_sre_el3;
562 break;
563 }
564
565 // Control Register
566 case MISCREG_ICC_CTLR:
567 case MISCREG_ICC_CTLR_EL1: {
568 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
569 return readMiscReg(MISCREG_ICV_CTLR_EL1);
570 }
571
572 // Enforce value for RO bits
573 // ExtRange [19], INTIDs in the range 1024..8191 not supported
574 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
575 // A3V [15], supports non-zero values of the Aff3 field in SGI
576 // generation System registers
577 // SEIS [14], does not support generation of SEIs (deprecated)
578 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
579 // PRIbits [10:8], number of priority bits implemented, minus one
580 ICC_CTLR_EL1 icc_ctlr_el1 = value;
581 icc_ctlr_el1.ExtRange = 0;
582 icc_ctlr_el1.RSS = 1;
583 icc_ctlr_el1.A3V = 1;
584 icc_ctlr_el1.SEIS = 0;
585 icc_ctlr_el1.IDbits = 1;
586 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
587 value = icc_ctlr_el1;
588 break;
589 }
590
591 // Virtual Control Register
592 case MISCREG_ICV_CTLR_EL1: {
593 ICV_CTLR_EL1 icv_ctlr_el1 = value;
594 icv_ctlr_el1.RSS = 0;
595 icv_ctlr_el1.A3V = 1;
596 icv_ctlr_el1.SEIS = 0;
597 icv_ctlr_el1.IDbits = 1;
598 icv_ctlr_el1.PRIbits = 7;
599 value = icv_ctlr_el1;
600 break;
601 }
602
603 // Control Register
604 case MISCREG_ICC_MCTLR:
605 case MISCREG_ICC_CTLR_EL3: {
606 // Enforce value for RO bits
607 // ExtRange [19], INTIDs in the range 1024..8191 not supported
608 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
609 // nDS [17], supports disabling of security
610 // A3V [15], supports non-zero values of the Aff3 field in SGI
611 // generation System registers
612 // SEIS [14], does not support generation of SEIs (deprecated)
613 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
614 // PRIbits [10:8], number of priority bits implemented, minus one
615 ICC_CTLR_EL3 icc_ctlr_el3 = value;
616 icc_ctlr_el3.ExtRange = 0;
617 icc_ctlr_el3.RSS = 1;
618 icc_ctlr_el3.nDS = 0;
619 icc_ctlr_el3.A3V = 1;
620 icc_ctlr_el3.SEIS = 0;
621 icc_ctlr_el3.IDbits = 0;
622 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
623 value = icc_ctlr_el3;
624 break;
625 }
626
627 // Hyp Control Register
628 case MISCREG_ICH_HCR:
629 case MISCREG_ICH_HCR_EL2:
630 break;
631
632 // Hyp Active Priorities Group 0 Registers
633 case MISCREG_ICH_AP0R0:
634 case MISCREG_ICH_AP0R0_EL2:
635 break;
636
637 // Hyp Active Priorities Group 1 Registers
638 case MISCREG_ICH_AP1R0:
639 case MISCREG_ICH_AP1R0_EL2:
640 break;
641
642 // Maintenance Interrupt State Register
643 case MISCREG_ICH_MISR:
644 case MISCREG_ICH_MISR_EL2:
645 value = maintenanceInterruptStatus();
646 break;
647
648 // VGIC Type Register
649 case MISCREG_ICH_VTR:
650 case MISCREG_ICH_VTR_EL2: {
651 ICH_VTR_EL2 ich_vtr_el2 = value;
652
653 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
654 ich_vtr_el2.A3V = 1;
655 ich_vtr_el2.IDbits = 1;
656 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
657 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
658
659 value = ich_vtr_el2;
660 break;
661 }
662
663 // End of Interrupt Status Register
664 case MISCREG_ICH_EISR:
665 case MISCREG_ICH_EISR_EL2:
666 value = eoiMaintenanceInterruptStatus();
667 break;
668
669 // Empty List Register Status Register
670 case MISCREG_ICH_ELRSR:
671 case MISCREG_ICH_ELRSR_EL2:
672 value = 0;
673
674 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
675 ICH_LR_EL2 ich_lr_el2 =
676 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
677
678 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
679 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
680 value |= (1 << lr_idx);
681 }
682 }
683
684 break;
685
686 // List Registers
687 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
688 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
689 value = value >> 32;
690 break;
691
692 // List Registers
693 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
694 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
695 value = value & 0xffffffff;
696 break;
697
698 // List Registers
699 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
700 break;
701
702 // Virtual Machine Control Register
703 case MISCREG_ICH_VMCR:
704 case MISCREG_ICH_VMCR_EL2:
705 break;
706
707 default:
708 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
709 misc_reg, miscRegName[misc_reg]);
710 }
711
712 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
713 miscRegName[misc_reg], value);
714 return value;
715}
716
717void
718Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
719{
720 bool do_virtual_update = false;
721 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
722 miscRegName[misc_reg], val);
723 bool hcr_fmo = getHCREL2FMO();
724 bool hcr_imo = getHCREL2IMO();
725
726 switch (misc_reg) {
727 // Active Priorities Group 1 Registers
728 case MISCREG_ICC_AP1R0:
729 case MISCREG_ICC_AP1R0_EL1:
730 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
731 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
732 }
733
734 break;
735
736 case MISCREG_ICC_AP1R1:
737 case MISCREG_ICC_AP1R1_EL1:
738
739 // only implemented if supporting 6 or more bits of priority
740 case MISCREG_ICC_AP1R2:
741 case MISCREG_ICC_AP1R2_EL1:
742
743 // only implemented if supporting 7 or more bits of priority
744 case MISCREG_ICC_AP1R3:
745 case MISCREG_ICC_AP1R3_EL1:
746 // only implemented if supporting 7 or more bits of priority
747 break;
748
749 // Active Priorities Group 0 Registers
750 case MISCREG_ICC_AP0R0:
751 case MISCREG_ICC_AP0R0_EL1:
752 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
753 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
754 }
755
756 break;
757
758 case MISCREG_ICC_AP0R1:
759 case MISCREG_ICC_AP0R1_EL1:
760
761 // only implemented if supporting 6 or more bits of priority
762 case MISCREG_ICC_AP0R2:
763 case MISCREG_ICC_AP0R2_EL1:
764
765 // only implemented if supporting 7 or more bits of priority
766 case MISCREG_ICC_AP0R3:
767 case MISCREG_ICC_AP0R3_EL1:
768 // only implemented if supporting 7 or more bits of priority
769 break;
770
771 // End Of Interrupt Register 0
772 case MISCREG_ICC_EOIR0:
773 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
774 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
775 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
776 }
777
778 int int_id = val & 0xffffff;
779
780 // avoid activation for special interrupts
781 if (int_id >= Gicv3::INTID_SECURE) {
782 return;
783 }
784
785 Gicv3::GroupId group = Gicv3::G0S;
786
787 if (highestActiveGroup() != group) {
788 return;
789 }
790
791 dropPriority(group);
792
793 if (!isEOISplitMode()) {
794 deactivateIRQ(int_id, group);
795 }
796
797 break;
798 }
799
800 // Virtual End Of Interrupt Register 0
801 case MISCREG_ICV_EOIR0_EL1: {
802 int int_id = val & 0xffffff;
803
804 // avoid deactivation for special interrupts
805 if (int_id >= Gicv3::INTID_SECURE &&
806 int_id <= Gicv3::INTID_SPURIOUS) {
807 return;
808 }
809
810 uint8_t drop_prio = virtualDropPriority();
811
812 if (drop_prio == 0xff) {
813 return;
814 }
815
816 int lr_idx = virtualFindActive(int_id);
817
818 if (lr_idx < 0) {
819 // No LR found matching
820 virtualIncrementEOICount();
821 } else {
822 ICH_LR_EL2 ich_lr_el2 =
823 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
824 Gicv3::GroupId lr_group =
825 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
826 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
827
828 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
829 //if (!virtualIsEOISplitMode())
830 {
831 virtualDeactivateIRQ(lr_idx);
832 }
833 }
834 }
835
836 virtualUpdate();
837 break;
838 }
839
840 // End Of Interrupt Register 1
841 case MISCREG_ICC_EOIR1:
842 case MISCREG_ICC_EOIR1_EL1: {
843 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
844 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
845 }
846
847 int int_id = val & 0xffffff;
848
849 // avoid deactivation for special interrupts
850 if (int_id >= Gicv3::INTID_SECURE) {
851 return;
852 }
853
854 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
855
856 if (highestActiveGroup() == Gicv3::G0S) {
857 return;
858 }
859
860 if (distributor->DS == 0) {
861 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
862 return;
863 } else if (highestActiveGroup() == Gicv3::G1NS &&
864 !(!inSecureState() or (currEL() == EL3))) {
865 return;
866 }
867 }
868
869 dropPriority(group);
870
871 if (!isEOISplitMode()) {
872 deactivateIRQ(int_id, group);
873 }
874
875 break;
876 }
877
878 // Virtual End Of Interrupt Register 1
879 case MISCREG_ICV_EOIR1_EL1: {
880 int int_id = val & 0xffffff;
881
882 // avoid deactivation for special interrupts
883 if (int_id >= Gicv3::INTID_SECURE &&
884 int_id <= Gicv3::INTID_SPURIOUS) {
885 return;
886 }
887
888 uint8_t drop_prio = virtualDropPriority();
889
890 if (drop_prio == 0xff) {
891 return;
892 }
893
894 int lr_idx = virtualFindActive(int_id);
895
896 if (lr_idx < 0) {
897 // No matching LR found
898 virtualIncrementEOICount();
899 } else {
900 ICH_LR_EL2 ich_lr_el2 =
901 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
902 Gicv3::GroupId lr_group =
903 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
904 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
905
906 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
907 if (!virtualIsEOISplitMode()) {
908 virtualDeactivateIRQ(lr_idx);
909 }
910 }
911 }
912
913 virtualUpdate();
914 break;
915 }
916
917 // Deactivate Interrupt Register
918 case MISCREG_ICC_DIR:
919 case MISCREG_ICC_DIR_EL1: {
920 if ((currEL() == EL1) && !inSecureState() &&
921 (hcr_imo || hcr_fmo)) {
922 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
923 }
924
925 int int_id = val & 0xffffff;
926
927 // The following checks are as per spec pseudocode
928 // aarch64/support/ICC_DIR_EL1
929
930 // Check for spurious ID
931 if (int_id >= Gicv3::INTID_SECURE) {
932 return;
933 }
934
935 // EOI mode is not set, so don't deactivate
936 if (!isEOISplitMode()) {
937 return;
938 }
939
940 Gicv3::GroupId group =
941 int_id >= 32 ? distributor->getIntGroup(int_id) :
942 redistributor->getIntGroup(int_id);
943 bool irq_is_grp0 = group == Gicv3::G0S;
944 bool single_sec_state = distributor->DS;
945 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
946 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
947 bool route_fiq_to_el3 = scr_el3.fiq;
948 bool route_irq_to_el3 = scr_el3.irq;
949 bool route_fiq_to_el2 = hcr_fmo;
950 bool route_irq_to_el2 = hcr_imo;
951
952 switch (currEL()) {
953 case EL3:
954 break;
955
956 case EL2:
957 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
958 break;
959 }
960
961 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
962 break;
963 }
964
965 return;
966
967 case EL1:
968 if (!isSecureBelowEL3()) {
969 if (single_sec_state && irq_is_grp0 &&
970 !route_fiq_to_el3 && !route_fiq_to_el2) {
971 break;
972 }
973
974 if (!irq_is_secure && !irq_is_grp0 &&
975 !route_irq_to_el3 && !route_irq_to_el2) {
976 break;
977 }
978 } else {
979 if (irq_is_grp0 && !route_fiq_to_el3) {
980 break;
981 }
982
983 if (!irq_is_grp0 &&
984 (!irq_is_secure || !single_sec_state) &&
985 !route_irq_to_el3) {
986 break;
987 }
988 }
989
990 return;
991
992 default:
993 break;
994 }
995
996 deactivateIRQ(int_id, group);
997 break;
998 }
999
1000 // Deactivate Virtual Interrupt Register
1001 case MISCREG_ICV_DIR_EL1: {
1002 int int_id = val & 0xffffff;
1003
1004 // avoid deactivation for special interrupts
1005 if (int_id >= Gicv3::INTID_SECURE &&
1006 int_id <= Gicv3::INTID_SPURIOUS) {
1007 return;
1008 }
1009
1010 if (!virtualIsEOISplitMode()) {
1011 return;
1012 }
1013
1014 int lr_idx = virtualFindActive(int_id);
1015
1016 if (lr_idx < 0) {
1017 // No matching LR found
1018 virtualIncrementEOICount();
1019 } else {
1020 virtualDeactivateIRQ(lr_idx);
1021 }
1022
1023 virtualUpdate();
1024 break;
1025 }
1026
1027 // Binary Point Register 0
1028 case MISCREG_ICC_BPR0:
1029 case MISCREG_ICC_BPR0_EL1:
1030 // Binary Point Register 1
1031 case MISCREG_ICC_BPR1:
1032 case MISCREG_ICC_BPR1_EL1: {
1033 if ((currEL() == EL1) && !inSecureState()) {
1034 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1035 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1036 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1037 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1038 }
1039 }
1040
1041 Gicv3::GroupId group =
1042 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1043
1044 if (group == Gicv3::G1S && !inSecureState()) {
1045 group = Gicv3::G1NS;
1046 }
1047
1048 ICC_CTLR_EL1 icc_ctlr_el1_s =
1049 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1050
1051 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1052 icc_ctlr_el1_s.CBPR) {
1053 group = Gicv3::G0S;
1054 }
1055
1056 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1057 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1058
1059 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1060 icc_ctlr_el1_ns.CBPR) {
1061 // BPR0 + 1 saturated to 7, WI
1062 return;
1063 }
1064
1065 uint8_t min_val = (group == Gicv3::G1NS) ?
1066 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1067 val &= 0x7;
1068
1069 if (val < min_val) {
1070 val = min_val;
1071 }
1072
1073 break;
1074 }
1075
1076 // Virtual Binary Point Register 0
1077 case MISCREG_ICV_BPR0_EL1:
1078 // Virtual Binary Point Register 1
1079 case MISCREG_ICV_BPR1_EL1: {
1080 Gicv3::GroupId group =
1081 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1082 ICH_VMCR_EL2 ich_vmcr_el2 =
1083 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1084
1085 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1086 // BPR0 + 1 saturated to 7, WI
1087 return;
1088 }
1089
1090 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1091
1092 if (group != Gicv3::G0S) {
1093 min_VPBR++;
1094 }
1095
1096 if (val < min_VPBR) {
1097 val = min_VPBR;
1098 }
1099
1100 if (group == Gicv3::G0S) {
1101 ich_vmcr_el2.VBPR0 = val;
1102 } else {
1103 ich_vmcr_el2.VBPR1 = val;
1104 }
1105
1106 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1107 do_virtual_update = true;
1108 break;
1109 }
1110
1111 // Control Register EL1
1112 case MISCREG_ICC_CTLR:
1113 case MISCREG_ICC_CTLR_EL1: {
1114 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1115 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1116 }
1117
1118 /*
1119 * ExtRange is RO.
1120 * RSS is RO.
1121 * A3V is RO.
1122 * SEIS is RO.
1123 * IDbits is RO.
1124 * PRIbits is RO.
1125 */
1126 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1127 ICC_CTLR_EL1 icc_ctlr_el1 =
1128 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1129
1130 ICC_CTLR_EL3 icc_ctlr_el3 =
1131 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1132
1133 // The following could be refactored but it is following
1134 // spec description section 9.2.6 point by point.
1135
1136 // PMHE
1137 if (haveEL(EL3)) {
1138 // PMHE is alias of ICC_CTLR_EL3.PMHE
1139
1140 if (distributor->DS == 0) {
1141 // PMHE is RO
1142 } else if (distributor->DS == 1) {
1143 // PMHE is RW
1144 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1145 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1146 }
1147 } else {
1148 // PMHE is RW (by implementation choice)
1149 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1150 }
1151
1152 // EOImode
1153 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1154
1155 if (inSecureState()) {
1156 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1157 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1158 } else {
1159 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1160 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1161 }
1162
1163 // CBPR
1164 if (haveEL(EL3)) {
1165 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1166
1167 if (distributor->DS == 0) {
1168 // CBPR is RO
1169 } else {
1170 // CBPR is RW
1171 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1172
1173 if (inSecureState()) {
1174 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1175 } else {
1176 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1177 }
1178 }
1179 } else {
1180 // CBPR is RW
1181 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1182 }
1183
1184 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1185
1186 val = icc_ctlr_el1;
1187 break;
1188 }
1189
1190 // Virtual Control Register
1191 case MISCREG_ICV_CTLR_EL1: {
1192 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1193 ICV_CTLR_EL1 icv_ctlr_el1 =
1194 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1195 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1196 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1197 val = icv_ctlr_el1;
1198
1199 // Aliases
1200 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1201 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1202 ICH_VMCR_EL2 ich_vmcr_el2 =
1203 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1204 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1205 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1206 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1207 break;
1208 }
1209
1210 // Control Register EL3
1211 case MISCREG_ICC_MCTLR:
1212 case MISCREG_ICC_CTLR_EL3: {
1213 /*
1214 * ExtRange is RO.
1215 * RSS is RO.
1216 * nDS is RO.
1217 * A3V is RO.
1218 * SEIS is RO.
1219 * IDbits is RO.
1220 * PRIbits is RO.
1221 * PMHE is RAO/WI, priority-based routing is always used.
1222 */
1223 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1224
1225 // Aliases
1226 if (haveEL(EL3))
1227 {
1228 ICC_CTLR_EL1 icc_ctlr_el1_s =
1229 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1230 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1231 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1232
1233 // ICC_CTLR_EL1(NS).EOImode is an alias of
1234 // ICC_CTLR_EL3.EOImode_EL1NS
1235 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1236 // ICC_CTLR_EL1(S).EOImode is an alias of
1237 // ICC_CTLR_EL3.EOImode_EL1S
1238 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1239 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1240 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1241 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1242 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1243
1244 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1245 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1246 icc_ctlr_el1_ns);
1247 }
1248
1249 ICC_CTLR_EL3 icc_ctlr_el3 =
1250 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1251
1252 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1253 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1254 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1255 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1256 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1257 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1258
1259 val = icc_ctlr_el3;
1260 break;
1261 }
1262
1263 // Priority Mask Register
1264 case MISCREG_ICC_PMR:
1265 case MISCREG_ICC_PMR_EL1: {
1266 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1267 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1268 }
1269
1270 val &= 0xff;
1271 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1272
1273 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1274 // Spec section 4.8.1
1275 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1276 RegVal old_icc_pmr_el1 =
1277 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1278
1279 if (!(old_icc_pmr_el1 & 0x80)) {
1280 // If the current priority mask value is in the range of
1281 // 0x00-0x7F then WI
1282 return;
1283 }
1284
1285 // If the current priority mask value is in the range of
1286 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1287 // based on the Non-secure read of the priority mask value
1288 // written to the register.
1289
1290 val = (val >> 1) | 0x80;
1291 }
1292
1293 val &= ~0U << (8 - PRIORITY_BITS);
1294 break;
1295 }
1296
1297 // Interrupt Group 0 Enable Register EL1
1298 case MISCREG_ICC_IGRPEN0:
1299 case MISCREG_ICC_IGRPEN0_EL1: {
1300 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1301 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1302 }
1303
1304 break;
1305 }
1306
1307 // Virtual Interrupt Group 0 Enable register
1308 case MISCREG_ICV_IGRPEN0_EL1: {
1309 bool enable = val & 0x1;
1310 ICH_VMCR_EL2 ich_vmcr_el2 =
1311 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1312 ich_vmcr_el2.VENG0 = enable;
1313 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1314 virtualUpdate();
1315 return;
1316 }
1317
1318 // Interrupt Group 1 Enable register EL1
1319 case MISCREG_ICC_IGRPEN1:
1320 case MISCREG_ICC_IGRPEN1_EL1: {
1321 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1322 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1323 }
1324
1325 if (haveEL(EL3)) {
1326 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1327 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1328 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1329
1330 if (inSecureState()) {
1331 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1332 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1333 } else {
1334 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1335 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1336 }
1337
1338 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1339 icc_igrpen1_el3);
1340 }
1341
1342 break;
1343 }
1344
1345 // Virtual Interrupt Group 1 Enable register
1346 case MISCREG_ICV_IGRPEN1_EL1: {
1347 bool enable = val & 0x1;
1348 ICH_VMCR_EL2 ich_vmcr_el2 =
1349 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1350 ich_vmcr_el2.VENG1 = enable;
1351 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1352 virtualUpdate();
1353 return;
1354 }
1355
1356 // Interrupt Group 1 Enable register
1357 case MISCREG_ICC_MGRPEN1:
1358 case MISCREG_ICC_IGRPEN1_EL3: {
1359 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1360 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1361 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1362
1363 if (inSecureState()) {
1364 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1365 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1366 } else {
1367 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1368 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1369 }
1370
1371 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1372 break;
1373 }
1374
1375 // Software Generated Interrupt Group 0 Register
1376 case MISCREG_ICC_SGI0R:
1377 case MISCREG_ICC_SGI0R_EL1:
1378
1379 // Software Generated Interrupt Group 1 Register
1380 case MISCREG_ICC_SGI1R:
1381 case MISCREG_ICC_SGI1R_EL1:
1382
1383 // Alias Software Generated Interrupt Group 1 Register
1384 case MISCREG_ICC_ASGI1R:
1385 case MISCREG_ICC_ASGI1R_EL1: {
1386 bool ns = !inSecureState();
1387 Gicv3::GroupId group;
1388
1389 if (misc_reg == MISCREG_ICC_SGI1R_EL1) {
1390 group = ns ? Gicv3::G1NS : Gicv3::G1S;
1391 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) {
1392 group = ns ? Gicv3::G1S : Gicv3::G1NS;
1393 } else {
1394 group = Gicv3::G0S;
1395 }
1396
1397 if (distributor->DS && group == Gicv3::G1S) {
1398 group = Gicv3::G0S;
1399 }
1400
1401 uint8_t aff3 = bits(val, 55, 48);
1402 uint8_t aff2 = bits(val, 39, 32);
1403 uint8_t aff1 = bits(val, 23, 16);;
1404 uint16_t target_list = bits(val, 15, 0);
1405 uint32_t int_id = bits(val, 27, 24);
1406 bool irm = bits(val, 40, 40);
1407 uint8_t rs = bits(val, 47, 44);
1408
1409 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1410 Gicv3Redistributor * redistributor_i =
1411 gic->getRedistributor(i);
1412 uint32_t affinity_i = redistributor_i->getAffinity();
1413
1414 if (irm) {
1415 // Interrupts routed to all PEs in the system,
1416 // excluding "self"
1417 if (affinity_i == redistributor->getAffinity()) {
1418 continue;
1419 }
1420 } else {
1421 // Interrupts routed to the PEs specified by
1422 // Aff3.Aff2.Aff1.<target list>
1423 if ((affinity_i >> 8) !=
1424 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1425 continue;
1426 }
1427
1428 uint8_t aff0_i = bits(affinity_i, 7, 0);
1429
1430 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1431 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1432 continue;
1433 }
1434 }
1435
1436 redistributor_i->sendSGI(int_id, group, ns);
1437 }
1438
1439 break;
1440 }
1441
1442 // System Register Enable Register EL1
1443 case MISCREG_ICC_SRE:
1444 case MISCREG_ICC_SRE_EL1:
1445 // System Register Enable Register EL2
1446 case MISCREG_ICC_HSRE:
1447 case MISCREG_ICC_SRE_EL2:
1448 // System Register Enable Register EL3
1449 case MISCREG_ICC_MSRE:
1450 case MISCREG_ICC_SRE_EL3:
1451 // All bits are RAO/WI
1452 return;
1453
1454 // Hyp Control Register
1455 case MISCREG_ICH_HCR:
1456 case MISCREG_ICH_HCR_EL2: {
1457 ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1458 ICH_HCR_EL2 ich_hcr_el2 =
1459 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1460
1461 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1462 {
1463 // EOIcount - Permitted behaviors are:
1464 // - Increment EOIcount.
1465 // - Leave EOIcount unchanged.
1466 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1467 }
1468
1469 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1470 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1471 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1472 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1473 ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1474 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1475 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1476 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1477 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1478 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1479 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1480 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1481 ich_hcr_el2.En = requested_ich_hcr_el2.En;
1482 val = ich_hcr_el2;
1483 do_virtual_update = true;
1484 break;
1485 }
1486
1487 // List Registers
1488 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1489 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1490 ICH_LRC requested_ich_lrc = val;
1491 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1492
1493 ich_lrc.State = requested_ich_lrc.State;
1494 ich_lrc.HW = requested_ich_lrc.HW;
1495 ich_lrc.Group = requested_ich_lrc.Group;
1496
1497 // Priority, bits [23:16]
1498 // At least five bits must be implemented.
1499 // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1500 // We implement 5 bits.
1501 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1502 (ich_lrc.Priority & 0x07);
1503
1504 // pINTID, bits [12:0]
1505 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1506 // - Bits[12:10] : RES0.
1507 // - Bit[9] : EOI.
1508 // - Bits[8:0] : RES0.
1509 // When ICH_LR<n>.HW is 1:
1510 // - This field is only required to implement enough bits to hold a
1511 // valid value for the implemented INTID size. Any unused higher
1512 // order bits are RES0.
1513 if (requested_ich_lrc.HW == 0) {
1514 ich_lrc.EOI = requested_ich_lrc.EOI;
1515 } else {
1516 ich_lrc.pINTID = requested_ich_lrc.pINTID;
1517 }
1518
1519 val = ich_lrc;
1520 do_virtual_update = true;
1521 break;
1522 }
1523
1524 // List Registers
1525 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1526 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1527 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1528 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1529 do_virtual_update = true;
1530 break;
1531 }
1532
1533 // List Registers
1534 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1535 ICH_LR_EL2 requested_ich_lr_el2 = val;
1536 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1537
1538 ich_lr_el2.State = requested_ich_lr_el2.State;
1539 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1540 ich_lr_el2.Group = requested_ich_lr_el2.Group;
1541
1542 // Priority, bits [55:48]
1543 // At least five bits must be implemented.
1544 // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1545 // We implement 5 bits.
1546 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1547 (ich_lr_el2.Priority & 0x07);
1548
1549 // pINTID, bits [44:32]
1550 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1551 // - Bits[44:42] : RES0.
1552 // - Bit[41] : EOI.
1553 // - Bits[40:32] : RES0.
1554 // When ICH_LR<n>_EL2.HW is 1:
1555 // - This field is only required to implement enough bits to hold a
1556 // valid value for the implemented INTID size. Any unused higher
1557 // order bits are RES0.
1558 if (requested_ich_lr_el2.HW == 0) {
1559 ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1560 } else {
1561 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1562 }
1563
1564 // vINTID, bits [31:0]
1565 // It is IMPLEMENTATION DEFINED how many bits are implemented,
1566 // though at least 16 bits must be implemented.
1567 // Unimplemented bits are RES0.
1568 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1569
1570 val = ich_lr_el2;
1571 do_virtual_update = true;
1572 break;
1573 }
1574
1575 // Virtual Machine Control Register
1576 case MISCREG_ICH_VMCR:
1577 case MISCREG_ICH_VMCR_EL2: {
1578 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1579 ICH_VMCR_EL2 ich_vmcr_el2 =
1580 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1581 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1582 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1583
1584 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1585 ich_vmcr_el2.VBPR0 = min_vpr0;
1586 } else {
1587 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1588 }
1589
1590 uint8_t min_vpr1 = min_vpr0 + 1;
1591
1592 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1593 ich_vmcr_el2.VBPR1 = min_vpr1;
1594 } else {
1595 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1596 }
1597
1598 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1599 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1600 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1601 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1602 val = ich_vmcr_el2;
1603 break;
1604 }
1605
1606 // Hyp Active Priorities Group 0 Registers
1607 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1608 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1609 // Hyp Active Priorities Group 1 Registers
1610 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1611 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1612 break;
1613
1614 default:
1615 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1616 misc_reg, miscRegName[misc_reg]);
1617 }
1618
1619 isa->setMiscRegNoEffect(misc_reg, val);
1620
1621 if (do_virtual_update) {
1622 virtualUpdate();
1623 }
1624}
1625
1626int
1627Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1628{
1629 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1630 ICH_LR_EL2 ich_lr_el2 =
1631 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1632
1633 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1634 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1635 (ich_lr_el2.vINTID == int_id)) {
1636 return lr_idx;
1637 }
1638 }
1639
1640 return -1;
1641}
1642
1643uint32_t
1644Gicv3CPUInterface::getHPPIR0() const
1645{
1646 if (hppi.prio == 0xff) {
1647 return Gicv3::INTID_SPURIOUS;
1648 }
1649
1650 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1651
1652 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1653 // interrupt for the other state pending
1654 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1655 }
1656
1657 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1658 return Gicv3::INTID_SPURIOUS;
1659 }
1660
1661 if (irq_is_secure && !inSecureState()) {
1662 // Secure interrupts not visible in Non-secure
1663 return Gicv3::INTID_SPURIOUS;
1664 }
1665
1666 return hppi.intid;
1667}
1668
1669uint32_t
1670Gicv3CPUInterface::getHPPIR1() const
1671{
1672 if (hppi.prio == 0xff) {
1673 return Gicv3::INTID_SPURIOUS;
1674 }
1675
1676 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1677 if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1678 if (hppi.group == Gicv3::G0S) {
1679 return Gicv3::INTID_SECURE;
1680 } else if (hppi.group == Gicv3::G1NS) {
1681 return Gicv3::INTID_NONSECURE;
1682 }
1683 }
1684
1685 if (hppi.group == Gicv3::G0S) {
1686 return Gicv3::INTID_SPURIOUS;
1687 }
1688
1689 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1690
1691 if (irq_is_secure) {
1692 if (!inSecureState()) {
1693 // Secure interrupts not visible in Non-secure
1694 return Gicv3::INTID_SPURIOUS;
1695 }
1696 } else if (!isEL3OrMon() && inSecureState()) {
1697 // Group 1 non-secure interrupts not visible in Secure EL1
1698 return Gicv3::INTID_SPURIOUS;
1699 }
1700
1701 return hppi.intid;
1702}
1703
1704void
1705Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1706{
1707 int apr_misc_reg;
1708 RegVal apr;
1709 apr_misc_reg = group == Gicv3::G0S ?
1710 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1711 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1712
1713 if (apr) {
1714 apr &= apr - 1;
1715 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1716 }
1717
1718 update();
1719}
1720
1721uint8_t
1722Gicv3CPUInterface::virtualDropPriority()
1723{
1724 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1725
1726 for (int i = 0; i < apr_max; i++) {
1727 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1728 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1729
1730 if (!vapr0 && !vapr1) {
1731 continue;
1732 }
1733
1734 int vapr0_count = ctz32(vapr0);
1735 int vapr1_count = ctz32(vapr1);
1736
1737 if (vapr0_count <= vapr1_count) {
1738 vapr0 &= vapr0 - 1;
1739 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1740 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1741 } else {
1742 vapr1 &= vapr1 - 1;
1743 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1744 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1745 }
1746 }
1747
1748 return 0xff;
1749}
1750
1751void
1752Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1753{
1754 // Update active priority registers.
1755 uint32_t prio = hppi.prio & 0xf8;
1756 int apr_bit = prio >> (8 - PRIORITY_BITS);
1757 int reg_bit = apr_bit % 32;
1758 int apr_idx = group == Gicv3::G0S ?
1759 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1760 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1761 apr |= (1 << reg_bit);
1762 isa->setMiscRegNoEffect(apr_idx, apr);
1763
1764 // Move interrupt state from pending to active.
1765 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1766 // SGI or PPI, redistributor
1767 redistributor->activateIRQ(int_id);
1768 redistributor->updateAndInformCPUInterface();
1769 } else if (int_id < Gicv3::INTID_SECURE) {
1770 // SPI, distributor
1771 distributor->activateIRQ(int_id);
1772 distributor->updateAndInformCPUInterfaces();
1773 }
1774}
1775
1776void
1777Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1778{
1779 // Update active priority registers.
1780 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1781 lr_idx);
1782 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1783 uint8_t prio = ich_lr_el.Priority & 0xf8;
1784 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1785 int reg_no = apr_bit / 32;
1786 int reg_bit = apr_bit % 32;
1787 int apr_idx = group == Gicv3::G0S ?
1788 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1789 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1790 apr |= (1 << reg_bit);
1791 isa->setMiscRegNoEffect(apr_idx, apr);
1792 // Move interrupt state from pending to active.
1793 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1794 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1795}
1796
1797void
1798Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1799{
1800 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1801 // SGI or PPI, redistributor
1802 redistributor->deactivateIRQ(int_id);
1803 redistributor->updateAndInformCPUInterface();
1804 } else if (int_id < Gicv3::INTID_SECURE) {
1805 // SPI, distributor
1806 distributor->deactivateIRQ(int_id);
1807 distributor->updateAndInformCPUInterfaces();
1808 } else {
1809 return;
1810 }
1811}
1812
1813void
1814Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1815{
1816 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1817 lr_idx);
1818
1819 if (ich_lr_el2.HW) {
1820 // Deactivate the associated physical interrupt
1821 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1822 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1823 distributor->getIntGroup(ich_lr_el2.pINTID) :
1824 redistributor->getIntGroup(ich_lr_el2.pINTID);
1825 deactivateIRQ(ich_lr_el2.pINTID, group);
1826 }
1827 }
1828
1829 // Remove the active bit
1830 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1831 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1832}
1833
1834/*
1835 * Returns the priority group field for the current BPR value for the group.
1836 * GroupBits() Pseudocode from spec.
1837 */
1838uint32_t
1839Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
1840{
1841 ICC_CTLR_EL1 icc_ctlr_el1_s =
1842 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1843 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1844 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1845
1846 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1847 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1848 group = Gicv3::G0S;
1849 }
1850
1851 int bpr;
1852
1853 if (group == Gicv3::G0S) {
1854 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
1855 } else {
1856 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
1857 }
1858
1859 if (group == Gicv3::G1NS) {
1860 assert(bpr > 0);
1861 bpr--;
1862 }
1863
1864 return ~0U << (bpr + 1);
1865}
1866
1867uint32_t
1868Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1869{
1870 ICH_VMCR_EL2 ich_vmcr_el2 =
1871 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1872
1873 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1874 group = Gicv3::G0S;
1875 }
1876
1877 int bpr;
1878
1879 if (group == Gicv3::G0S) {
1880 bpr = ich_vmcr_el2.VBPR0;
1881 } else {
1882 bpr = ich_vmcr_el2.VBPR1;
1883 }
1884
1885 if (group == Gicv3::G1NS) {
1886 assert(bpr > 0);
1887 bpr--;
1888 }
1889
1890 return ~0U << (bpr + 1);
1891}
1892
1893bool
1894Gicv3CPUInterface::isEOISplitMode() const
1895{
1896 if (isEL3OrMon()) {
1897 ICC_CTLR_EL3 icc_ctlr_el3 =
1898 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1899 return icc_ctlr_el3.EOImode_EL3;
1900 } else {
1901 ICC_CTLR_EL1 icc_ctlr_el1 =
1902 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1903 return icc_ctlr_el1.EOImode;
1904 }
1905}
1906
1907bool
1908Gicv3CPUInterface::virtualIsEOISplitMode() const
1909{
1910 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1911 return ich_vmcr_el2.VEOIM;
1912}
1913
1914int
1915Gicv3CPUInterface::highestActiveGroup() const
1916{
1917 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1918 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
1919 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
1920
1921 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
1922 return Gicv3::G1NS;
1923 }
1924
1925 if (gq_ctz < g0_ctz) {
1926 return Gicv3::G1S;
1927 }
1928
1929 if (g0_ctz < 32) {
1930 return Gicv3::G0S;
1931 }
1932
1933 return -1;
1934}
1935
1936void
1937Gicv3CPUInterface::update()
1938{
1939 bool signal_IRQ = false;
1940 bool signal_FIQ = false;
1941
1942 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
1943 /*
1944 * Secure enabled GIC sending a G1S IRQ to a secure disabled
1945 * CPU -> send G0 IRQ
1946 */
1947 hppi.group = Gicv3::G0S;
1948 }
1949
1950 if (hppiCanPreempt()) {
1951 ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
1952 DPRINTF(GIC, "Gicv3CPUInterface::update(): "
1953 "posting int as %d!\n", int_type);
1954 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
1955 }
1956
1957 if (signal_IRQ) {
1958 gic->postInt(cpuId, ArmISA::INT_IRQ);
1959 } else {
1960 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
1961 }
1962
1963 if (signal_FIQ) {
1964 gic->postInt(cpuId, ArmISA::INT_FIQ);
1965 } else {
1966 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
1967 }
1968}
1969
1970void
1971Gicv3CPUInterface::virtualUpdate()
1972{
1973 bool signal_IRQ = false;
1974 bool signal_FIQ = false;
1975 int lr_idx = getHPPVILR();
1976
1977 if (lr_idx >= 0) {
1978 ICH_LR_EL2 ich_lr_el2 =
1979 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1980
1981 if (hppviCanPreempt(lr_idx)) {
1982 if (ich_lr_el2.Group) {
1983 signal_IRQ = true;
1984 } else {
1985 signal_FIQ = true;
1986 }
1987 }
1988 }
1989
1990 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1991
1992 if (ich_hcr_el2.En) {
1993 if (maintenanceInterruptStatus()) {
|
1989 }
1990 }
1991
1992 if (signal_IRQ) {
1993 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
1994 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
1995 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
1996 } else {
1997 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
1998 }
1999
2000 if (signal_FIQ) {
2001 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2002 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2003 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2004 } else {
2005 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2006 }
2007}
2008
2009// Returns the index of the LR with the HPPI
2010int
2011Gicv3CPUInterface::getHPPVILR() const
2012{
2013 int idx = -1;
2014 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2015
2016 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2017 // VG0 and VG1 disabled...
2018 return idx;
2019 }
2020
2021 uint8_t highest_prio = 0xff;
2022
2023 for (int i = 0; i < 16; i++) {
2024 ICH_LR_EL2 ich_lr_el2 =
2025 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2026
2027 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2028 continue;
2029 }
2030
2031 if (ich_lr_el2.Group) {
2032 // VG1
2033 if (!ich_vmcr_el2.VENG1) {
2034 continue;
2035 }
2036 } else {
2037 // VG0
2038 if (!ich_vmcr_el2.VENG0) {
2039 continue;
2040 }
2041 }
2042
2043 uint8_t prio = ich_lr_el2.Priority;
2044
2045 if (prio < highest_prio) {
2046 highest_prio = prio;
2047 idx = i;
2048 }
2049 }
2050
2051 return idx;
2052}
2053
2054bool
2055Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2056{
2057 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2058 if (!ich_hcr_el2.En) {
2059 // virtual interface is disabled
2060 return false;
2061 }
2062
2063 ICH_LR_EL2 ich_lr_el2 =
2064 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2065 uint8_t prio = ich_lr_el2.Priority;
2066 uint8_t vpmr =
2067 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2068
2069 if (prio >= vpmr) {
2070 // prioriry masked
2071 return false;
2072 }
2073
2074 uint8_t rprio = virtualHighestActivePriority();
2075
2076 if (rprio == 0xff) {
2077 return true;
2078 }
2079
2080 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2081 uint32_t prio_mask = virtualGroupPriorityMask(group);
2082
2083 if ((prio & prio_mask) < (rprio & prio_mask)) {
2084 return true;
2085 }
2086
2087 return false;
2088}
2089
2090uint8_t
2091Gicv3CPUInterface::virtualHighestActivePriority() const
2092{
2093 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2094
2095 for (int i = 0; i < num_aprs; i++) {
2096 RegVal vapr =
2097 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2098 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2099
2100 if (!vapr) {
2101 continue;
2102 }
2103
2104 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2105 }
2106
2107 // no active interrups, return idle priority
2108 return 0xff;
2109}
2110
2111void
2112Gicv3CPUInterface::virtualIncrementEOICount()
2113{
2114 // Increment the EOICOUNT field in ICH_HCR_EL2
2115 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2116 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2117 EOI_cout++;
2118 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2119 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2120}
2121
2122// spec section 4.6.2
2123ArmISA::InterruptTypes
2124Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2125{
2126 bool is_fiq = false;
2127
2128 switch (group) {
2129 case Gicv3::G0S:
2130 is_fiq = true;
2131 break;
2132
2133 case Gicv3::G1S:
2134 is_fiq = (distributor->DS == 0) &&
2135 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2136 break;
2137
2138 case Gicv3::G1NS:
2139 is_fiq = (distributor->DS == 0) && inSecureState();
2140 break;
2141
2142 default:
2143 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2144 }
2145
2146 if (is_fiq) {
2147 return ArmISA::INT_FIQ;
2148 } else {
2149 return ArmISA::INT_IRQ;
2150 }
2151}
2152
2153bool
2154Gicv3CPUInterface::hppiCanPreempt() const
2155{
2156 if (hppi.prio == 0xff) {
2157 // there is no pending interrupt
2158 return false;
2159 }
2160
2161 if (!groupEnabled(hppi.group)) {
2162 // group disabled at CPU interface
2163 return false;
2164 }
2165
2166 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2167 // priority masked
2168 return false;
2169 }
2170
2171 uint8_t rprio = highestActivePriority();
2172
2173 if (rprio == 0xff) {
2174 return true;
2175 }
2176
2177 uint32_t prio_mask = groupPriorityMask(hppi.group);
2178
2179 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2180 return true;
2181 }
2182
2183 return false;
2184}
2185
2186uint8_t
2187Gicv3CPUInterface::highestActivePriority() const
2188{
2189 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2190 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2191 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2192
2193 if (apr) {
2194 return ctz32(apr) << (GIC_MIN_BPR + 1);
2195 }
2196
2197 // no active interrups, return idle priority
2198 return 0xff;
2199}
2200
2201bool
2202Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2203{
2204 switch (group) {
2205 case Gicv3::G0S: {
2206 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2207 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2208 return icc_igrpen0_el1.Enable;
2209 }
2210
2211 case Gicv3::G1S: {
2212 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2213 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2214 return icc_igrpen1_el1_s.Enable;
2215 }
2216
2217 case Gicv3::G1NS: {
2218 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2219 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2220 return icc_igrpen1_el1_ns.Enable;
2221 }
2222
2223 default:
2224 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2225 }
2226}
2227
2228bool
2229Gicv3CPUInterface::inSecureState() const
2230{
2231 if (!gic->getSystem()->haveSecurity()) {
2232 return false;
2233 }
2234
2235 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2236 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2237 return ArmISA::inSecureState(scr, cpsr);
2238}
2239
2240int
2241Gicv3CPUInterface::currEL() const
2242{
2243 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2244 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2245
2246 if (is_64) {
2247 return (ExceptionLevel)(uint8_t) cpsr.el;
2248 } else {
2249 switch (cpsr.mode) {
2250 case MODE_USER:
2251 return 0;
2252
2253 case MODE_HYP:
2254 return 2;
2255
2256 case MODE_MON:
2257 return 3;
2258
2259 default:
2260 return 1;
2261 }
2262 }
2263}
2264
2265bool
2266Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2267{
2268 switch (el) {
2269 case EL0:
2270 case EL1:
2271 return true;
2272
2273 case EL2:
2274 return gic->getSystem()->haveVirtualization();
2275
2276 case EL3:
2277 return gic->getSystem()->haveSecurity();
2278
2279 default:
2280 warn("Unimplemented Exception Level\n");
2281 return false;
2282 }
2283}
2284
2285bool
2286Gicv3CPUInterface::isSecureBelowEL3() const
2287{
2288 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2289 return haveEL(EL3) && scr.ns == 0;
2290}
2291
2292bool
2293Gicv3CPUInterface::isAA64() const
2294{
2295 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2296 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2297}
2298
2299bool
2300Gicv3CPUInterface::isEL3OrMon() const
2301{
2302 if (haveEL(EL3)) {
2303 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2304 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2305
2306 if (is_64 && (cpsr.el == EL3)) {
2307 return true;
2308 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2309 return true;
2310 }
2311 }
2312
2313 return false;
2314}
2315
2316// Computes ICH_EISR_EL2
2317uint64_t
2318Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2319{
2320 // ICH_EISR_EL2
2321 // Bits [63:16] - RES0
2322 // Status<n>, bit [n], for n = 0 to 15
2323 // EOI maintenance interrupt status bit for List register <n>:
2324 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2325 // maintenance interrupt.
2326 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2327 // interrupt that has not been handled.
2328 //
2329 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2330 // of the following are true:
2331 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2332 // - ICH_LR<n>_EL2.HW is 0.
2333 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2334
2335 uint64_t value = 0;
2336
2337 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2338 ICH_LR_EL2 ich_lr_el2 =
2339 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2340
2341 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2342 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2343 value |= (1 << lr_idx);
2344 }
2345 }
2346
2347 return value;
2348}
2349
2350Gicv3CPUInterface::ICH_MISR_EL2
2351Gicv3CPUInterface::maintenanceInterruptStatus() const
2352{
2353 // Comments are copied from SPEC section 9.4.7 (ID012119)
2354 ICH_MISR_EL2 ich_misr_el2 = 0;
2355 ICH_HCR_EL2 ich_hcr_el2 =
2356 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2357 ICH_VMCR_EL2 ich_vmcr_el2 =
2358 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2359
2360 // End Of Interrupt. [bit 0]
2361 // This maintenance interrupt is asserted when at least one bit in
2362 // ICH_EISR_EL2 is 1.
2363
2364 if (eoiMaintenanceInterruptStatus()) {
2365 ich_misr_el2.EOI = 1;
2366 }
2367
2368 // Underflow. [bit 1]
2369 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2370 // zero or one of the List register entries are marked as a valid
2371 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2372 // do not equal 0x0.
2373 uint32_t num_valid_interrupts = 0;
2374 uint32_t num_pending_interrupts = 0;
2375
2376 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2377 ICH_LR_EL2 ich_lr_el2 =
2378 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2379
2380 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2381 num_valid_interrupts++;
2382 }
2383
2384 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2385 num_pending_interrupts++;
2386 }
2387 }
2388
2389 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2390 ich_misr_el2.U = 1;
2391 }
2392
2393 // List Register Entry Not Present. [bit 2]
2394 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2395 // and ICH_HCR_EL2.EOIcount is non-zero.
2396 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2397 ich_misr_el2.LRENP = 1;
2398 }
2399
2400 // No Pending. [bit 3]
2401 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2402 // no List register is in pending state.
2403 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2404 ich_misr_el2.NP = 1;
2405 }
2406
2407 // vPE Group 0 Enabled. [bit 4]
2408 // This maintenance interrupt is asserted when
2409 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2410 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2411 ich_misr_el2.VGrp0E = 1;
2412 }
2413
2414 // vPE Group 0 Disabled. [bit 5]
2415 // This maintenance interrupt is asserted when
2416 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2417 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2418 ich_misr_el2.VGrp0D = 1;
2419 }
2420
2421 // vPE Group 1 Enabled. [bit 6]
2422 // This maintenance interrupt is asserted when
2423 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2424 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2425 ich_misr_el2.VGrp1E = 1;
2426 }
2427
2428 // vPE Group 1 Disabled. [bit 7]
2429 // This maintenance interrupt is asserted when
2430 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2431 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2432 ich_misr_el2.VGrp1D = 1;
2433 }
2434
2435 return ich_misr_el2;
2436}
2437
2438void
2439Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2440{
2441 SERIALIZE_SCALAR(hppi.intid);
2442 SERIALIZE_SCALAR(hppi.prio);
2443 SERIALIZE_ENUM(hppi.group);
2444}
2445
2446void
2447Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2448{
2449 UNSERIALIZE_SCALAR(hppi.intid);
2450 UNSERIALIZE_SCALAR(hppi.prio);
2451 UNSERIALIZE_ENUM(hppi.group);
2452}
| 1995 }
1996 }
1997
1998 if (signal_IRQ) {
1999 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2000 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
2001 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2002 } else {
2003 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2004 }
2005
2006 if (signal_FIQ) {
2007 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2008 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
2009 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2010 } else {
2011 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
2012 }
2013}
2014
2015// Returns the index of the LR with the HPPI
2016int
2017Gicv3CPUInterface::getHPPVILR() const
2018{
2019 int idx = -1;
2020 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2021
2022 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2023 // VG0 and VG1 disabled...
2024 return idx;
2025 }
2026
2027 uint8_t highest_prio = 0xff;
2028
2029 for (int i = 0; i < 16; i++) {
2030 ICH_LR_EL2 ich_lr_el2 =
2031 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2032
2033 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2034 continue;
2035 }
2036
2037 if (ich_lr_el2.Group) {
2038 // VG1
2039 if (!ich_vmcr_el2.VENG1) {
2040 continue;
2041 }
2042 } else {
2043 // VG0
2044 if (!ich_vmcr_el2.VENG0) {
2045 continue;
2046 }
2047 }
2048
2049 uint8_t prio = ich_lr_el2.Priority;
2050
2051 if (prio < highest_prio) {
2052 highest_prio = prio;
2053 idx = i;
2054 }
2055 }
2056
2057 return idx;
2058}
2059
2060bool
2061Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2062{
2063 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2064 if (!ich_hcr_el2.En) {
2065 // virtual interface is disabled
2066 return false;
2067 }
2068
2069 ICH_LR_EL2 ich_lr_el2 =
2070 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2071 uint8_t prio = ich_lr_el2.Priority;
2072 uint8_t vpmr =
2073 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2074
2075 if (prio >= vpmr) {
2076 // prioriry masked
2077 return false;
2078 }
2079
2080 uint8_t rprio = virtualHighestActivePriority();
2081
2082 if (rprio == 0xff) {
2083 return true;
2084 }
2085
2086 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2087 uint32_t prio_mask = virtualGroupPriorityMask(group);
2088
2089 if ((prio & prio_mask) < (rprio & prio_mask)) {
2090 return true;
2091 }
2092
2093 return false;
2094}
2095
2096uint8_t
2097Gicv3CPUInterface::virtualHighestActivePriority() const
2098{
2099 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2100
2101 for (int i = 0; i < num_aprs; i++) {
2102 RegVal vapr =
2103 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2104 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2105
2106 if (!vapr) {
2107 continue;
2108 }
2109
2110 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2111 }
2112
2113 // no active interrups, return idle priority
2114 return 0xff;
2115}
2116
2117void
2118Gicv3CPUInterface::virtualIncrementEOICount()
2119{
2120 // Increment the EOICOUNT field in ICH_HCR_EL2
2121 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2122 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2123 EOI_cout++;
2124 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2125 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2126}
2127
2128// spec section 4.6.2
2129ArmISA::InterruptTypes
2130Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2131{
2132 bool is_fiq = false;
2133
2134 switch (group) {
2135 case Gicv3::G0S:
2136 is_fiq = true;
2137 break;
2138
2139 case Gicv3::G1S:
2140 is_fiq = (distributor->DS == 0) &&
2141 (!inSecureState() || ((currEL() == EL3) && isAA64()));
2142 break;
2143
2144 case Gicv3::G1NS:
2145 is_fiq = (distributor->DS == 0) && inSecureState();
2146 break;
2147
2148 default:
2149 panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2150 }
2151
2152 if (is_fiq) {
2153 return ArmISA::INT_FIQ;
2154 } else {
2155 return ArmISA::INT_IRQ;
2156 }
2157}
2158
2159bool
2160Gicv3CPUInterface::hppiCanPreempt() const
2161{
2162 if (hppi.prio == 0xff) {
2163 // there is no pending interrupt
2164 return false;
2165 }
2166
2167 if (!groupEnabled(hppi.group)) {
2168 // group disabled at CPU interface
2169 return false;
2170 }
2171
2172 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2173 // priority masked
2174 return false;
2175 }
2176
2177 uint8_t rprio = highestActivePriority();
2178
2179 if (rprio == 0xff) {
2180 return true;
2181 }
2182
2183 uint32_t prio_mask = groupPriorityMask(hppi.group);
2184
2185 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2186 return true;
2187 }
2188
2189 return false;
2190}
2191
2192uint8_t
2193Gicv3CPUInterface::highestActivePriority() const
2194{
2195 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2196 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2197 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2198
2199 if (apr) {
2200 return ctz32(apr) << (GIC_MIN_BPR + 1);
2201 }
2202
2203 // no active interrups, return idle priority
2204 return 0xff;
2205}
2206
2207bool
2208Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2209{
2210 switch (group) {
2211 case Gicv3::G0S: {
2212 ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2213 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2214 return icc_igrpen0_el1.Enable;
2215 }
2216
2217 case Gicv3::G1S: {
2218 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2219 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2220 return icc_igrpen1_el1_s.Enable;
2221 }
2222
2223 case Gicv3::G1NS: {
2224 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2225 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2226 return icc_igrpen1_el1_ns.Enable;
2227 }
2228
2229 default:
2230 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2231 }
2232}
2233
2234bool
2235Gicv3CPUInterface::inSecureState() const
2236{
2237 if (!gic->getSystem()->haveSecurity()) {
2238 return false;
2239 }
2240
2241 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2242 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
2243 return ArmISA::inSecureState(scr, cpsr);
2244}
2245
2246int
2247Gicv3CPUInterface::currEL() const
2248{
2249 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2250 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2251
2252 if (is_64) {
2253 return (ExceptionLevel)(uint8_t) cpsr.el;
2254 } else {
2255 switch (cpsr.mode) {
2256 case MODE_USER:
2257 return 0;
2258
2259 case MODE_HYP:
2260 return 2;
2261
2262 case MODE_MON:
2263 return 3;
2264
2265 default:
2266 return 1;
2267 }
2268 }
2269}
2270
2271bool
2272Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2273{
2274 switch (el) {
2275 case EL0:
2276 case EL1:
2277 return true;
2278
2279 case EL2:
2280 return gic->getSystem()->haveVirtualization();
2281
2282 case EL3:
2283 return gic->getSystem()->haveSecurity();
2284
2285 default:
2286 warn("Unimplemented Exception Level\n");
2287 return false;
2288 }
2289}
2290
2291bool
2292Gicv3CPUInterface::isSecureBelowEL3() const
2293{
2294 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2295 return haveEL(EL3) && scr.ns == 0;
2296}
2297
2298bool
2299Gicv3CPUInterface::isAA64() const
2300{
2301 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2302 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2303}
2304
2305bool
2306Gicv3CPUInterface::isEL3OrMon() const
2307{
2308 if (haveEL(EL3)) {
2309 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2310 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2311
2312 if (is_64 && (cpsr.el == EL3)) {
2313 return true;
2314 } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2315 return true;
2316 }
2317 }
2318
2319 return false;
2320}
2321
2322// Computes ICH_EISR_EL2
2323uint64_t
2324Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2325{
2326 // ICH_EISR_EL2
2327 // Bits [63:16] - RES0
2328 // Status<n>, bit [n], for n = 0 to 15
2329 // EOI maintenance interrupt status bit for List register <n>:
2330 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2331 // maintenance interrupt.
2332 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2333 // interrupt that has not been handled.
2334 //
2335 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2336 // of the following are true:
2337 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2338 // - ICH_LR<n>_EL2.HW is 0.
2339 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2340
2341 uint64_t value = 0;
2342
2343 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2344 ICH_LR_EL2 ich_lr_el2 =
2345 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2346
2347 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2348 !ich_lr_el2.HW && ich_lr_el2.EOI) {
2349 value |= (1 << lr_idx);
2350 }
2351 }
2352
2353 return value;
2354}
2355
2356Gicv3CPUInterface::ICH_MISR_EL2
2357Gicv3CPUInterface::maintenanceInterruptStatus() const
2358{
2359 // Comments are copied from SPEC section 9.4.7 (ID012119)
2360 ICH_MISR_EL2 ich_misr_el2 = 0;
2361 ICH_HCR_EL2 ich_hcr_el2 =
2362 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2363 ICH_VMCR_EL2 ich_vmcr_el2 =
2364 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2365
2366 // End Of Interrupt. [bit 0]
2367 // This maintenance interrupt is asserted when at least one bit in
2368 // ICH_EISR_EL2 is 1.
2369
2370 if (eoiMaintenanceInterruptStatus()) {
2371 ich_misr_el2.EOI = 1;
2372 }
2373
2374 // Underflow. [bit 1]
2375 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2376 // zero or one of the List register entries are marked as a valid
2377 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2378 // do not equal 0x0.
2379 uint32_t num_valid_interrupts = 0;
2380 uint32_t num_pending_interrupts = 0;
2381
2382 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2383 ICH_LR_EL2 ich_lr_el2 =
2384 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2385
2386 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2387 num_valid_interrupts++;
2388 }
2389
2390 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2391 num_pending_interrupts++;
2392 }
2393 }
2394
2395 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2396 ich_misr_el2.U = 1;
2397 }
2398
2399 // List Register Entry Not Present. [bit 2]
2400 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2401 // and ICH_HCR_EL2.EOIcount is non-zero.
2402 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2403 ich_misr_el2.LRENP = 1;
2404 }
2405
2406 // No Pending. [bit 3]
2407 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2408 // no List register is in pending state.
2409 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2410 ich_misr_el2.NP = 1;
2411 }
2412
2413 // vPE Group 0 Enabled. [bit 4]
2414 // This maintenance interrupt is asserted when
2415 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2416 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2417 ich_misr_el2.VGrp0E = 1;
2418 }
2419
2420 // vPE Group 0 Disabled. [bit 5]
2421 // This maintenance interrupt is asserted when
2422 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2423 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2424 ich_misr_el2.VGrp0D = 1;
2425 }
2426
2427 // vPE Group 1 Enabled. [bit 6]
2428 // This maintenance interrupt is asserted when
2429 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2430 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2431 ich_misr_el2.VGrp1E = 1;
2432 }
2433
2434 // vPE Group 1 Disabled. [bit 7]
2435 // This maintenance interrupt is asserted when
2436 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2437 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2438 ich_misr_el2.VGrp1D = 1;
2439 }
2440
2441 return ich_misr_el2;
2442}
2443
2444void
2445Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2446{
2447 SERIALIZE_SCALAR(hppi.intid);
2448 SERIALIZE_SCALAR(hppi.prio);
2449 SERIALIZE_ENUM(hppi.group);
2450}
2451
2452void
2453Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2454{
2455 UNSERIALIZE_SCALAR(hppi.intid);
2456 UNSERIALIZE_SCALAR(hppi.prio);
2457 UNSERIALIZE_ENUM(hppi.group);
2458}
|