gic_v3_cpu_interface.cc (14227:af80b8fab43b) | gic_v3_cpu_interface.cc (14231:222f6512335e) |
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1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1805 unchanged lines hidden (view full) --- 1814 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1815 apr |= (1 << reg_bit); 1816 isa->setMiscRegNoEffect(apr_idx, apr); 1817 1818 // Move interrupt state from pending to active. 1819 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1820 // SGI or PPI, redistributor 1821 redistributor->activateIRQ(int_id); | 1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1805 unchanged lines hidden (view full) --- 1814 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1815 apr |= (1 << reg_bit); 1816 isa->setMiscRegNoEffect(apr_idx, apr); 1817 1818 // Move interrupt state from pending to active. 1819 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1820 // SGI or PPI, redistributor 1821 redistributor->activateIRQ(int_id); |
1822 redistributor->updateAndInformCPUInterface(); | |
1823 } else if (int_id < Gicv3::INTID_SECURE) { 1824 // SPI, distributor 1825 distributor->activateIRQ(int_id); | 1822 } else if (int_id < Gicv3::INTID_SECURE) { 1823 // SPI, distributor 1824 distributor->activateIRQ(int_id); |
1826 distributor->updateAndInformCPUInterfaces(); | |
1827 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 1828 // LPI, Redistributor 1829 redistributor->setClrLPI(int_id, false); 1830 } | 1825 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 1826 // LPI, Redistributor 1827 redistributor->setClrLPI(int_id, false); 1828 } |
1829 1830 // By setting the priority to 0xff we are effectively 1831 // making the int_id not pending anymore at the cpu 1832 // interface. 1833 hppi.prio = 0xff; 1834 updateDistributor(); |
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1831} 1832 1833void 1834Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1835{ 1836 // Update active priority registers. 1837 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1838 lr_idx); --- 13 unchanged lines hidden (view full) --- 1852} 1853 1854void 1855Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 1856{ 1857 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1858 // SGI or PPI, redistributor 1859 redistributor->deactivateIRQ(int_id); | 1835} 1836 1837void 1838Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1839{ 1840 // Update active priority registers. 1841 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1842 lr_idx); --- 13 unchanged lines hidden (view full) --- 1856} 1857 1858void 1859Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 1860{ 1861 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1862 // SGI or PPI, redistributor 1863 redistributor->deactivateIRQ(int_id); |
1860 redistributor->updateAndInformCPUInterface(); | |
1861 } else if (int_id < Gicv3::INTID_SECURE) { 1862 // SPI, distributor 1863 distributor->deactivateIRQ(int_id); | 1864 } else if (int_id < Gicv3::INTID_SECURE) { 1865 // SPI, distributor 1866 distributor->deactivateIRQ(int_id); |
1864 distributor->updateAndInformCPUInterfaces(); 1865 } else { 1866 // LPI, redistributor, shouldn't deactivate 1867 redistributor->updateAndInformCPUInterface(); | |
1868 } | 1867 } |
1868 1869 updateDistributor(); |
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1869} 1870 1871void 1872Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 1873{ 1874 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1875 lr_idx); 1876 --- 110 unchanged lines hidden (view full) --- 1987 if (g0_ctz < 32) { 1988 return Gicv3::G0S; 1989 } 1990 1991 return -1; 1992} 1993 1994void | 1870} 1871 1872void 1873Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 1874{ 1875 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1876 lr_idx); 1877 --- 110 unchanged lines hidden (view full) --- 1988 if (g0_ctz < 32) { 1989 return Gicv3::G0S; 1990 } 1991 1992 return -1; 1993} 1994 1995void |
1996Gicv3CPUInterface::updateDistributor() 1997{ 1998 distributor->update(); 1999} 2000 2001void |
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1995Gicv3CPUInterface::update() 1996{ 1997 bool signal_IRQ = false; 1998 bool signal_FIQ = false; 1999 2000 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 2001 /* 2002 * Secure enabled GIC sending a G1S IRQ to a secure disabled --- 514 unchanged lines hidden --- | 2002Gicv3CPUInterface::update() 2003{ 2004 bool signal_IRQ = false; 2005 bool signal_FIQ = false; 2006 2007 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 2008 /* 2009 * Secure enabled GIC sending a G1S IRQ to a secure disabled --- 514 unchanged lines hidden --- |