1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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299 }
300 }
301
302 break;
303 }
304
305 // Binary Point Register 0
306 case MISCREG_ICC_BPR0:
307 case MISCREG_ICC_BPR0_EL1:
308 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
309 return readMiscReg(MISCREG_ICV_BPR0_EL1);
310 }
311
312 M5_FALLTHROUGH;
313
314 // Binary Point Register 1
315 case MISCREG_ICC_BPR1:
316 case MISCREG_ICC_BPR1_EL1: {
317 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
318 return readMiscReg(MISCREG_ICV_BPR1_EL1);
319 }
320
321 Gicv3::GroupId group =
322 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
323
324 if (group == Gicv3::G1S && !inSecureState()) {
325 group = Gicv3::G1NS;
326 }
327
328 ICC_CTLR_EL1 icc_ctlr_el1_s =
329 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
330
331 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
332 icc_ctlr_el1_s.CBPR) {
333 group = Gicv3::G0S;
334 }
335
336 bool sat_inc = false;
337
338 ICC_CTLR_EL1 icc_ctlr_el1_ns =
339 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
340
341 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
342 icc_ctlr_el1_ns.CBPR) {
343 // Reads return BPR0 + 1 saturated to 7, WI
344 group = Gicv3::G0S;
345 sat_inc = true;
346 }
347
348 uint8_t bpr;
349
350 if (group == Gicv3::G0S) {
351 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
352 } else {
353 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
354 bpr = std::max(bpr, group == Gicv3::G1S ?
355 GIC_MIN_BPR : GIC_MIN_BPR_NS);
356 }
357
358 if (sat_inc) {
359 bpr++;
360
361 if (bpr > 7) {
362 bpr = 7;
363 }
364 }
365
366 value = bpr;
367 break;
368 }
369
370 // Virtual Binary Point Register 1
371 case MISCREG_ICV_BPR0_EL1:
372 case MISCREG_ICV_BPR1_EL1: {
373 Gicv3::GroupId group =
374 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
375 ICH_VMCR_EL2 ich_vmcr_el2 =
376 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
377 bool sat_inc = false;
378
379 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
380 // bpr0 + 1 saturated to 7, WI
381 group = Gicv3::G0S;
382 sat_inc = true;
383 }
384
385 uint8_t vbpr;
386
387 if (group == Gicv3::G0S) {
388 vbpr = ich_vmcr_el2.VBPR0;
389 } else {
390 vbpr = ich_vmcr_el2.VBPR1;
391 }
392
393 if (sat_inc) {
394 vbpr++;
395
396 if (vbpr > 7) {
397 vbpr = 7;
398 }
399 }
400
401 value = vbpr;
402 break;
403 }
404
405 // Interrupt Priority Mask Register
406 case MISCREG_ICC_PMR:
407 case MISCREG_ICC_PMR_EL1:
408 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
409 return readMiscReg(MISCREG_ICV_PMR_EL1);
410 }

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1088 }
1089
1090 virtualUpdate();
1091 break;
1092 }
1093
1094 // Binary Point Register 0
1095 case MISCREG_ICC_BPR0:
1096 case MISCREG_ICC_BPR0_EL1:
1097 // Binary Point Register 1
1098 case MISCREG_ICC_BPR1:
1099 case MISCREG_ICC_BPR1_EL1: {
1100 if ((currEL() == EL1) && !inSecureState()) {
1101 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
1102 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1103 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) {
1104 return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1105 }
1106 }
1107
1108 Gicv3::GroupId group =
1109 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
1110
1111 if (group == Gicv3::G1S && !inSecureState()) {
1112 group = Gicv3::G1NS;
1113 }
1114
1115 ICC_CTLR_EL1 icc_ctlr_el1_s =
1116 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1117
1118 if ((group == Gicv3::G1S) && !isEL3OrMon() &&
1119 icc_ctlr_el1_s.CBPR) {
1120 group = Gicv3::G0S;
1121 }
1122
1123 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1124 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1125
1126 if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
1127 icc_ctlr_el1_ns.CBPR) {
1128 // BPR0 + 1 saturated to 7, WI
1129 return;
1130 }
1131
1132 uint8_t min_val = (group == Gicv3::G1NS) ?
1133 GIC_MIN_BPR_NS : GIC_MIN_BPR;
1134 val &= 0x7;
1135
1136 if (val < min_val) {
1137 val = min_val;
1138 }
1139
1140 break;
1141 }
1142
1143 // Virtual Binary Point Register 0
1144 case MISCREG_ICV_BPR0_EL1:
1145 // Virtual Binary Point Register 1
1146 case MISCREG_ICV_BPR1_EL1: {
1147 Gicv3::GroupId group =
1148 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;

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1956 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1957 group = Gicv3::G0S;
1958 }
1959
1960 int bpr;
1961
1962 if (group == Gicv3::G0S) {
1963 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
1964 } else {
1965 bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
1966 }
1967
1968 if (group == Gicv3::G1NS) {
1969 assert(bpr > 0);
1970 bpr--;
1971 }
1972
1973 return ~0U << (bpr + 1);

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2551 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2552 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2553 ich_misr_el2.VGrp1D = 1;
2554 }
2555
2556 return ich_misr_el2;
2557}
2558
2559void
2560Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2561{
2562 SERIALIZE_SCALAR(hppi.intid);
2563 SERIALIZE_SCALAR(hppi.prio);
2564 SERIALIZE_ENUM(hppi.group);
2565}
2566
2567void
2568Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2569{
2570 UNSERIALIZE_SCALAR(hppi.intid);
2571 UNSERIALIZE_SCALAR(hppi.prio);
2572 UNSERIALIZE_ENUM(hppi.group);
2573}