1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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670 case MISCREG_ICH_HCR_EL2:
671 break;
672
673 // Hyp Active Priorities Group 0 Registers
674 case MISCREG_ICH_AP0R0:
675 case MISCREG_ICH_AP0R0_EL2:
676 break;
677
678 // Hyp Active Priorities Group 1 Registers
679 case MISCREG_ICH_AP1R0:
680 case MISCREG_ICH_AP1R0_EL2:
681 break;
682
683 // Maintenance Interrupt State Register
684 case MISCREG_ICH_MISR:
685 case MISCREG_ICH_MISR_EL2:
686 value = maintenanceInterruptStatus();
687 break;
688
689 // VGIC Type Register
690 case MISCREG_ICH_VTR:

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1609 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1610 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1611 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1612 val = ich_vmcr_el2;
1613 break;
1614 }
1615
1616 // Hyp Active Priorities Group 0 Registers
1617 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
1618 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
1619 // Hyp Active Priorities Group 1 Registers
1620 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
1621 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
1622 break;
1623
1624 default:
1625 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1626 misc_reg, miscRegName[misc_reg]);
1627 }
1628
1629 isa->setMiscRegNoEffect(misc_reg, val);
1630
1631 if (do_virtual_update) {

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