1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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1411
1412 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1413 break;
1414 }
1415
1416 // Software Generated Interrupt Group 0 Register
1417 case MISCREG_ICC_SGI0R:
1418 case MISCREG_ICC_SGI0R_EL1:
1419
1420 // Software Generated Interrupt Group 1 Register
1421 case MISCREG_ICC_SGI1R:
1422 case MISCREG_ICC_SGI1R_EL1:
1423
1424 // Alias Software Generated Interrupt Group 1 Register
1425 case MISCREG_ICC_ASGI1R:
1426 case MISCREG_ICC_ASGI1R_EL1: {
1427 bool ns = !inSecureState();
1428 Gicv3::GroupId group;
1429
1430 if (misc_reg == MISCREG_ICC_SGI1R_EL1) {
1431 group = ns ? Gicv3::G1NS : Gicv3::G1S;
1432 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) {
1433 group = ns ? Gicv3::G1S : Gicv3::G1NS;
1434 } else {
1435 group = Gicv3::G0S;
1436 }
1437
1438 if (distributor->DS && group == Gicv3::G1S) {
1439 group = Gicv3::G0S;
1440 }
1441
1442 uint8_t aff3 = bits(val, 55, 48);
1443 uint8_t aff2 = bits(val, 39, 32);
1444 uint8_t aff1 = bits(val, 23, 16);;
1445 uint16_t target_list = bits(val, 15, 0);
1446 uint32_t int_id = bits(val, 27, 24);
1447 bool irm = bits(val, 40, 40);
1448 uint8_t rs = bits(val, 47, 44);
1449
1450 for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
1451 Gicv3Redistributor * redistributor_i =
1452 gic->getRedistributor(i);
1453 uint32_t affinity_i = redistributor_i->getAffinity();
1454
1455 if (irm) {
1456 // Interrupts routed to all PEs in the system,
1457 // excluding "self"
1458 if (affinity_i == redistributor->getAffinity()) {
1459 continue;
1460 }
1461 } else {
1462 // Interrupts routed to the PEs specified by
1463 // Aff3.Aff2.Aff1.<target list>
1464 if ((affinity_i >> 8) !=
1465 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1466 continue;
1467 }
1468
1469 uint8_t aff0_i = bits(affinity_i, 7, 0);
1470
1471 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1472 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1473 continue;
1474 }
1475 }
1476
1477 redistributor_i->sendSGI(int_id, group, ns);
1478 }
1479
1480 break;
1481 }
1482
1483 // System Register Enable Register EL1
1484 case MISCREG_ICC_SRE:
1485 case MISCREG_ICC_SRE_EL1:
1486 // System Register Enable Register EL2
1487 case MISCREG_ICC_HSRE:
1488 case MISCREG_ICC_SRE_EL2:

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1785 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1786 }
1787 }
1788
1789 return 0xff;
1790}
1791
1792void
1793Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1794{
1795 // Update active priority registers.
1796 uint32_t prio = hppi.prio & 0xf8;
1797 int apr_bit = prio >> (8 - PRIORITY_BITS);
1798 int reg_bit = apr_bit % 32;
1799 int apr_idx = group == Gicv3::G0S ?
1800 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;

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