1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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154 case MISCREG_ICC_AP0R3_EL1:
155 // only implemented if supporting 7 or more bits of priority
156 return 0;
157
158 // Interrupt Group 0 Enable register EL1
159 case MISCREG_ICC_IGRPEN0:
160 case MISCREG_ICC_IGRPEN0_EL1: {
161 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
162 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
163 }
164
165 break;
166 }
167
168 // Interrupt Group 1 Enable register EL1
169 case MISCREG_ICC_IGRPEN1:
170 case MISCREG_ICC_IGRPEN1_EL1: {
171 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
172 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
173 }
174
175 break;
176 }
177
178 // Interrupt Group 1 Enable register EL3
179 case MISCREG_ICC_MGRPEN1:
180 case MISCREG_ICC_IGRPEN1_EL3:
181 break;
182
183 // Running Priority Register
184 case MISCREG_ICC_RPR:
185 case MISCREG_ICC_RPR_EL1: {

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375 value = vbpr;
376 break;
377 }
378
379 // Interrupt Priority Mask Register
380 case MISCREG_ICC_PMR:
381 case MISCREG_ICC_PMR_EL1:
382 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
383 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
384 }
385
386 if (haveEL(EL3) && !inSecureState() &&
387 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
388 // Spec section 4.8.1
389 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
390 if ((value & 0x80) == 0) {
391 // If the current priority mask value is in the range of

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396 // 0x80-0xFF a read access returns the Non-secure read of the
397 // current value.
398 value = (value << 1) & 0xff;
399 }
400 }
401
402 break;
403
404 // Interrupt Acknowledge Register 0
405 case MISCREG_ICC_IAR0:
406 case MISCREG_ICC_IAR0_EL1: {
407 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
408 return readMiscReg(MISCREG_ICV_IAR0_EL1);
409 }
410
411 uint32_t int_id;

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1268 val = icc_ctlr_el3;
1269 break;
1270 }
1271
1272 // Priority Mask Register
1273 case MISCREG_ICC_PMR:
1274 case MISCREG_ICC_PMR_EL1: {
1275 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1276 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1277 }
1278
1279 val &= 0xff;
1280 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1281
1282 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1283 // Spec section 4.8.1
1284 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:

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1298
1299 val = (val >> 1) | 0x80;
1300 }
1301
1302 val &= ~0U << (8 - PRIORITY_BITS);
1303 break;
1304 }
1305
1306 // Interrupt Group 0 Enable Register EL1
1307 case MISCREG_ICC_IGRPEN0:
1308 case MISCREG_ICC_IGRPEN0_EL1: {
1309 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1310 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1311 }
1312
1313 break;

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