1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
412 if (int_id < Gicv3::INTID_SECURE) {
413 activateIRQ(int_id, hppi.group);
414 }
415 } else {
416 int_id = Gicv3::INTID_SPURIOUS;
417 }
418
419 value = int_id;
420 break;

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459 }
460
461 uint32_t int_id;
462
463 if (hppiCanPreempt()) {
464 int_id = getHPPIR1();
465
466 // avoid activation for special interrupts
467 if (int_id < Gicv3::INTID_SECURE) {
468 activateIRQ(int_id, hppi.group);
469 }
470 } else {
471 int_id = Gicv3::INTID_SPURIOUS;
472 }
473
474 value = int_id;
475 break;

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773 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
774 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
775 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
776 }
777
778 int int_id = val & 0xffffff;
779
780 // avoid activation for special interrupts
781 if (int_id >= Gicv3::INTID_SECURE) {
782 return;
783 }
784
785 Gicv3::GroupId group = Gicv3::G0S;
786
787 if (highestActiveGroup() != group) {
788 return;
789 }

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842 case MISCREG_ICC_EOIR1_EL1: {
843 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
844 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
845 }
846
847 int int_id = val & 0xffffff;
848
849 // avoid deactivation for special interrupts
850 if (int_id >= Gicv3::INTID_SECURE) {
851 return;
852 }
853
854 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
855
856 if (highestActiveGroup() == Gicv3::G0S) {
857 return;
858 }

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1765 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1766 // SGI or PPI, redistributor
1767 redistributor->activateIRQ(int_id);
1768 redistributor->updateAndInformCPUInterface();
1769 } else if (int_id < Gicv3::INTID_SECURE) {
1770 // SPI, distributor
1771 distributor->activateIRQ(int_id);
1772 distributor->updateAndInformCPUInterfaces();
1773 }
1774}
1775
1776void
1777Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1778{
1779 // Update active priority registers.
1780 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +

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1801 // SGI or PPI, redistributor
1802 redistributor->deactivateIRQ(int_id);
1803 redistributor->updateAndInformCPUInterface();
1804 } else if (int_id < Gicv3::INTID_SECURE) {
1805 // SPI, distributor
1806 distributor->deactivateIRQ(int_id);
1807 distributor->updateAndInformCPUInterfaces();
1808 } else {
1809 return;
1810 }
1811}
1812
1813void
1814Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1815{
1816 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1817 lr_idx);

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