1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
67bool
68Gicv3CPUInterface::getHCREL2FMO() const
69{
70 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
71
72 if (hcr.tge && hcr.e2h) {
73 return false;
74 } else if (hcr.tge) {
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1980 }
1981 }
1982 }
1983
1984 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1985
1986 if (ich_hcr_el2.En) {
1987 if (maintenanceInterruptStatus()) {
1988 redistributor->sendPPInt(25);
1989 }
1990 }
1991
1992 if (signal_IRQ) {
1993 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
1994 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
1995 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
1996 } else {
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2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 50 unchanged lines hidden (view full) ---
59}
60
61void
62Gicv3CPUInterface::reset()
63{
64 hppi.prio = 0xff;
65}
66
67bool
68Gicv3CPUInterface::getHCREL2FMO() const
69{
70 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
71
72 if (hcr.tge && hcr.e2h) {
73 return false;
74 } else if (hcr.tge) {
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1980 }
1981 }
1982 }
1983
1984 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1985
1986 if (ich_hcr_el2.En) {
1987 if (maintenanceInterruptStatus()) {
1988 redistributor->sendPPInt(25);
1989 }
1990 }
1991
1992 if (signal_IRQ) {
1993 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
1994 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
1995 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
1996 } else {
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