1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;
203 }
204
205 // Interrupt Group 1 Enable register EL3
206 case MISCREG_ICC_MGRPEN1:
207 case MISCREG_ICC_IGRPEN1_EL3: {
208 ICC_IGRPEN1_EL3 igrp_el3 = 0;
209 igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
210 MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
211
212 igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
213 MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
214
215 value = igrp_el3;
216 break;
217 }
218
219 // Running Priority Register
220 case MISCREG_ICC_RPR:
221 case MISCREG_ICC_RPR_EL1: {
222 if ((currEL() == EL1) && !inSecureState() &&
223 (hcr_imo || hcr_fmo)) {
224 return readMiscReg(MISCREG_ICV_RPR_EL1);
225 }

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1348
1349 // Interrupt Group 1 Enable register EL1
1350 case MISCREG_ICC_IGRPEN1:
1351 case MISCREG_ICC_IGRPEN1_EL1: {
1352 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1353 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1354 }
1355
1356 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1357 updateDistributor();
1358 return;
1359 }
1360
1361 // Virtual Interrupt Group 1 Enable register
1362 case MISCREG_ICV_IGRPEN1_EL1: {
1363 bool enable = val & 0x1;

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1368 virtualUpdate();
1369 return;
1370 }
1371
1372 // Interrupt Group 1 Enable register
1373 case MISCREG_ICC_MGRPEN1:
1374 case MISCREG_ICC_IGRPEN1_EL3: {
1375 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1376
1377 isa->setMiscRegNoEffect(
1378 MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
1379 isa->setMiscRegNoEffect(
1380 MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
1381 return;
1382 }
1383
1384 // Software Generated Interrupt Group 0 Register
1385 case MISCREG_ICC_SGI0R:
1386 case MISCREG_ICC_SGI0R_EL1:
1387 generateSGI(val, Gicv3::G0S);
1388 break;
1389

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