1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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670 case MISCREG_ICH_HCR_EL2:
671 break;
672
673 // Hyp Active Priorities Group 0 Registers
674 case MISCREG_ICH_AP0R0:
675 case MISCREG_ICH_AP0R0_EL2:
676 break;
677
678 // only implemented if supporting 6 or more bits of priority
679 case MISCREG_ICH_AP0R1:
680 case MISCREG_ICH_AP0R1_EL2:
681 // only implemented if supporting 7 or more bits of priority
682 case MISCREG_ICH_AP0R2:
683 case MISCREG_ICH_AP0R2_EL2:
684 // only implemented if supporting 7 or more bits of priority
685 case MISCREG_ICH_AP0R3:
686 case MISCREG_ICH_AP0R3_EL2:
687 // Unimplemented registers are RAZ/WI
688 return 0;
689
690 // Hyp Active Priorities Group 1 Registers
691 case MISCREG_ICH_AP1R0:
692 case MISCREG_ICH_AP1R0_EL2:
693 break;
694
695 // only implemented if supporting 6 or more bits of priority
696 case MISCREG_ICH_AP1R1:
697 case MISCREG_ICH_AP1R1_EL2:
698 // only implemented if supporting 7 or more bits of priority
699 case MISCREG_ICH_AP1R2:
700 case MISCREG_ICH_AP1R2_EL2:
701 // only implemented if supporting 7 or more bits of priority
702 case MISCREG_ICH_AP1R3:
703 case MISCREG_ICH_AP1R3_EL2:
704 // Unimplemented registers are RAZ/WI
705 return 0;
706
707 // Maintenance Interrupt State Register
708 case MISCREG_ICH_MISR:
709 case MISCREG_ICH_MISR_EL2:
710 value = maintenanceInterruptStatus();
711 break;
712
713 // VGIC Type Register
714 case MISCREG_ICH_VTR:

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1633 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1634 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1635 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1636 val = ich_vmcr_el2;
1637 break;
1638 }
1639
1640 // Hyp Active Priorities Group 0 Registers
1641 case MISCREG_ICH_AP0R0:
1642 case MISCREG_ICH_AP0R0_EL2:
1643 break;
1644
1645 // only implemented if supporting 6 or more bits of priority
1646 case MISCREG_ICH_AP0R1:
1647 case MISCREG_ICH_AP0R1_EL2:
1648 // only implemented if supporting 7 or more bits of priority
1649 case MISCREG_ICH_AP0R2:
1650 case MISCREG_ICH_AP0R2_EL2:
1651 // only implemented if supporting 7 or more bits of priority
1652 case MISCREG_ICH_AP0R3:
1653 case MISCREG_ICH_AP0R3_EL2:
1654 // Unimplemented registers are RAZ/WI
1655 return;
1656
1657 // Hyp Active Priorities Group 1 Registers
1658 case MISCREG_ICH_AP1R0:
1659 case MISCREG_ICH_AP1R0_EL2:
1660 break;
1661
1662 // only implemented if supporting 6 or more bits of priority
1663 case MISCREG_ICH_AP1R1:
1664 case MISCREG_ICH_AP1R1_EL2:
1665 // only implemented if supporting 7 or more bits of priority
1666 case MISCREG_ICH_AP1R2:
1667 case MISCREG_ICH_AP1R2_EL2:
1668 // only implemented if supporting 7 or more bits of priority
1669 case MISCREG_ICH_AP1R3:
1670 case MISCREG_ICH_AP1R3_EL2:
1671 // Unimplemented registers are RAZ/WI
1672 return;
1673
1674 default:
1675 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1676 misc_reg, miscRegName[misc_reg]);
1677 }
1678
1679 isa->setMiscRegNoEffect(misc_reg, val);
1680
1681 if (do_virtual_update) {

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