gic_v2.hh (13111:74ef47d9c035) gic_v2.hh (13112:c31596a933a3)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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329 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
330 if (ix == SPURIOUS_INT) {
331 return false;
332 } else {
333 return bits(getIntConfig(ctx, ix), 1) == 0;
334 }
335 }
336
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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329 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
330 if (ix == SPURIOUS_INT) {
331 return false;
332 } else {
333 return bits(getIntConfig(ctx, ix), 1) == 0;
334 }
335 }
336
337 /** CPU enabled */
337 bool isGroup0(ContextID ctx, uint32_t int_num) {
338 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
339 return bits(group_reg, intNumToBit(int_num));
340 }
341
342 /**
343 * This method checks if an interrupt ID must be signaled or has been
344 * signaled as a FIQ to the cpu. It does that by reading:
345 *
346 * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
347 * group1. Only group0 interrupts can be signaled as FIQs.
348 *
349 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
350 * interrupts to a target processor using the FIQ or the IRQ signal
351 */
352 bool isFiq(ContextID ctx, uint32_t int_num) {
353 const bool is_group0 = isGroup0(ctx, int_num);
354 const bool use_fiq = cpuControl[ctx].fiqEn;
355
356 if (is_group0 && use_fiq) {
357 return true;
358 } else {
359 return false;
360 }
361 }
362
363 /** CPU enabled:
364 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
365 */
338 bool cpuEnabled(ContextID ctx) const {
339 return cpuControl[ctx].enableGrp0 ||
340 cpuControl[ctx].enableGrp1;
341 }
342
343 /** GICC_CTLR:
344 * CPU interface control register
345 */

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388 void updateRunPri();
389
390 /** generate a bit mask to check cpuSgi for an interrupt. */
391 uint64_t genSwiMask(int cpu);
392
393 int intNumToWord(int num) const { return num >> 5; }
394 int intNumToBit(int num) const { return num % 32; }
395
366 bool cpuEnabled(ContextID ctx) const {
367 return cpuControl[ctx].enableGrp0 ||
368 cpuControl[ctx].enableGrp1;
369 }
370
371 /** GICC_CTLR:
372 * CPU interface control register
373 */

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416 void updateRunPri();
417
418 /** generate a bit mask to check cpuSgi for an interrupt. */
419 uint64_t genSwiMask(int cpu);
420
421 int intNumToWord(int num) const { return num >> 5; }
422 int intNumToBit(int num) const { return num % 32; }
423
424 /** Clears a cpu IRQ or FIQ signal */
425 void clearInt(ContextID ctx, uint32_t int_num);
426
396 /**
397 * Post an interrupt to a CPU with a delay
398 */
399 void postInt(uint32_t cpu, Tick when);
400 void postFiq(uint32_t cpu, Tick when);
401
402 /**
403 * Deliver a delayed interrupt to the target CPU

--- 80 unchanged lines hidden --- 		427 /**
428 * Post an interrupt to a CPU with a delay
429 */
430 void postInt(uint32_t cpu, Tick when);
431 void postFiq(uint32_t cpu, Tick when);
432
433 /**
434 * Deliver a delayed interrupt to the target CPU

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