gic_v2.hh (13109:786adb0cefde) gic_v2.hh (13110:f7fcb16be5ab)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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189 /** GICD_I{S,C}PENDR0
190 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
191 uint32_t pendingInt;
192
193 /** GICD_I{S,C}ACTIVER0
194 * interrupt active bits for first 32 interrupts, 1b per interrupt */
195 uint32_t activeInt;
196
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 180 unchanged lines hidden (view full) ---

189 /** GICD_I{S,C}PENDR0
190 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
191 uint32_t pendingInt;
192
193 /** GICD_I{S,C}ACTIVER0
194 * interrupt active bits for first 32 interrupts, 1b per interrupt */
195 uint32_t activeInt;
196
197 /** GICD_IGROUPR0
198 * interrupt group bits for first 32 interrupts, 1b per interrupt */
199 uint32_t intGroup;
200
197 /** GICD_IPRIORITYR{0..7}
198 * interrupt priority for SGIs and PPIs */
199 uint8_t intPriority[SGI_MAX + PPI_MAX];
200
201 void serialize(CheckpointOut &cp) const override;
202 void unserialize(CheckpointIn &cp) override;
203
204 BankedRegs() :
201 /** GICD_IPRIORITYR{0..7}
202 * interrupt priority for SGIs and PPIs */
203 uint8_t intPriority[SGI_MAX + PPI_MAX];
204
205 void serialize(CheckpointOut &cp) const override;
206 void unserialize(CheckpointIn &cp) override;
207
208 BankedRegs() :
205 intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
209 intEnabled(0), pendingInt(0), activeInt(0),
210 intGroup(0), intPriority {0}
206 {}
207 };
208 std::vector<BankedRegs*> bankedRegs;
209
210 BankedRegs& getBankedRegs(ContextID);
211
212 /** GICD_I{S,C}ENABLER{1..31}
213 * interrupt enable bits for global interrupts

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245 assert(ix < INT_BITS_MAX);
246 if (ix == 0) {
247 return getBankedRegs(ctx).activeInt;
248 } else {
249 return activeInt[ix - 1];
250 }
251 }
252
211 {}
212 };
213 std::vector<BankedRegs*> bankedRegs;
214
215 BankedRegs& getBankedRegs(ContextID);
216
217 /** GICD_I{S,C}ENABLER{1..31}
218 * interrupt enable bits for global interrupts

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250 assert(ix < INT_BITS_MAX);
251 if (ix == 0) {
252 return getBankedRegs(ctx).activeInt;
253 } else {
254 return activeInt[ix - 1];
255 }
256 }
257
258 /** GICD_IGROUPR{1..31}
259 * interrupt group bits for global interrupts
260 * 1b per interrupt, 32 bits per word, 31 words */
261 uint32_t intGroup[INT_BITS_MAX-1];
262
263 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
264 assert(ix < INT_BITS_MAX);
265 if (ix == 0) {
266 return getBankedRegs(ctx).intGroup;
267 } else {
268 return intGroup[ix - 1];
269 }
270 }
271
253 /** read only running priority register, 1 per cpu*/
254 uint32_t iccrpr[CPU_MAX];
255
256 /** GICD_IPRIORITYR{8..255}
257 * an 8 bit priority (lower is higher priority) for each
258 * of the global (not replicated per CPU) interrupts.
259 */
260 uint8_t intPriority[GLOBAL_INT_LINES];

--- 201 unchanged lines hidden --- 		272 /** read only running priority register, 1 per cpu*/
273 uint32_t iccrpr[CPU_MAX];
274
275 /** GICD_IPRIORITYR{8..255}
276 * an 8 bit priority (lower is higher priority) for each
277 * of the global (not replicated per CPU) interrupts.
278 */
279 uint8_t intPriority[GLOBAL_INT_LINES];

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