gic_v2.hh (13108:8e46a4e10f94) gic_v2.hh (13109:786adb0cefde)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 128 unchanged lines hidden (view full) ---

137 Bitfield<25,24> list_type;
138 EndBitUnion(SWI)
139
140 BitUnion32(IAR)
141 Bitfield<9,0> ack_id;
142 Bitfield<12,10> cpu_id;
143 EndBitUnion(IAR)
144
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 128 unchanged lines hidden (view full) ---

137 Bitfield<25,24> list_type;
138 EndBitUnion(SWI)
139
140 BitUnion32(IAR)
141 Bitfield<9,0> ack_id;
142 Bitfield<12,10> cpu_id;
143 EndBitUnion(IAR)
144
145 BitUnion32(CTLR)
146 Bitfield<3> fiqEn;
147 Bitfield<1> enableGrp1;
148 Bitfield<0> enableGrp0;
149 EndBitUnion(CTLR)
150
145 protected: /* Params */
146 /** Address range for the distributor interface */
147 const AddrRange distRange;
148
149 /** Address range for the CPU interfaces */
150 const AddrRange cpuRange;
151
152 /** All address ranges used by this GIC */

--- 152 unchanged lines hidden (view full) ---

305 if (ix == SPURIOUS_INT) {
306 return false;
307 } else {
308 return bits(getIntConfig(ctx, ix), 1) == 0;
309 }
310 }
311
312 /** CPU enabled */
151 protected: /* Params */
152 /** Address range for the distributor interface */
153 const AddrRange distRange;
154
155 /** Address range for the CPU interfaces */
156 const AddrRange cpuRange;
157
158 /** All address ranges used by this GIC */

--- 152 unchanged lines hidden (view full) ---

311 if (ix == SPURIOUS_INT) {
312 return false;
313 } else {
314 return bits(getIntConfig(ctx, ix), 1) == 0;
315 }
316 }
317
318 /** CPU enabled */
313 bool cpuEnabled[CPU_MAX];
319 bool cpuEnabled(ContextID ctx) const {
320 return cpuControl[ctx].enableGrp0 ||
321 cpuControl[ctx].enableGrp1;
322 }
314
323
324 /** GICC_CTLR:
325 * CPU interface control register
326 */
327 CTLR cpuControl[CPU_MAX];
328
315 /** CPU priority */
316 uint8_t cpuPriority[CPU_MAX];
317 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
318
319 /** Binary point registers */
320 uint8_t cpuBpr[CPU_MAX];
321
322 /** highest interrupt that is interrupting CPU */

--- 125 unchanged lines hidden --- 		329 /** CPU priority */
330 uint8_t cpuPriority[CPU_MAX];
331 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
332
333 /** Binary point registers */
334 uint8_t cpuBpr[CPU_MAX];
335
336 /** highest interrupt that is interrupting CPU */

--- 125 unchanged lines hidden ---