gic_v2.hh (13014:a4f71c3dc602) gic_v2.hh (13108:8e46a4e10f94)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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257 assert(ix < INT_LINES_MAX);
258 if (ix < SGI_MAX + PPI_MAX) {
259 return getBankedRegs(ctx).intPriority[ix];
260 } else {
261 return intPriority[ix - (SGI_MAX + PPI_MAX)];
262 }
263 }
264
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 248 unchanged lines hidden (view full) ---

257 assert(ix < INT_LINES_MAX);
258 if (ix < SGI_MAX + PPI_MAX) {
259 return getBankedRegs(ctx).intPriority[ix];
260 } else {
261 return intPriority[ix - (SGI_MAX + PPI_MAX)];
262 }
263 }
264
265 /** GICD_ICFGRn
266 * get 2 bit config associated to an interrupt.
267 */
268 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
269 assert(ix < INT_LINES_MAX);
270 const uint8_t cfg_low = intNumToBit(ix * 2);
271 const uint8_t cfg_hi = cfg_low + 1;
272 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
273 }
274
265 /** GICD_ITARGETSR{8..255}
266 * an 8 bit cpu target id for each global interrupt.
267 */
268 uint8_t cpuTarget[GLOBAL_INT_LINES];
269
270 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
271 assert(ctx < sys->numRunningContexts());
272 assert(ix < INT_LINES_MAX);

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286 return cpuTarget[ix - 32];
287 }
288 }
289
290 /** 2 bit per interrupt signaling if it's level or edge sensitive
291 * and if it is 1:N or N:N */
292 uint32_t intConfig[INT_BITS_MAX*2];
293
275 /** GICD_ITARGETSR{8..255}
276 * an 8 bit cpu target id for each global interrupt.
277 */
278 uint8_t cpuTarget[GLOBAL_INT_LINES];
279
280 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
281 assert(ctx < sys->numRunningContexts());
282 assert(ix < INT_LINES_MAX);

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296 return cpuTarget[ix - 32];
297 }
298 }
299
300 /** 2 bit per interrupt signaling if it's level or edge sensitive
301 * and if it is 1:N or N:N */
302 uint32_t intConfig[INT_BITS_MAX*2];
303
304 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
305 if (ix == SPURIOUS_INT) {
306 return false;
307 } else {
308 return bits(getIntConfig(ctx, ix), 1) == 0;
309 }
310 }
311
294 /** CPU enabled */
295 bool cpuEnabled[CPU_MAX];
296
297 /** CPU priority */
298 uint8_t cpuPriority[CPU_MAX];
299 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
300
301 /** Binary point registers */

--- 128 unchanged lines hidden --- 		312 /** CPU enabled */
313 bool cpuEnabled[CPU_MAX];
314
315 /** CPU priority */
316 uint8_t cpuPriority[CPU_MAX];
317 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
318
319 /** Binary point registers */

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