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< /** CPU enabled */
---
> bool isGroup0(ContextID ctx, uint32_t int_num) {
> const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
> return bits(group_reg, intNumToBit(int_num));
> }
>
> /**
> * This method checks if an interrupt ID must be signaled or has been
> * signaled as a FIQ to the cpu. It does that by reading:
> *
> * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
> * group1. Only group0 interrupts can be signaled as FIQs.
> *
> * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
> * interrupts to a target processor using the FIQ or the IRQ signal
> */
> bool isFiq(ContextID ctx, uint32_t int_num) {
> const bool is_group0 = isGroup0(ctx, int_num);
> const bool use_fiq = cpuControl[ctx].fiqEn;
>
> if (is_group0 && use_fiq) {
> return true;
> } else {
> return false;
> }
> }
>
> /** CPU enabled:
> * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
> */
395a424,426
> /** Clears a cpu IRQ or FIQ signal */
> void clearInt(ContextID ctx, uint32_t int_num);
>