1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementation of a GICv2
46 */
47
48#ifndef __DEV_ARM_GICV2_H__
49#define __DEV_ARM_GICV2_H__
50
51#include <vector>
52
53#include "base/addr_range.hh"
54#include "base/bitunion.hh"
55#include "cpu/intr_control.hh"
56#include "dev/arm/base_gic.hh"
57#include "dev/io_device.hh"
58#include "dev/platform.hh"
59#include "params/GicV2.hh"
60
61class GicV2 : public BaseGic, public BaseGicRegisters
62{
63 protected:
64 // distributor memory addresses
65 enum {
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
74
75 DIST_SIZE = 0x1000,
76 };
77
| 1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementation of a GICv2
46 */
47
48#ifndef __DEV_ARM_GICV2_H__
49#define __DEV_ARM_GICV2_H__
50
51#include <vector>
52
53#include "base/addr_range.hh"
54#include "base/bitunion.hh"
55#include "cpu/intr_control.hh"
56#include "dev/arm/base_gic.hh"
57#include "dev/io_device.hh"
58#include "dev/platform.hh"
59#include "params/GicV2.hh"
60
61class GicV2 : public BaseGic, public BaseGicRegisters
62{
63 protected:
64 // distributor memory addresses
65 enum {
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
74
75 DIST_SIZE = 0x1000,
76 };
77
|
86
87 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
88 static const AddrRange GICD_ISENABLER; // interrupt set enable
89 static const AddrRange GICD_ICENABLER; // interrupt clear enable
90 static const AddrRange GICD_ISPENDR; // set pending interrupt
91 static const AddrRange GICD_ICPENDR; // clear pending interrupt
92 static const AddrRange GICD_ISACTIVER; // active bit registers
93 static const AddrRange GICD_ICACTIVER; // clear bit registers
94 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
95 static const AddrRange GICD_ITARGETSR; // processor target registers
96 static const AddrRange GICD_ICFGR; // interrupt config registers
97
98 // cpu memory addresses
99 enum {
100 GICC_CTLR = 0x00, // CPU control register
101 GICC_PMR = 0x04, // Interrupt priority mask
102 GICC_BPR = 0x08, // binary point register
103 GICC_IAR = 0x0C, // interrupt ack register
104 GICC_EOIR = 0x10, // end of interrupt
105 GICC_RPR = 0x14, // running priority
106 GICC_HPPIR = 0x18, // highest pending interrupt
107 GICC_ABPR = 0x1c, // aliased binary point
108 GICC_APR0 = 0xd0, // active priority register 0
109 GICC_APR1 = 0xd4, // active priority register 1
110 GICC_APR2 = 0xd8, // active priority register 2
111 GICC_APR3 = 0xdc, // active priority register 3
112 GICC_IIDR = 0xfc, // cpu interface id register
113 GICC_DIR = 0x1000, // deactive interrupt register
114 };
115
116 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
117 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
118
119 /** Mask off SGI's when setting/clearing pending bits */
120 static const int SGI_MASK = 0xFFFF0000;
121
122 /** Mask for bits that config N:N mode in GICD_ICFGR's */
123 static const int NN_CONFIG_MASK = 0x55555555;
124
125 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
126 static const int SPURIOUS_INT = 1023;
127 static const int INT_BITS_MAX = 32;
128 static const int INT_LINES_MAX = 1020;
129 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
130
131 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
132 chosen for consistency with Linux's in-kernel KVM GIC model */
133 static const int GICC_BPR_MINIMUM = 2;
134
135 BitUnion32(SWI)
136 Bitfield<3,0> sgi_id;
137 Bitfield<23,16> cpu_list;
138 Bitfield<25,24> list_type;
139 EndBitUnion(SWI)
140
141 BitUnion32(IAR)
142 Bitfield<9,0> ack_id;
143 Bitfield<12,10> cpu_id;
144 EndBitUnion(IAR)
145
146 BitUnion32(CTLR)
147 Bitfield<3> fiqEn;
148 Bitfield<1> enableGrp1;
149 Bitfield<0> enableGrp0;
150 EndBitUnion(CTLR)
151
152 protected: /* Params */
153 /** Address range for the distributor interface */
154 const AddrRange distRange;
155
156 /** Address range for the CPU interfaces */
157 const AddrRange cpuRange;
158
159 /** All address ranges used by this GIC */
160 const AddrRangeList addrRanges;
161
162 /** Latency for a distributor operation */
163 const Tick distPioDelay;
164
165 /** Latency for a cpu operation */
166 const Tick cpuPioDelay;
167
168 /** Latency for a interrupt to get to CPU */
169 const Tick intLatency;
170
171 protected:
172 /** Gic enabled */
173 bool enabled;
174
175 /** Are gem5 extensions available? */
176 const bool haveGem5Extensions;
177
178 /** gem5 many-core extension enabled by driver */
179 bool gem5ExtensionsEnabled;
180
181 /** Number of itLines enabled */
182 uint32_t itLines;
183
184 /** Registers "banked for each connected processor" per ARM IHI0048B */
185 struct BankedRegs : public Serializable {
186 /** GICD_I{S,C}ENABLER0
187 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
188 uint32_t intEnabled;
189
190 /** GICD_I{S,C}PENDR0
191 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
192 uint32_t pendingInt;
193
194 /** GICD_I{S,C}ACTIVER0
195 * interrupt active bits for first 32 interrupts, 1b per interrupt */
196 uint32_t activeInt;
197
198 /** GICD_IGROUPR0
199 * interrupt group bits for first 32 interrupts, 1b per interrupt */
200 uint32_t intGroup;
201
202 /** GICD_IPRIORITYR{0..7}
203 * interrupt priority for SGIs and PPIs */
204 uint8_t intPriority[SGI_MAX + PPI_MAX];
205
206 void serialize(CheckpointOut &cp) const override;
207 void unserialize(CheckpointIn &cp) override;
208
209 BankedRegs() :
210 intEnabled(0), pendingInt(0), activeInt(0),
211 intGroup(0), intPriority {0}
212 {}
213 };
214 std::vector<BankedRegs*> bankedRegs;
215
216 BankedRegs& getBankedRegs(ContextID);
217
218 /** GICD_I{S,C}ENABLER{1..31}
219 * interrupt enable bits for global interrupts
220 * 1b per interrupt, 32 bits per word, 31 words */
221 uint32_t intEnabled[INT_BITS_MAX-1];
222
223 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
224 if (ix == 0) {
225 return getBankedRegs(ctx).intEnabled;
226 } else {
227 return intEnabled[ix - 1];
228 }
229 }
230
231 /** GICD_I{S,C}PENDR{1..31}
232 * interrupt pending bits for global interrupts
233 * 1b per interrupt, 32 bits per word, 31 words */
234 uint32_t pendingInt[INT_BITS_MAX-1];
235
236 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
237 assert(ix < INT_BITS_MAX);
238 if (ix == 0) {
239 return getBankedRegs(ctx).pendingInt;
240 } else {
241 return pendingInt[ix - 1];
242 }
243 }
244
245 /** GICD_I{S,C}ACTIVER{1..31}
246 * interrupt active bits for global interrupts
247 * 1b per interrupt, 32 bits per word, 31 words */
248 uint32_t activeInt[INT_BITS_MAX-1];
249
250 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
251 assert(ix < INT_BITS_MAX);
252 if (ix == 0) {
253 return getBankedRegs(ctx).activeInt;
254 } else {
255 return activeInt[ix - 1];
256 }
257 }
258
259 /** GICD_IGROUPR{1..31}
260 * interrupt group bits for global interrupts
261 * 1b per interrupt, 32 bits per word, 31 words */
262 uint32_t intGroup[INT_BITS_MAX-1];
263
264 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
265 assert(ix < INT_BITS_MAX);
266 if (ix == 0) {
267 return getBankedRegs(ctx).intGroup;
268 } else {
269 return intGroup[ix - 1];
270 }
271 }
272
273 /** read only running priority register, 1 per cpu*/
274 uint32_t iccrpr[CPU_MAX];
275
276 /** GICD_IPRIORITYR{8..255}
277 * an 8 bit priority (lower is higher priority) for each
278 * of the global (not replicated per CPU) interrupts.
279 */
280 uint8_t intPriority[GLOBAL_INT_LINES];
281
282 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
283 assert(ix < INT_LINES_MAX);
284 if (ix < SGI_MAX + PPI_MAX) {
285 return getBankedRegs(ctx).intPriority[ix];
286 } else {
287 return intPriority[ix - (SGI_MAX + PPI_MAX)];
288 }
289 }
290
291 /** GICD_ICFGRn
292 * get 2 bit config associated to an interrupt.
293 */
294 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
295 assert(ix < INT_LINES_MAX);
296 const uint8_t cfg_low = intNumToBit(ix * 2);
297 const uint8_t cfg_hi = cfg_low + 1;
298 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
299 }
300
301 /** GICD_ITARGETSR{8..255}
302 * an 8 bit cpu target id for each global interrupt.
303 */
304 uint8_t cpuTarget[GLOBAL_INT_LINES];
305
306 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
307 assert(ctx < sys->numRunningContexts());
308 assert(ix < INT_LINES_MAX);
309 if (ix < SGI_MAX + PPI_MAX) {
310 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
311 // field returns a value that corresponds only to the processor
312 // reading the register."
313 uint32_t ctx_mask;
314 if (gem5ExtensionsEnabled) {
315 ctx_mask = ctx;
316 } else {
317 // convert the CPU id number into a bit mask
318 ctx_mask = power(2, ctx);
319 }
320 return ctx_mask;
321 } else {
322 return cpuTarget[ix - 32];
323 }
324 }
325
326 /** 2 bit per interrupt signaling if it's level or edge sensitive
327 * and if it is 1:N or N:N */
328 uint32_t intConfig[INT_BITS_MAX*2];
329
330 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
331 if (ix == SPURIOUS_INT) {
332 return false;
333 } else {
334 return bits(getIntConfig(ctx, ix), 1) == 0;
335 }
336 }
337
338 bool isGroup0(ContextID ctx, uint32_t int_num) {
339 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
340 return !bits(group_reg, intNumToBit(int_num));
341 }
342
343 /**
344 * This method checks if an interrupt ID must be signaled or has been
345 * signaled as a FIQ to the cpu. It does that by reading:
346 *
347 * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
348 * group1. Only group0 interrupts can be signaled as FIQs.
349 *
350 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
351 * interrupts to a target processor using the FIQ or the IRQ signal
352 */
353 bool isFiq(ContextID ctx, uint32_t int_num) {
354 const bool is_group0 = isGroup0(ctx, int_num);
355 const bool use_fiq = cpuControl[ctx].fiqEn;
356
357 if (is_group0 && use_fiq) {
358 return true;
359 } else {
360 return false;
361 }
362 }
363
364 /** CPU enabled:
365 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
366 */
367 bool cpuEnabled(ContextID ctx) const {
368 return cpuControl[ctx].enableGrp0 ||
369 cpuControl[ctx].enableGrp1;
370 }
371
372 /** GICC_CTLR:
373 * CPU interface control register
374 */
375 CTLR cpuControl[CPU_MAX];
376
377 /** CPU priority */
378 uint8_t cpuPriority[CPU_MAX];
379 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
380
381 /** Binary point registers */
382 uint8_t cpuBpr[CPU_MAX];
383
384 /** highest interrupt that is interrupting CPU */
385 uint32_t cpuHighestInt[CPU_MAX];
386
387 /** One bit per cpu per software interrupt that is pending for each
388 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
389 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
390 * interrupt for CPU 2. */
391 uint64_t cpuSgiPending[SGI_MAX];
392 uint64_t cpuSgiActive[SGI_MAX];
393
394 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
395 * 16 SGI pending bits for each of the (large number of) CPUs.
396 */
397 uint32_t cpuSgiPendingExt[CPU_MAX];
398 uint32_t cpuSgiActiveExt[CPU_MAX];
399
400 /** One bit per private peripheral interrupt. Only upper 16 bits
401 * will be used since PPI interrupts are numberred from 16 to 32 */
402 uint32_t cpuPpiPending[CPU_MAX];
403 uint32_t cpuPpiActive[CPU_MAX];
404
405 /** software generated interrupt
406 * @param data data to decode that indicates which cpus to interrupt
407 */
408 void softInt(ContextID ctx, SWI swi);
409
410 /** See if some processor interrupt flags need to be enabled/disabled
411 * @param hint which set of interrupts needs to be checked
412 */
413 virtual void updateIntState(int hint);
414
415 /** Update the register that records priority of the highest priority
416 * active interrupt*/
417 void updateRunPri();
418
419 /** generate a bit mask to check cpuSgi for an interrupt. */
420 uint64_t genSwiMask(int cpu);
421
422 int intNumToWord(int num) const { return num >> 5; }
423 int intNumToBit(int num) const { return num % 32; }
424
425 /** Clears a cpu IRQ or FIQ signal */
426 void clearInt(ContextID ctx, uint32_t int_num);
427
428 /**
429 * Post an interrupt to a CPU with a delay
430 */
431 void postInt(uint32_t cpu, Tick when);
432 void postFiq(uint32_t cpu, Tick when);
433
434 /**
435 * Deliver a delayed interrupt to the target CPU
436 */
437 void postDelayedInt(uint32_t cpu);
438 void postDelayedFiq(uint32_t cpu);
439
440 EventFunctionWrapper *postIntEvent[CPU_MAX];
441 EventFunctionWrapper *postFiqEvent[CPU_MAX];
442 int pendingDelayedInterrupts;
443
444 public:
445 typedef GicV2Params Params;
446 const Params *
447 params() const
448 {
449 return dynamic_cast<const Params *>(_params);
450 }
451 GicV2(const Params *p);
452 ~GicV2();
453
454 DrainState drain() override;
455 void drainResume() override;
456
457 void serialize(CheckpointOut &cp) const override;
458 void unserialize(CheckpointIn &cp) override;
459
460 public: /* PioDevice */
461 AddrRangeList getAddrRanges() const override { return addrRanges; }
462
463 /** A PIO read to the device, immediately split up into
464 * readDistributor() or readCpu()
465 */
466 Tick read(PacketPtr pkt) override;
467
468 /** A PIO read to the device, immediately split up into
469 * writeDistributor() or writeCpu()
470 */
471 Tick write(PacketPtr pkt) override;
472
473 public: /* BaseGic */
474 void sendInt(uint32_t number) override;
475 void clearInt(uint32_t number) override;
476
477 void sendPPInt(uint32_t num, uint32_t cpu) override;
478 void clearPPInt(uint32_t num, uint32_t cpu) override;
479
480 protected:
481 /** Handle a read to the distributor portion of the GIC
482 * @param pkt packet to respond to
483 */
484 Tick readDistributor(PacketPtr pkt);
485 uint32_t readDistributor(ContextID ctx, Addr daddr,
486 size_t resp_sz);
487 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
488 return readDistributor(ctx, daddr, 4);
489 }
490
491 /** Handle a read to the cpu portion of the GIC
492 * @param pkt packet to respond to
493 */
494 Tick readCpu(PacketPtr pkt);
495 uint32_t readCpu(ContextID ctx, Addr daddr) override;
496
497 /** Handle a write to the distributor portion of the GIC
498 * @param pkt packet to respond to
499 */
500 Tick writeDistributor(PacketPtr pkt);
501 void writeDistributor(ContextID ctx, Addr daddr,
502 uint32_t data, size_t data_sz);
503 void writeDistributor(ContextID ctx, Addr daddr,
504 uint32_t data) override {
505 return writeDistributor(ctx, daddr, data, 4);
506 }
507
508 /** Handle a write to the cpu portion of the GIC
509 * @param pkt packet to respond to
510 */
511 Tick writeCpu(PacketPtr pkt);
512 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
513};
514
515#endif //__DEV_ARM_GIC_H__
| 81
82 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
83 static const AddrRange GICD_ISENABLER; // interrupt set enable
84 static const AddrRange GICD_ICENABLER; // interrupt clear enable
85 static const AddrRange GICD_ISPENDR; // set pending interrupt
86 static const AddrRange GICD_ICPENDR; // clear pending interrupt
87 static const AddrRange GICD_ISACTIVER; // active bit registers
88 static const AddrRange GICD_ICACTIVER; // clear bit registers
89 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
90 static const AddrRange GICD_ITARGETSR; // processor target registers
91 static const AddrRange GICD_ICFGR; // interrupt config registers
92
93 // cpu memory addresses
94 enum {
95 GICC_CTLR = 0x00, // CPU control register
96 GICC_PMR = 0x04, // Interrupt priority mask
97 GICC_BPR = 0x08, // binary point register
98 GICC_IAR = 0x0C, // interrupt ack register
99 GICC_EOIR = 0x10, // end of interrupt
100 GICC_RPR = 0x14, // running priority
101 GICC_HPPIR = 0x18, // highest pending interrupt
102 GICC_ABPR = 0x1c, // aliased binary point
103 GICC_APR0 = 0xd0, // active priority register 0
104 GICC_APR1 = 0xd4, // active priority register 1
105 GICC_APR2 = 0xd8, // active priority register 2
106 GICC_APR3 = 0xdc, // active priority register 3
107 GICC_IIDR = 0xfc, // cpu interface id register
108 GICC_DIR = 0x1000, // deactive interrupt register
109 };
110
111 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
112 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
113
114 /** Mask off SGI's when setting/clearing pending bits */
115 static const int SGI_MASK = 0xFFFF0000;
116
117 /** Mask for bits that config N:N mode in GICD_ICFGR's */
118 static const int NN_CONFIG_MASK = 0x55555555;
119
120 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
121 static const int SPURIOUS_INT = 1023;
122 static const int INT_BITS_MAX = 32;
123 static const int INT_LINES_MAX = 1020;
124 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
125
126 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
127 chosen for consistency with Linux's in-kernel KVM GIC model */
128 static const int GICC_BPR_MINIMUM = 2;
129
130 BitUnion32(SWI)
131 Bitfield<3,0> sgi_id;
132 Bitfield<23,16> cpu_list;
133 Bitfield<25,24> list_type;
134 EndBitUnion(SWI)
135
136 BitUnion32(IAR)
137 Bitfield<9,0> ack_id;
138 Bitfield<12,10> cpu_id;
139 EndBitUnion(IAR)
140
141 BitUnion32(CTLR)
142 Bitfield<3> fiqEn;
143 Bitfield<1> enableGrp1;
144 Bitfield<0> enableGrp0;
145 EndBitUnion(CTLR)
146
147 protected: /* Params */
148 /** Address range for the distributor interface */
149 const AddrRange distRange;
150
151 /** Address range for the CPU interfaces */
152 const AddrRange cpuRange;
153
154 /** All address ranges used by this GIC */
155 const AddrRangeList addrRanges;
156
157 /** Latency for a distributor operation */
158 const Tick distPioDelay;
159
160 /** Latency for a cpu operation */
161 const Tick cpuPioDelay;
162
163 /** Latency for a interrupt to get to CPU */
164 const Tick intLatency;
165
166 protected:
167 /** Gic enabled */
168 bool enabled;
169
170 /** Are gem5 extensions available? */
171 const bool haveGem5Extensions;
172
173 /** gem5 many-core extension enabled by driver */
174 bool gem5ExtensionsEnabled;
175
176 /** Number of itLines enabled */
177 uint32_t itLines;
178
179 /** Registers "banked for each connected processor" per ARM IHI0048B */
180 struct BankedRegs : public Serializable {
181 /** GICD_I{S,C}ENABLER0
182 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
183 uint32_t intEnabled;
184
185 /** GICD_I{S,C}PENDR0
186 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
187 uint32_t pendingInt;
188
189 /** GICD_I{S,C}ACTIVER0
190 * interrupt active bits for first 32 interrupts, 1b per interrupt */
191 uint32_t activeInt;
192
193 /** GICD_IGROUPR0
194 * interrupt group bits for first 32 interrupts, 1b per interrupt */
195 uint32_t intGroup;
196
197 /** GICD_IPRIORITYR{0..7}
198 * interrupt priority for SGIs and PPIs */
199 uint8_t intPriority[SGI_MAX + PPI_MAX];
200
201 void serialize(CheckpointOut &cp) const override;
202 void unserialize(CheckpointIn &cp) override;
203
204 BankedRegs() :
205 intEnabled(0), pendingInt(0), activeInt(0),
206 intGroup(0), intPriority {0}
207 {}
208 };
209 std::vector<BankedRegs*> bankedRegs;
210
211 BankedRegs& getBankedRegs(ContextID);
212
213 /** GICD_I{S,C}ENABLER{1..31}
214 * interrupt enable bits for global interrupts
215 * 1b per interrupt, 32 bits per word, 31 words */
216 uint32_t intEnabled[INT_BITS_MAX-1];
217
218 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
219 if (ix == 0) {
220 return getBankedRegs(ctx).intEnabled;
221 } else {
222 return intEnabled[ix - 1];
223 }
224 }
225
226 /** GICD_I{S,C}PENDR{1..31}
227 * interrupt pending bits for global interrupts
228 * 1b per interrupt, 32 bits per word, 31 words */
229 uint32_t pendingInt[INT_BITS_MAX-1];
230
231 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
232 assert(ix < INT_BITS_MAX);
233 if (ix == 0) {
234 return getBankedRegs(ctx).pendingInt;
235 } else {
236 return pendingInt[ix - 1];
237 }
238 }
239
240 /** GICD_I{S,C}ACTIVER{1..31}
241 * interrupt active bits for global interrupts
242 * 1b per interrupt, 32 bits per word, 31 words */
243 uint32_t activeInt[INT_BITS_MAX-1];
244
245 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
246 assert(ix < INT_BITS_MAX);
247 if (ix == 0) {
248 return getBankedRegs(ctx).activeInt;
249 } else {
250 return activeInt[ix - 1];
251 }
252 }
253
254 /** GICD_IGROUPR{1..31}
255 * interrupt group bits for global interrupts
256 * 1b per interrupt, 32 bits per word, 31 words */
257 uint32_t intGroup[INT_BITS_MAX-1];
258
259 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
260 assert(ix < INT_BITS_MAX);
261 if (ix == 0) {
262 return getBankedRegs(ctx).intGroup;
263 } else {
264 return intGroup[ix - 1];
265 }
266 }
267
268 /** read only running priority register, 1 per cpu*/
269 uint32_t iccrpr[CPU_MAX];
270
271 /** GICD_IPRIORITYR{8..255}
272 * an 8 bit priority (lower is higher priority) for each
273 * of the global (not replicated per CPU) interrupts.
274 */
275 uint8_t intPriority[GLOBAL_INT_LINES];
276
277 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
278 assert(ix < INT_LINES_MAX);
279 if (ix < SGI_MAX + PPI_MAX) {
280 return getBankedRegs(ctx).intPriority[ix];
281 } else {
282 return intPriority[ix - (SGI_MAX + PPI_MAX)];
283 }
284 }
285
286 /** GICD_ICFGRn
287 * get 2 bit config associated to an interrupt.
288 */
289 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
290 assert(ix < INT_LINES_MAX);
291 const uint8_t cfg_low = intNumToBit(ix * 2);
292 const uint8_t cfg_hi = cfg_low + 1;
293 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
294 }
295
296 /** GICD_ITARGETSR{8..255}
297 * an 8 bit cpu target id for each global interrupt.
298 */
299 uint8_t cpuTarget[GLOBAL_INT_LINES];
300
301 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
302 assert(ctx < sys->numRunningContexts());
303 assert(ix < INT_LINES_MAX);
304 if (ix < SGI_MAX + PPI_MAX) {
305 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
306 // field returns a value that corresponds only to the processor
307 // reading the register."
308 uint32_t ctx_mask;
309 if (gem5ExtensionsEnabled) {
310 ctx_mask = ctx;
311 } else {
312 // convert the CPU id number into a bit mask
313 ctx_mask = power(2, ctx);
314 }
315 return ctx_mask;
316 } else {
317 return cpuTarget[ix - 32];
318 }
319 }
320
321 /** 2 bit per interrupt signaling if it's level or edge sensitive
322 * and if it is 1:N or N:N */
323 uint32_t intConfig[INT_BITS_MAX*2];
324
325 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
326 if (ix == SPURIOUS_INT) {
327 return false;
328 } else {
329 return bits(getIntConfig(ctx, ix), 1) == 0;
330 }
331 }
332
333 bool isGroup0(ContextID ctx, uint32_t int_num) {
334 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
335 return !bits(group_reg, intNumToBit(int_num));
336 }
337
338 /**
339 * This method checks if an interrupt ID must be signaled or has been
340 * signaled as a FIQ to the cpu. It does that by reading:
341 *
342 * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
343 * group1. Only group0 interrupts can be signaled as FIQs.
344 *
345 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
346 * interrupts to a target processor using the FIQ or the IRQ signal
347 */
348 bool isFiq(ContextID ctx, uint32_t int_num) {
349 const bool is_group0 = isGroup0(ctx, int_num);
350 const bool use_fiq = cpuControl[ctx].fiqEn;
351
352 if (is_group0 && use_fiq) {
353 return true;
354 } else {
355 return false;
356 }
357 }
358
359 /** CPU enabled:
360 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
361 */
362 bool cpuEnabled(ContextID ctx) const {
363 return cpuControl[ctx].enableGrp0 ||
364 cpuControl[ctx].enableGrp1;
365 }
366
367 /** GICC_CTLR:
368 * CPU interface control register
369 */
370 CTLR cpuControl[CPU_MAX];
371
372 /** CPU priority */
373 uint8_t cpuPriority[CPU_MAX];
374 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
375
376 /** Binary point registers */
377 uint8_t cpuBpr[CPU_MAX];
378
379 /** highest interrupt that is interrupting CPU */
380 uint32_t cpuHighestInt[CPU_MAX];
381
382 /** One bit per cpu per software interrupt that is pending for each
383 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
384 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
385 * interrupt for CPU 2. */
386 uint64_t cpuSgiPending[SGI_MAX];
387 uint64_t cpuSgiActive[SGI_MAX];
388
389 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
390 * 16 SGI pending bits for each of the (large number of) CPUs.
391 */
392 uint32_t cpuSgiPendingExt[CPU_MAX];
393 uint32_t cpuSgiActiveExt[CPU_MAX];
394
395 /** One bit per private peripheral interrupt. Only upper 16 bits
396 * will be used since PPI interrupts are numberred from 16 to 32 */
397 uint32_t cpuPpiPending[CPU_MAX];
398 uint32_t cpuPpiActive[CPU_MAX];
399
400 /** software generated interrupt
401 * @param data data to decode that indicates which cpus to interrupt
402 */
403 void softInt(ContextID ctx, SWI swi);
404
405 /** See if some processor interrupt flags need to be enabled/disabled
406 * @param hint which set of interrupts needs to be checked
407 */
408 virtual void updateIntState(int hint);
409
410 /** Update the register that records priority of the highest priority
411 * active interrupt*/
412 void updateRunPri();
413
414 /** generate a bit mask to check cpuSgi for an interrupt. */
415 uint64_t genSwiMask(int cpu);
416
417 int intNumToWord(int num) const { return num >> 5; }
418 int intNumToBit(int num) const { return num % 32; }
419
420 /** Clears a cpu IRQ or FIQ signal */
421 void clearInt(ContextID ctx, uint32_t int_num);
422
423 /**
424 * Post an interrupt to a CPU with a delay
425 */
426 void postInt(uint32_t cpu, Tick when);
427 void postFiq(uint32_t cpu, Tick when);
428
429 /**
430 * Deliver a delayed interrupt to the target CPU
431 */
432 void postDelayedInt(uint32_t cpu);
433 void postDelayedFiq(uint32_t cpu);
434
435 EventFunctionWrapper *postIntEvent[CPU_MAX];
436 EventFunctionWrapper *postFiqEvent[CPU_MAX];
437 int pendingDelayedInterrupts;
438
439 public:
440 typedef GicV2Params Params;
441 const Params *
442 params() const
443 {
444 return dynamic_cast<const Params *>(_params);
445 }
446 GicV2(const Params *p);
447 ~GicV2();
448
449 DrainState drain() override;
450 void drainResume() override;
451
452 void serialize(CheckpointOut &cp) const override;
453 void unserialize(CheckpointIn &cp) override;
454
455 public: /* PioDevice */
456 AddrRangeList getAddrRanges() const override { return addrRanges; }
457
458 /** A PIO read to the device, immediately split up into
459 * readDistributor() or readCpu()
460 */
461 Tick read(PacketPtr pkt) override;
462
463 /** A PIO read to the device, immediately split up into
464 * writeDistributor() or writeCpu()
465 */
466 Tick write(PacketPtr pkt) override;
467
468 public: /* BaseGic */
469 void sendInt(uint32_t number) override;
470 void clearInt(uint32_t number) override;
471
472 void sendPPInt(uint32_t num, uint32_t cpu) override;
473 void clearPPInt(uint32_t num, uint32_t cpu) override;
474
475 protected:
476 /** Handle a read to the distributor portion of the GIC
477 * @param pkt packet to respond to
478 */
479 Tick readDistributor(PacketPtr pkt);
480 uint32_t readDistributor(ContextID ctx, Addr daddr,
481 size_t resp_sz);
482 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
483 return readDistributor(ctx, daddr, 4);
484 }
485
486 /** Handle a read to the cpu portion of the GIC
487 * @param pkt packet to respond to
488 */
489 Tick readCpu(PacketPtr pkt);
490 uint32_t readCpu(ContextID ctx, Addr daddr) override;
491
492 /** Handle a write to the distributor portion of the GIC
493 * @param pkt packet to respond to
494 */
495 Tick writeDistributor(PacketPtr pkt);
496 void writeDistributor(ContextID ctx, Addr daddr,
497 uint32_t data, size_t data_sz);
498 void writeDistributor(ContextID ctx, Addr daddr,
499 uint32_t data) override {
500 return writeDistributor(ctx, daddr, data, 4);
501 }
502
503 /** Handle a write to the cpu portion of the GIC
504 * @param pkt packet to respond to
505 */
506 Tick writeCpu(PacketPtr pkt);
507 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
508};
509
510#endif //__DEV_ARM_GIC_H__
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