gic_v2.hh (13111:74ef47d9c035) gic_v2.hh (13112:c31596a933a3)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementation of a GICv2
46 */
47
48#ifndef __DEV_ARM_GICV2_H__
49#define __DEV_ARM_GICV2_H__
50
51#include <vector>
52
53#include "base/addr_range.hh"
54#include "base/bitunion.hh"
55#include "cpu/intr_control.hh"
56#include "dev/arm/base_gic.hh"
57#include "dev/io_device.hh"
58#include "dev/platform.hh"
59#include "params/GicV2.hh"
60
61class GicV2 : public BaseGic, public BaseGicRegisters
62{
63 protected:
64 // distributor memory addresses
65 enum {
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
74
75 DIST_SIZE = 0x1000,
76 };
77
78 /**
79 * As defined in:
80 * "ARM Generic Interrupt Controller Architecture" version 2.0
81 * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
82 */
83 static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490;
84 static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B;
85 static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B;
86
87 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
88 static const AddrRange GICD_ISENABLER; // interrupt set enable
89 static const AddrRange GICD_ICENABLER; // interrupt clear enable
90 static const AddrRange GICD_ISPENDR; // set pending interrupt
91 static const AddrRange GICD_ICPENDR; // clear pending interrupt
92 static const AddrRange GICD_ISACTIVER; // active bit registers
93 static const AddrRange GICD_ICACTIVER; // clear bit registers
94 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
95 static const AddrRange GICD_ITARGETSR; // processor target registers
96 static const AddrRange GICD_ICFGR; // interrupt config registers
97
98 // cpu memory addresses
99 enum {
100 GICC_CTLR = 0x00, // CPU control register
101 GICC_PMR = 0x04, // Interrupt priority mask
102 GICC_BPR = 0x08, // binary point register
103 GICC_IAR = 0x0C, // interrupt ack register
104 GICC_EOIR = 0x10, // end of interrupt
105 GICC_RPR = 0x14, // running priority
106 GICC_HPPIR = 0x18, // highest pending interrupt
107 GICC_ABPR = 0x1c, // aliased binary point
108 GICC_APR0 = 0xd0, // active priority register 0
109 GICC_APR1 = 0xd4, // active priority register 1
110 GICC_APR2 = 0xd8, // active priority register 2
111 GICC_APR3 = 0xdc, // active priority register 3
112 GICC_IIDR = 0xfc, // cpu interface id register
113 };
114
115 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
116 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
117
118 /** Mask off SGI's when setting/clearing pending bits */
119 static const int SGI_MASK = 0xFFFF0000;
120
121 /** Mask for bits that config N:N mode in GICD_ICFGR's */
122 static const int NN_CONFIG_MASK = 0x55555555;
123
124 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
125 static const int SPURIOUS_INT = 1023;
126 static const int INT_BITS_MAX = 32;
127 static const int INT_LINES_MAX = 1020;
128 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
129
130 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
131 chosen for consistency with Linux's in-kernel KVM GIC model */
132 static const int GICC_BPR_MINIMUM = 2;
133
134 BitUnion32(SWI)
135 Bitfield<3,0> sgi_id;
136 Bitfield<23,16> cpu_list;
137 Bitfield<25,24> list_type;
138 EndBitUnion(SWI)
139
140 BitUnion32(IAR)
141 Bitfield<9,0> ack_id;
142 Bitfield<12,10> cpu_id;
143 EndBitUnion(IAR)
144
145 BitUnion32(CTLR)
146 Bitfield<3> fiqEn;
147 Bitfield<1> enableGrp1;
148 Bitfield<0> enableGrp0;
149 EndBitUnion(CTLR)
150
151 protected: /* Params */
152 /** Address range for the distributor interface */
153 const AddrRange distRange;
154
155 /** Address range for the CPU interfaces */
156 const AddrRange cpuRange;
157
158 /** All address ranges used by this GIC */
159 const AddrRangeList addrRanges;
160
161 /** Latency for a distributor operation */
162 const Tick distPioDelay;
163
164 /** Latency for a cpu operation */
165 const Tick cpuPioDelay;
166
167 /** Latency for a interrupt to get to CPU */
168 const Tick intLatency;
169
170 protected:
171 /** Gic enabled */
172 bool enabled;
173
174 /** Are gem5 extensions available? */
175 const bool haveGem5Extensions;
176
177 /** gem5 many-core extension enabled by driver */
178 bool gem5ExtensionsEnabled;
179
180 /** Number of itLines enabled */
181 uint32_t itLines;
182
183 /** Registers "banked for each connected processor" per ARM IHI0048B */
184 struct BankedRegs : public Serializable {
185 /** GICD_I{S,C}ENABLER0
186 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
187 uint32_t intEnabled;
188
189 /** GICD_I{S,C}PENDR0
190 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
191 uint32_t pendingInt;
192
193 /** GICD_I{S,C}ACTIVER0
194 * interrupt active bits for first 32 interrupts, 1b per interrupt */
195 uint32_t activeInt;
196
197 /** GICD_IGROUPR0
198 * interrupt group bits for first 32 interrupts, 1b per interrupt */
199 uint32_t intGroup;
200
201 /** GICD_IPRIORITYR{0..7}
202 * interrupt priority for SGIs and PPIs */
203 uint8_t intPriority[SGI_MAX + PPI_MAX];
204
205 void serialize(CheckpointOut &cp) const override;
206 void unserialize(CheckpointIn &cp) override;
207
208 BankedRegs() :
209 intEnabled(0), pendingInt(0), activeInt(0),
210 intGroup(0), intPriority {0}
211 {}
212 };
213 std::vector<BankedRegs*> bankedRegs;
214
215 BankedRegs& getBankedRegs(ContextID);
216
217 /** GICD_I{S,C}ENABLER{1..31}
218 * interrupt enable bits for global interrupts
219 * 1b per interrupt, 32 bits per word, 31 words */
220 uint32_t intEnabled[INT_BITS_MAX-1];
221
222 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
223 if (ix == 0) {
224 return getBankedRegs(ctx).intEnabled;
225 } else {
226 return intEnabled[ix - 1];
227 }
228 }
229
230 /** GICD_I{S,C}PENDR{1..31}
231 * interrupt pending bits for global interrupts
232 * 1b per interrupt, 32 bits per word, 31 words */
233 uint32_t pendingInt[INT_BITS_MAX-1];
234
235 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
236 assert(ix < INT_BITS_MAX);
237 if (ix == 0) {
238 return getBankedRegs(ctx).pendingInt;
239 } else {
240 return pendingInt[ix - 1];
241 }
242 }
243
244 /** GICD_I{S,C}ACTIVER{1..31}
245 * interrupt active bits for global interrupts
246 * 1b per interrupt, 32 bits per word, 31 words */
247 uint32_t activeInt[INT_BITS_MAX-1];
248
249 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
250 assert(ix < INT_BITS_MAX);
251 if (ix == 0) {
252 return getBankedRegs(ctx).activeInt;
253 } else {
254 return activeInt[ix - 1];
255 }
256 }
257
258 /** GICD_IGROUPR{1..31}
259 * interrupt group bits for global interrupts
260 * 1b per interrupt, 32 bits per word, 31 words */
261 uint32_t intGroup[INT_BITS_MAX-1];
262
263 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
264 assert(ix < INT_BITS_MAX);
265 if (ix == 0) {
266 return getBankedRegs(ctx).intGroup;
267 } else {
268 return intGroup[ix - 1];
269 }
270 }
271
272 /** read only running priority register, 1 per cpu*/
273 uint32_t iccrpr[CPU_MAX];
274
275 /** GICD_IPRIORITYR{8..255}
276 * an 8 bit priority (lower is higher priority) for each
277 * of the global (not replicated per CPU) interrupts.
278 */
279 uint8_t intPriority[GLOBAL_INT_LINES];
280
281 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
282 assert(ix < INT_LINES_MAX);
283 if (ix < SGI_MAX + PPI_MAX) {
284 return getBankedRegs(ctx).intPriority[ix];
285 } else {
286 return intPriority[ix - (SGI_MAX + PPI_MAX)];
287 }
288 }
289
290 /** GICD_ICFGRn
291 * get 2 bit config associated to an interrupt.
292 */
293 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
294 assert(ix < INT_LINES_MAX);
295 const uint8_t cfg_low = intNumToBit(ix * 2);
296 const uint8_t cfg_hi = cfg_low + 1;
297 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
298 }
299
300 /** GICD_ITARGETSR{8..255}
301 * an 8 bit cpu target id for each global interrupt.
302 */
303 uint8_t cpuTarget[GLOBAL_INT_LINES];
304
305 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
306 assert(ctx < sys->numRunningContexts());
307 assert(ix < INT_LINES_MAX);
308 if (ix < SGI_MAX + PPI_MAX) {
309 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
310 // field returns a value that corresponds only to the processor
311 // reading the register."
312 uint32_t ctx_mask;
313 if (gem5ExtensionsEnabled) {
314 ctx_mask = ctx;
315 } else {
316 // convert the CPU id number into a bit mask
317 ctx_mask = power(2, ctx);
318 }
319 return ctx_mask;
320 } else {
321 return cpuTarget[ix - 32];
322 }
323 }
324
325 /** 2 bit per interrupt signaling if it's level or edge sensitive
326 * and if it is 1:N or N:N */
327 uint32_t intConfig[INT_BITS_MAX*2];
328
329 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
330 if (ix == SPURIOUS_INT) {
331 return false;
332 } else {
333 return bits(getIntConfig(ctx, ix), 1) == 0;
334 }
335 }
336
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementation of a GICv2
46 */
47
48#ifndef __DEV_ARM_GICV2_H__
49#define __DEV_ARM_GICV2_H__
50
51#include <vector>
52
53#include "base/addr_range.hh"
54#include "base/bitunion.hh"
55#include "cpu/intr_control.hh"
56#include "dev/arm/base_gic.hh"
57#include "dev/io_device.hh"
58#include "dev/platform.hh"
59#include "params/GicV2.hh"
60
61class GicV2 : public BaseGic, public BaseGicRegisters
62{
63 protected:
64 // distributor memory addresses
65 enum {
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
74
75 DIST_SIZE = 0x1000,
76 };
77
78 /**
79 * As defined in:
80 * "ARM Generic Interrupt Controller Architecture" version 2.0
81 * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
82 */
83 static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490;
84 static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B;
85 static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B;
86
87 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
88 static const AddrRange GICD_ISENABLER; // interrupt set enable
89 static const AddrRange GICD_ICENABLER; // interrupt clear enable
90 static const AddrRange GICD_ISPENDR; // set pending interrupt
91 static const AddrRange GICD_ICPENDR; // clear pending interrupt
92 static const AddrRange GICD_ISACTIVER; // active bit registers
93 static const AddrRange GICD_ICACTIVER; // clear bit registers
94 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
95 static const AddrRange GICD_ITARGETSR; // processor target registers
96 static const AddrRange GICD_ICFGR; // interrupt config registers
97
98 // cpu memory addresses
99 enum {
100 GICC_CTLR = 0x00, // CPU control register
101 GICC_PMR = 0x04, // Interrupt priority mask
102 GICC_BPR = 0x08, // binary point register
103 GICC_IAR = 0x0C, // interrupt ack register
104 GICC_EOIR = 0x10, // end of interrupt
105 GICC_RPR = 0x14, // running priority
106 GICC_HPPIR = 0x18, // highest pending interrupt
107 GICC_ABPR = 0x1c, // aliased binary point
108 GICC_APR0 = 0xd0, // active priority register 0
109 GICC_APR1 = 0xd4, // active priority register 1
110 GICC_APR2 = 0xd8, // active priority register 2
111 GICC_APR3 = 0xdc, // active priority register 3
112 GICC_IIDR = 0xfc, // cpu interface id register
113 };
114
115 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
116 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
117
118 /** Mask off SGI's when setting/clearing pending bits */
119 static const int SGI_MASK = 0xFFFF0000;
120
121 /** Mask for bits that config N:N mode in GICD_ICFGR's */
122 static const int NN_CONFIG_MASK = 0x55555555;
123
124 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
125 static const int SPURIOUS_INT = 1023;
126 static const int INT_BITS_MAX = 32;
127 static const int INT_LINES_MAX = 1020;
128 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
129
130 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
131 chosen for consistency with Linux's in-kernel KVM GIC model */
132 static const int GICC_BPR_MINIMUM = 2;
133
134 BitUnion32(SWI)
135 Bitfield<3,0> sgi_id;
136 Bitfield<23,16> cpu_list;
137 Bitfield<25,24> list_type;
138 EndBitUnion(SWI)
139
140 BitUnion32(IAR)
141 Bitfield<9,0> ack_id;
142 Bitfield<12,10> cpu_id;
143 EndBitUnion(IAR)
144
145 BitUnion32(CTLR)
146 Bitfield<3> fiqEn;
147 Bitfield<1> enableGrp1;
148 Bitfield<0> enableGrp0;
149 EndBitUnion(CTLR)
150
151 protected: /* Params */
152 /** Address range for the distributor interface */
153 const AddrRange distRange;
154
155 /** Address range for the CPU interfaces */
156 const AddrRange cpuRange;
157
158 /** All address ranges used by this GIC */
159 const AddrRangeList addrRanges;
160
161 /** Latency for a distributor operation */
162 const Tick distPioDelay;
163
164 /** Latency for a cpu operation */
165 const Tick cpuPioDelay;
166
167 /** Latency for a interrupt to get to CPU */
168 const Tick intLatency;
169
170 protected:
171 /** Gic enabled */
172 bool enabled;
173
174 /** Are gem5 extensions available? */
175 const bool haveGem5Extensions;
176
177 /** gem5 many-core extension enabled by driver */
178 bool gem5ExtensionsEnabled;
179
180 /** Number of itLines enabled */
181 uint32_t itLines;
182
183 /** Registers "banked for each connected processor" per ARM IHI0048B */
184 struct BankedRegs : public Serializable {
185 /** GICD_I{S,C}ENABLER0
186 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
187 uint32_t intEnabled;
188
189 /** GICD_I{S,C}PENDR0
190 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
191 uint32_t pendingInt;
192
193 /** GICD_I{S,C}ACTIVER0
194 * interrupt active bits for first 32 interrupts, 1b per interrupt */
195 uint32_t activeInt;
196
197 /** GICD_IGROUPR0
198 * interrupt group bits for first 32 interrupts, 1b per interrupt */
199 uint32_t intGroup;
200
201 /** GICD_IPRIORITYR{0..7}
202 * interrupt priority for SGIs and PPIs */
203 uint8_t intPriority[SGI_MAX + PPI_MAX];
204
205 void serialize(CheckpointOut &cp) const override;
206 void unserialize(CheckpointIn &cp) override;
207
208 BankedRegs() :
209 intEnabled(0), pendingInt(0), activeInt(0),
210 intGroup(0), intPriority {0}
211 {}
212 };
213 std::vector<BankedRegs*> bankedRegs;
214
215 BankedRegs& getBankedRegs(ContextID);
216
217 /** GICD_I{S,C}ENABLER{1..31}
218 * interrupt enable bits for global interrupts
219 * 1b per interrupt, 32 bits per word, 31 words */
220 uint32_t intEnabled[INT_BITS_MAX-1];
221
222 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
223 if (ix == 0) {
224 return getBankedRegs(ctx).intEnabled;
225 } else {
226 return intEnabled[ix - 1];
227 }
228 }
229
230 /** GICD_I{S,C}PENDR{1..31}
231 * interrupt pending bits for global interrupts
232 * 1b per interrupt, 32 bits per word, 31 words */
233 uint32_t pendingInt[INT_BITS_MAX-1];
234
235 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
236 assert(ix < INT_BITS_MAX);
237 if (ix == 0) {
238 return getBankedRegs(ctx).pendingInt;
239 } else {
240 return pendingInt[ix - 1];
241 }
242 }
243
244 /** GICD_I{S,C}ACTIVER{1..31}
245 * interrupt active bits for global interrupts
246 * 1b per interrupt, 32 bits per word, 31 words */
247 uint32_t activeInt[INT_BITS_MAX-1];
248
249 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
250 assert(ix < INT_BITS_MAX);
251 if (ix == 0) {
252 return getBankedRegs(ctx).activeInt;
253 } else {
254 return activeInt[ix - 1];
255 }
256 }
257
258 /** GICD_IGROUPR{1..31}
259 * interrupt group bits for global interrupts
260 * 1b per interrupt, 32 bits per word, 31 words */
261 uint32_t intGroup[INT_BITS_MAX-1];
262
263 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
264 assert(ix < INT_BITS_MAX);
265 if (ix == 0) {
266 return getBankedRegs(ctx).intGroup;
267 } else {
268 return intGroup[ix - 1];
269 }
270 }
271
272 /** read only running priority register, 1 per cpu*/
273 uint32_t iccrpr[CPU_MAX];
274
275 /** GICD_IPRIORITYR{8..255}
276 * an 8 bit priority (lower is higher priority) for each
277 * of the global (not replicated per CPU) interrupts.
278 */
279 uint8_t intPriority[GLOBAL_INT_LINES];
280
281 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
282 assert(ix < INT_LINES_MAX);
283 if (ix < SGI_MAX + PPI_MAX) {
284 return getBankedRegs(ctx).intPriority[ix];
285 } else {
286 return intPriority[ix - (SGI_MAX + PPI_MAX)];
287 }
288 }
289
290 /** GICD_ICFGRn
291 * get 2 bit config associated to an interrupt.
292 */
293 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
294 assert(ix < INT_LINES_MAX);
295 const uint8_t cfg_low = intNumToBit(ix * 2);
296 const uint8_t cfg_hi = cfg_low + 1;
297 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
298 }
299
300 /** GICD_ITARGETSR{8..255}
301 * an 8 bit cpu target id for each global interrupt.
302 */
303 uint8_t cpuTarget[GLOBAL_INT_LINES];
304
305 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
306 assert(ctx < sys->numRunningContexts());
307 assert(ix < INT_LINES_MAX);
308 if (ix < SGI_MAX + PPI_MAX) {
309 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
310 // field returns a value that corresponds only to the processor
311 // reading the register."
312 uint32_t ctx_mask;
313 if (gem5ExtensionsEnabled) {
314 ctx_mask = ctx;
315 } else {
316 // convert the CPU id number into a bit mask
317 ctx_mask = power(2, ctx);
318 }
319 return ctx_mask;
320 } else {
321 return cpuTarget[ix - 32];
322 }
323 }
324
325 /** 2 bit per interrupt signaling if it's level or edge sensitive
326 * and if it is 1:N or N:N */
327 uint32_t intConfig[INT_BITS_MAX*2];
328
329 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
330 if (ix == SPURIOUS_INT) {
331 return false;
332 } else {
333 return bits(getIntConfig(ctx, ix), 1) == 0;
334 }
335 }
336
337 /** CPU enabled */
337 bool isGroup0(ContextID ctx, uint32_t int_num) {
338 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
339 return bits(group_reg, intNumToBit(int_num));
340 }
341
342 /**
343 * This method checks if an interrupt ID must be signaled or has been
344 * signaled as a FIQ to the cpu. It does that by reading:
345 *
346 * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
347 * group1. Only group0 interrupts can be signaled as FIQs.
348 *
349 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
350 * interrupts to a target processor using the FIQ or the IRQ signal
351 */
352 bool isFiq(ContextID ctx, uint32_t int_num) {
353 const bool is_group0 = isGroup0(ctx, int_num);
354 const bool use_fiq = cpuControl[ctx].fiqEn;
355
356 if (is_group0 && use_fiq) {
357 return true;
358 } else {
359 return false;
360 }
361 }
362
363 /** CPU enabled:
364 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
365 */
338 bool cpuEnabled(ContextID ctx) const {
339 return cpuControl[ctx].enableGrp0 ||
340 cpuControl[ctx].enableGrp1;
341 }
342
343 /** GICC_CTLR:
344 * CPU interface control register
345 */
346 CTLR cpuControl[CPU_MAX];
347
348 /** CPU priority */
349 uint8_t cpuPriority[CPU_MAX];
350 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
351
352 /** Binary point registers */
353 uint8_t cpuBpr[CPU_MAX];
354
355 /** highest interrupt that is interrupting CPU */
356 uint32_t cpuHighestInt[CPU_MAX];
357
358 /** One bit per cpu per software interrupt that is pending for each
359 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
360 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
361 * interrupt for CPU 2. */
362 uint64_t cpuSgiPending[SGI_MAX];
363 uint64_t cpuSgiActive[SGI_MAX];
364
365 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
366 * 16 SGI pending bits for each of the (large number of) CPUs.
367 */
368 uint32_t cpuSgiPendingExt[CPU_MAX];
369 uint32_t cpuSgiActiveExt[CPU_MAX];
370
371 /** One bit per private peripheral interrupt. Only upper 16 bits
372 * will be used since PPI interrupts are numberred from 16 to 32 */
373 uint32_t cpuPpiPending[CPU_MAX];
374 uint32_t cpuPpiActive[CPU_MAX];
375
376 /** software generated interrupt
377 * @param data data to decode that indicates which cpus to interrupt
378 */
379 void softInt(ContextID ctx, SWI swi);
380
381 /** See if some processor interrupt flags need to be enabled/disabled
382 * @param hint which set of interrupts needs to be checked
383 */
384 virtual void updateIntState(int hint);
385
386 /** Update the register that records priority of the highest priority
387 * active interrupt*/
388 void updateRunPri();
389
390 /** generate a bit mask to check cpuSgi for an interrupt. */
391 uint64_t genSwiMask(int cpu);
392
393 int intNumToWord(int num) const { return num >> 5; }
394 int intNumToBit(int num) const { return num % 32; }
395
366 bool cpuEnabled(ContextID ctx) const {
367 return cpuControl[ctx].enableGrp0 ||
368 cpuControl[ctx].enableGrp1;
369 }
370
371 /** GICC_CTLR:
372 * CPU interface control register
373 */
374 CTLR cpuControl[CPU_MAX];
375
376 /** CPU priority */
377 uint8_t cpuPriority[CPU_MAX];
378 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
379
380 /** Binary point registers */
381 uint8_t cpuBpr[CPU_MAX];
382
383 /** highest interrupt that is interrupting CPU */
384 uint32_t cpuHighestInt[CPU_MAX];
385
386 /** One bit per cpu per software interrupt that is pending for each
387 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
388 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
389 * interrupt for CPU 2. */
390 uint64_t cpuSgiPending[SGI_MAX];
391 uint64_t cpuSgiActive[SGI_MAX];
392
393 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
394 * 16 SGI pending bits for each of the (large number of) CPUs.
395 */
396 uint32_t cpuSgiPendingExt[CPU_MAX];
397 uint32_t cpuSgiActiveExt[CPU_MAX];
398
399 /** One bit per private peripheral interrupt. Only upper 16 bits
400 * will be used since PPI interrupts are numberred from 16 to 32 */
401 uint32_t cpuPpiPending[CPU_MAX];
402 uint32_t cpuPpiActive[CPU_MAX];
403
404 /** software generated interrupt
405 * @param data data to decode that indicates which cpus to interrupt
406 */
407 void softInt(ContextID ctx, SWI swi);
408
409 /** See if some processor interrupt flags need to be enabled/disabled
410 * @param hint which set of interrupts needs to be checked
411 */
412 virtual void updateIntState(int hint);
413
414 /** Update the register that records priority of the highest priority
415 * active interrupt*/
416 void updateRunPri();
417
418 /** generate a bit mask to check cpuSgi for an interrupt. */
419 uint64_t genSwiMask(int cpu);
420
421 int intNumToWord(int num) const { return num >> 5; }
422 int intNumToBit(int num) const { return num % 32; }
423
424 /** Clears a cpu IRQ or FIQ signal */
425 void clearInt(ContextID ctx, uint32_t int_num);
426
396 /**
397 * Post an interrupt to a CPU with a delay
398 */
399 void postInt(uint32_t cpu, Tick when);
400 void postFiq(uint32_t cpu, Tick when);
401
402 /**
403 * Deliver a delayed interrupt to the target CPU
404 */
405 void postDelayedInt(uint32_t cpu);
406 void postDelayedFiq(uint32_t cpu);
407
408 EventFunctionWrapper *postIntEvent[CPU_MAX];
409 EventFunctionWrapper *postFiqEvent[CPU_MAX];
410 int pendingDelayedInterrupts;
411
412 public:
413 typedef GicV2Params Params;
414 const Params *
415 params() const
416 {
417 return dynamic_cast<const Params *>(_params);
418 }
419 GicV2(const Params *p);
420 ~GicV2();
421
422 DrainState drain() override;
423 void drainResume() override;
424
425 void serialize(CheckpointOut &cp) const override;
426 void unserialize(CheckpointIn &cp) override;
427
428 public: /* PioDevice */
429 AddrRangeList getAddrRanges() const override { return addrRanges; }
430
431 /** A PIO read to the device, immediately split up into
432 * readDistributor() or readCpu()
433 */
434 Tick read(PacketPtr pkt) override;
435
436 /** A PIO read to the device, immediately split up into
437 * writeDistributor() or writeCpu()
438 */
439 Tick write(PacketPtr pkt) override;
440
441 public: /* BaseGic */
442 void sendInt(uint32_t number) override;
443 void clearInt(uint32_t number) override;
444
445 void sendPPInt(uint32_t num, uint32_t cpu) override;
446 void clearPPInt(uint32_t num, uint32_t cpu) override;
447
448 protected:
449 /** Handle a read to the distributor portion of the GIC
450 * @param pkt packet to respond to
451 */
452 Tick readDistributor(PacketPtr pkt);
453 uint32_t readDistributor(ContextID ctx, Addr daddr,
454 size_t resp_sz);
455 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
456 return readDistributor(ctx, daddr, 4);
457 }
458
459 /** Handle a read to the cpu portion of the GIC
460 * @param pkt packet to respond to
461 */
462 Tick readCpu(PacketPtr pkt);
463 uint32_t readCpu(ContextID ctx, Addr daddr) override;
464
465 /** Handle a write to the distributor portion of the GIC
466 * @param pkt packet to respond to
467 */
468 Tick writeDistributor(PacketPtr pkt);
469 void writeDistributor(ContextID ctx, Addr daddr,
470 uint32_t data, size_t data_sz);
471 void writeDistributor(ContextID ctx, Addr daddr,
472 uint32_t data) override {
473 return writeDistributor(ctx, daddr, data, 4);
474 }
475
476 /** Handle a write to the cpu portion of the GIC
477 * @param pkt packet to respond to
478 */
479 Tick writeCpu(PacketPtr pkt);
480 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
481};
482
483#endif //__DEV_ARM_GIC_H__
427 /**
428 * Post an interrupt to a CPU with a delay
429 */
430 void postInt(uint32_t cpu, Tick when);
431 void postFiq(uint32_t cpu, Tick when);
432
433 /**
434 * Deliver a delayed interrupt to the target CPU
435 */
436 void postDelayedInt(uint32_t cpu);
437 void postDelayedFiq(uint32_t cpu);
438
439 EventFunctionWrapper *postIntEvent[CPU_MAX];
440 EventFunctionWrapper *postFiqEvent[CPU_MAX];
441 int pendingDelayedInterrupts;
442
443 public:
444 typedef GicV2Params Params;
445 const Params *
446 params() const
447 {
448 return dynamic_cast<const Params *>(_params);
449 }
450 GicV2(const Params *p);
451 ~GicV2();
452
453 DrainState drain() override;
454 void drainResume() override;
455
456 void serialize(CheckpointOut &cp) const override;
457 void unserialize(CheckpointIn &cp) override;
458
459 public: /* PioDevice */
460 AddrRangeList getAddrRanges() const override { return addrRanges; }
461
462 /** A PIO read to the device, immediately split up into
463 * readDistributor() or readCpu()
464 */
465 Tick read(PacketPtr pkt) override;
466
467 /** A PIO read to the device, immediately split up into
468 * writeDistributor() or writeCpu()
469 */
470 Tick write(PacketPtr pkt) override;
471
472 public: /* BaseGic */
473 void sendInt(uint32_t number) override;
474 void clearInt(uint32_t number) override;
475
476 void sendPPInt(uint32_t num, uint32_t cpu) override;
477 void clearPPInt(uint32_t num, uint32_t cpu) override;
478
479 protected:
480 /** Handle a read to the distributor portion of the GIC
481 * @param pkt packet to respond to
482 */
483 Tick readDistributor(PacketPtr pkt);
484 uint32_t readDistributor(ContextID ctx, Addr daddr,
485 size_t resp_sz);
486 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
487 return readDistributor(ctx, daddr, 4);
488 }
489
490 /** Handle a read to the cpu portion of the GIC
491 * @param pkt packet to respond to
492 */
493 Tick readCpu(PacketPtr pkt);
494 uint32_t readCpu(ContextID ctx, Addr daddr) override;
495
496 /** Handle a write to the distributor portion of the GIC
497 * @param pkt packet to respond to
498 */
499 Tick writeDistributor(PacketPtr pkt);
500 void writeDistributor(ContextID ctx, Addr daddr,
501 uint32_t data, size_t data_sz);
502 void writeDistributor(ContextID ctx, Addr daddr,
503 uint32_t data) override {
504 return writeDistributor(ctx, daddr, data, 4);
505 }
506
507 /** Handle a write to the cpu portion of the GIC
508 * @param pkt packet to respond to
509 */
510 Tick writeCpu(PacketPtr pkt);
511 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
512};
513
514#endif //__DEV_ARM_GIC_H__