1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementation of a GICv2
46 */
47
48#ifndef __DEV_ARM_GICV2_H__
49#define __DEV_ARM_GICV2_H__
50
51#include <vector>
52
53#include "base/addr_range.hh"
54#include "base/bitunion.hh"
55#include "cpu/intr_control.hh"
56#include "dev/arm/base_gic.hh"
57#include "dev/io_device.hh"
58#include "dev/platform.hh"
59#include "params/GicV2.hh"
60
61class GicV2 : public BaseGic, public BaseGicRegisters
62{
63 protected:
64 // distributor memory addresses
65 enum {
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
74
75 DIST_SIZE = 0x1000,
76 };
77
78 /**
79 * As defined in:
80 * "ARM Generic Interrupt Controller Architecture" version 2.0
81 * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
82 */
83 static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490;
84 static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B;
85 static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B;
86
87 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
88 static const AddrRange GICD_ISENABLER; // interrupt set enable
89 static const AddrRange GICD_ICENABLER; // interrupt clear enable
90 static const AddrRange GICD_ISPENDR; // set pending interrupt
91 static const AddrRange GICD_ICPENDR; // clear pending interrupt
92 static const AddrRange GICD_ISACTIVER; // active bit registers
93 static const AddrRange GICD_ICACTIVER; // clear bit registers
94 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
95 static const AddrRange GICD_ITARGETSR; // processor target registers
96 static const AddrRange GICD_ICFGR; // interrupt config registers
97
98 // cpu memory addresses
99 enum {
100 GICC_CTLR = 0x00, // CPU control register
101 GICC_PMR = 0x04, // Interrupt priority mask
102 GICC_BPR = 0x08, // binary point register
103 GICC_IAR = 0x0C, // interrupt ack register
104 GICC_EOIR = 0x10, // end of interrupt
105 GICC_RPR = 0x14, // running priority
106 GICC_HPPIR = 0x18, // highest pending interrupt
107 GICC_ABPR = 0x1c, // aliased binary point
108 GICC_APR0 = 0xd0, // active priority register 0
109 GICC_APR1 = 0xd4, // active priority register 1
110 GICC_APR2 = 0xd8, // active priority register 2
111 GICC_APR3 = 0xdc, // active priority register 3
112 GICC_IIDR = 0xfc, // cpu interface id register
113 };
114
115 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
116 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
117
118 /** Mask off SGI's when setting/clearing pending bits */
119 static const int SGI_MASK = 0xFFFF0000;
120
121 /** Mask for bits that config N:N mode in GICD_ICFGR's */
122 static const int NN_CONFIG_MASK = 0x55555555;
123
124 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
125 static const int SPURIOUS_INT = 1023;
126 static const int INT_BITS_MAX = 32;
127 static const int INT_LINES_MAX = 1020;
128 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
129
130 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
131 chosen for consistency with Linux's in-kernel KVM GIC model */
132 static const int GICC_BPR_MINIMUM = 2;
133
134 BitUnion32(SWI)
135 Bitfield<3,0> sgi_id;
136 Bitfield<23,16> cpu_list;
137 Bitfield<25,24> list_type;
138 EndBitUnion(SWI)
139
140 BitUnion32(IAR)
141 Bitfield<9,0> ack_id;
142 Bitfield<12,10> cpu_id;
143 EndBitUnion(IAR)
144
145 BitUnion32(CTLR)
146 Bitfield<3> fiqEn;
147 Bitfield<1> enableGrp1;
148 Bitfield<0> enableGrp0;
149 EndBitUnion(CTLR)
150
151 protected: /* Params */
152 /** Address range for the distributor interface */
153 const AddrRange distRange;
154
155 /** Address range for the CPU interfaces */
156 const AddrRange cpuRange;
157
158 /** All address ranges used by this GIC */
159 const AddrRangeList addrRanges;
160
161 /** Latency for a distributor operation */
162 const Tick distPioDelay;
163
164 /** Latency for a cpu operation */
165 const Tick cpuPioDelay;
166
167 /** Latency for a interrupt to get to CPU */
168 const Tick intLatency;
169
170 protected:
171 /** Gic enabled */
172 bool enabled;
173
174 /** Are gem5 extensions available? */
175 const bool haveGem5Extensions;
176
177 /** gem5 many-core extension enabled by driver */
178 bool gem5ExtensionsEnabled;
179
180 /** Number of itLines enabled */
181 uint32_t itLines;
182
183 /** Registers "banked for each connected processor" per ARM IHI0048B */
184 struct BankedRegs : public Serializable {
185 /** GICD_I{S,C}ENABLER0
186 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
187 uint32_t intEnabled;
188
189 /** GICD_I{S,C}PENDR0
190 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
191 uint32_t pendingInt;
192
193 /** GICD_I{S,C}ACTIVER0
194 * interrupt active bits for first 32 interrupts, 1b per interrupt */
195 uint32_t activeInt;
196
197 /** GICD_IPRIORITYR{0..7}
198 * interrupt priority for SGIs and PPIs */
199 uint8_t intPriority[SGI_MAX + PPI_MAX];
200
201 void serialize(CheckpointOut &cp) const override;
202 void unserialize(CheckpointIn &cp) override;
203
204 BankedRegs() :
205 intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
206 {}
207 };
208 std::vector<BankedRegs*> bankedRegs;
209
210 BankedRegs& getBankedRegs(ContextID);
211
212 /** GICD_I{S,C}ENABLER{1..31}
213 * interrupt enable bits for global interrupts
214 * 1b per interrupt, 32 bits per word, 31 words */
215 uint32_t intEnabled[INT_BITS_MAX-1];
216
217 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
218 if (ix == 0) {
219 return getBankedRegs(ctx).intEnabled;
220 } else {
221 return intEnabled[ix - 1];
222 }
223 }
224
225 /** GICD_I{S,C}PENDR{1..31}
226 * interrupt pending bits for global interrupts
227 * 1b per interrupt, 32 bits per word, 31 words */
228 uint32_t pendingInt[INT_BITS_MAX-1];
229
230 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
231 assert(ix < INT_BITS_MAX);
232 if (ix == 0) {
233 return getBankedRegs(ctx).pendingInt;
234 } else {
235 return pendingInt[ix - 1];
236 }
237 }
238
239 /** GICD_I{S,C}ACTIVER{1..31}
240 * interrupt active bits for global interrupts
241 * 1b per interrupt, 32 bits per word, 31 words */
242 uint32_t activeInt[INT_BITS_MAX-1];
243
244 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
245 assert(ix < INT_BITS_MAX);
246 if (ix == 0) {
247 return getBankedRegs(ctx).activeInt;
248 } else {
249 return activeInt[ix - 1];
250 }
251 }
252
253 /** read only running priority register, 1 per cpu*/
254 uint32_t iccrpr[CPU_MAX];
255
256 /** GICD_IPRIORITYR{8..255}
257 * an 8 bit priority (lower is higher priority) for each
258 * of the global (not replicated per CPU) interrupts.
259 */
260 uint8_t intPriority[GLOBAL_INT_LINES];
261
262 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
263 assert(ix < INT_LINES_MAX);
264 if (ix < SGI_MAX + PPI_MAX) {
265 return getBankedRegs(ctx).intPriority[ix];
266 } else {
267 return intPriority[ix - (SGI_MAX + PPI_MAX)];
268 }
269 }
270
271 /** GICD_ICFGRn
272 * get 2 bit config associated to an interrupt.
273 */
274 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
275 assert(ix < INT_LINES_MAX);
276 const uint8_t cfg_low = intNumToBit(ix * 2);
277 const uint8_t cfg_hi = cfg_low + 1;
278 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
279 }
280
281 /** GICD_ITARGETSR{8..255}
282 * an 8 bit cpu target id for each global interrupt.
283 */
284 uint8_t cpuTarget[GLOBAL_INT_LINES];
285
286 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
287 assert(ctx < sys->numRunningContexts());
288 assert(ix < INT_LINES_MAX);
289 if (ix < SGI_MAX + PPI_MAX) {
290 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
291 // field returns a value that corresponds only to the processor
292 // reading the register."
293 uint32_t ctx_mask;
294 if (gem5ExtensionsEnabled) {
295 ctx_mask = ctx;
296 } else {
297 // convert the CPU id number into a bit mask
298 ctx_mask = power(2, ctx);
299 }
300 return ctx_mask;
301 } else {
302 return cpuTarget[ix - 32];
303 }
304 }
305
306 /** 2 bit per interrupt signaling if it's level or edge sensitive
307 * and if it is 1:N or N:N */
308 uint32_t intConfig[INT_BITS_MAX*2];
309
310 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
311 if (ix == SPURIOUS_INT) {
312 return false;
313 } else {
314 return bits(getIntConfig(ctx, ix), 1) == 0;
315 }
316 }
317
318 /** CPU enabled */
319 bool cpuEnabled(ContextID ctx) const {
320 return cpuControl[ctx].enableGrp0 ||
321 cpuControl[ctx].enableGrp1;
322 }
323
324 /** GICC_CTLR:
325 * CPU interface control register
326 */
327 CTLR cpuControl[CPU_MAX];
328
329 /** CPU priority */
330 uint8_t cpuPriority[CPU_MAX];
331 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
332
333 /** Binary point registers */
334 uint8_t cpuBpr[CPU_MAX];
335
336 /** highest interrupt that is interrupting CPU */
337 uint32_t cpuHighestInt[CPU_MAX];
338
339 /** One bit per cpu per software interrupt that is pending for each
340 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
341 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
342 * interrupt for CPU 2. */
343 uint64_t cpuSgiPending[SGI_MAX];
344 uint64_t cpuSgiActive[SGI_MAX];
345
346 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
347 * 16 SGI pending bits for each of the (large number of) CPUs.
348 */
349 uint32_t cpuSgiPendingExt[CPU_MAX];
350 uint32_t cpuSgiActiveExt[CPU_MAX];
351
352 /** One bit per private peripheral interrupt. Only upper 16 bits
353 * will be used since PPI interrupts are numberred from 16 to 32 */
354 uint32_t cpuPpiPending[CPU_MAX];
355 uint32_t cpuPpiActive[CPU_MAX];
356
357 /** software generated interrupt
358 * @param data data to decode that indicates which cpus to interrupt
359 */
360 void softInt(ContextID ctx, SWI swi);
361
362 /** See if some processor interrupt flags need to be enabled/disabled
363 * @param hint which set of interrupts needs to be checked
364 */
365 virtual void updateIntState(int hint);
366
367 /** Update the register that records priority of the highest priority
368 * active interrupt*/
369 void updateRunPri();
370
371 /** generate a bit mask to check cpuSgi for an interrupt. */
372 uint64_t genSwiMask(int cpu);
373
374 int intNumToWord(int num) const { return num >> 5; }
375 int intNumToBit(int num) const { return num % 32; }
376
377 /**
378 * Post an interrupt to a CPU with a delay
379 */
380 void postInt(uint32_t cpu, Tick when);
381
382 /**
383 * Deliver a delayed interrupt to the target CPU
384 */
385 void postDelayedInt(uint32_t cpu);
386
387 EventFunctionWrapper *postIntEvent[CPU_MAX];
388 int pendingDelayedInterrupts;
389
390 public:
391 typedef GicV2Params Params;
392 const Params *
393 params() const
394 {
395 return dynamic_cast<const Params *>(_params);
396 }
397 GicV2(const Params *p);
398 ~GicV2();
399
400 DrainState drain() override;
401 void drainResume() override;
402
403 void serialize(CheckpointOut &cp) const override;
404 void unserialize(CheckpointIn &cp) override;
405
406 public: /* PioDevice */
407 AddrRangeList getAddrRanges() const override { return addrRanges; }
408
409 /** A PIO read to the device, immediately split up into
410 * readDistributor() or readCpu()
411 */
412 Tick read(PacketPtr pkt) override;
413
414 /** A PIO read to the device, immediately split up into
415 * writeDistributor() or writeCpu()
416 */
417 Tick write(PacketPtr pkt) override;
418
419 public: /* BaseGic */
420 void sendInt(uint32_t number) override;
421 void clearInt(uint32_t number) override;
422
423 void sendPPInt(uint32_t num, uint32_t cpu) override;
424 void clearPPInt(uint32_t num, uint32_t cpu) override;
425
426 protected:
427 /** Handle a read to the distributor portion of the GIC
428 * @param pkt packet to respond to
429 */
430 Tick readDistributor(PacketPtr pkt);
431 uint32_t readDistributor(ContextID ctx, Addr daddr,
432 size_t resp_sz);
433 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
434 return readDistributor(ctx, daddr, 4);
435 }
436
437 /** Handle a read to the cpu portion of the GIC
438 * @param pkt packet to respond to
439 */
440 Tick readCpu(PacketPtr pkt);
441 uint32_t readCpu(ContextID ctx, Addr daddr) override;
442
443 /** Handle a write to the distributor portion of the GIC
444 * @param pkt packet to respond to
445 */
446 Tick writeDistributor(PacketPtr pkt);
447 void writeDistributor(ContextID ctx, Addr daddr,
448 uint32_t data, size_t data_sz);
449 void writeDistributor(ContextID ctx, Addr daddr,
450 uint32_t data) override {
451 return writeDistributor(ctx, daddr, data, 4);
452 }
453
454 /** Handle a write to the cpu portion of the GIC
455 * @param pkt packet to respond to
456 */
457 Tick writeCpu(PacketPtr pkt);
458 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
459};
460
461#endif //__DEV_ARM_GIC_H__