1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 320 unchanged lines hidden (view full) ---

329 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
330 if (ix == SPURIOUS_INT) {
331 return false;
332 } else {
333 return bits(getIntConfig(ctx, ix), 1) == 0;
334 }
335 }
336
337 /** CPU enabled */
338 bool cpuEnabled(ContextID ctx) const {
339 return cpuControl[ctx].enableGrp0 ||
340 cpuControl[ctx].enableGrp1;
341 }
342
343 /** GICC_CTLR:
344 * CPU interface control register
345 */

--- 42 unchanged lines hidden (view full) ---

388 void updateRunPri();
389
390 /** generate a bit mask to check cpuSgi for an interrupt. */
391 uint64_t genSwiMask(int cpu);
392
393 int intNumToWord(int num) const { return num >> 5; }
394 int intNumToBit(int num) const { return num % 32; }
395
396 /**
397 * Post an interrupt to a CPU with a delay
398 */
399 void postInt(uint32_t cpu, Tick when);
400 void postFiq(uint32_t cpu, Tick when);
401
402 /**
403 * Deliver a delayed interrupt to the target CPU

--- 80 unchanged lines hidden ---