gic_v2.cc (13503:43d086278416) gic_v2.cc (13505:e699fce12780)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x37f);
60const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x3ff);
61const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x7ff);
62const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
63const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff);
64
65GicV2::GicV2(const Params *p)
66 : BaseGic(p),
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x37f);
60const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x3ff);
61const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x7ff);
62const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
63const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff);
64
65GicV2::GicV2(const Params *p)
66 : BaseGic(p),
67 gicdPIDR(p->gicd_pidr),
68 gicdIIDR(p->gicd_iidr),
69 giccIIDR(p->gicc_iidr),
67 distRange(RangeSize(p->dist_addr, DIST_SIZE)),
68 cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
69 addrRanges{distRange, cpuRange},
70 distPioDelay(p->dist_pio_delay),
71 cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
72 enabled(false), haveGem5Extensions(p->gem5_extensions),
73 itLines(p->it_lines),
74 intEnabled {}, pendingInt {}, activeInt {},

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263 /* The 0x100 is a made-up flag to show that gem5 extensions
264 * are available,
265 * write 0x200 to this register to enable it. */
266 return (((sys->numRunningContexts() - 1) << 5) |
267 (itLines/INT_BITS_MAX -1) |
268 (haveGem5Extensions ? 0x100 : 0x0));
269 case GICD_PIDR0:
270 //ARM defined DevID
70 distRange(RangeSize(p->dist_addr, DIST_SIZE)),
71 cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
72 addrRanges{distRange, cpuRange},
73 distPioDelay(p->dist_pio_delay),
74 cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
75 enabled(false), haveGem5Extensions(p->gem5_extensions),
76 itLines(p->it_lines),
77 intEnabled {}, pendingInt {}, activeInt {},

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266 /* The 0x100 is a made-up flag to show that gem5 extensions
267 * are available,
268 * write 0x200 to this register to enable it. */
269 return (((sys->numRunningContexts() - 1) << 5) |
270 (itLines/INT_BITS_MAX -1) |
271 (haveGem5Extensions ? 0x100 : 0x0));
272 case GICD_PIDR0:
273 //ARM defined DevID
271 return (GICD_400_PIDR_VALUE & 0xFF);
274 return (gicdPIDR & 0xFF);
272 case GICD_PIDR1:
275 case GICD_PIDR1:
273 return ((GICD_400_PIDR_VALUE >> 8) & 0xFF);
276 return ((gicdPIDR >> 8) & 0xFF);
274 case GICD_PIDR2:
277 case GICD_PIDR2:
275 return ((GICD_400_PIDR_VALUE >> 16) & 0xFF);
278 return ((gicdPIDR >> 16) & 0xFF);
276 case GICD_PIDR3:
279 case GICD_PIDR3:
277 return ((GICD_400_PIDR_VALUE >> 24) & 0xFF);
280 return ((gicdPIDR >> 24) & 0xFF);
278 case GICD_IIDR:
279 /* revision id is resorted to 1 and variant to 0*/
281 case GICD_IIDR:
282 /* revision id is resorted to 1 and variant to 0*/
280 return GICD_400_IIDR_VALUE;
283 return gicdIIDR;
281 default:
282 panic("Tried to read Gic distributor at offset %#x\n", daddr);
283 break;
284 }
285}
286
287Tick
288GicV2::readCpu(PacketPtr pkt)

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302 return cpuPioDelay;
303}
304
305uint32_t
306GicV2::readCpu(ContextID ctx, Addr daddr)
307{
308 switch(daddr) {
309 case GICC_IIDR:
284 default:
285 panic("Tried to read Gic distributor at offset %#x\n", daddr);
286 break;
287 }
288}
289
290Tick
291GicV2::readCpu(PacketPtr pkt)

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305 return cpuPioDelay;
306}
307
308uint32_t
309GicV2::readCpu(ContextID ctx, Addr daddr)
310{
311 switch(daddr) {
312 case GICC_IIDR:
310 return GICC_400_IIDR_VALUE;
313 return giccIIDR;
311 case GICC_CTLR:
312 return cpuControl[ctx];
313 case GICC_PMR:
314 return cpuPriority[ctx];
315 case GICC_BPR:
316 return cpuBpr[ctx];
317 case GICC_IAR:
318 if (enabled && cpuEnabled(ctx)) {

--- 767 unchanged lines hidden --- 		314 case GICC_CTLR:
315 return cpuControl[ctx];
316 case GICC_PMR:
317 return cpuPriority[ctx];
318 case GICC_BPR:
319 return cpuBpr[ctx];
320 case GICC_IAR:
321 if (enabled && cpuEnabled(ctx)) {

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