gic_v2.cc (13111:74ef47d9c035) gic_v2.cc (13112:c31596a933a3)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 350 unchanged lines hidden (view full) ---

359 }
360 }
361
362 DPRINTF(Interrupt,
363 "CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
364 ctx, iar.ack_id, iar.cpu_id, iar);
365 cpuHighestInt[ctx] = SPURIOUS_INT;
366 updateIntState(-1);
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 350 unchanged lines hidden (view full) ---

359 }
360 }
361
362 DPRINTF(Interrupt,
363 "CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
364 ctx, iar.ack_id, iar.cpu_id, iar);
365 cpuHighestInt[ctx] = SPURIOUS_INT;
366 updateIntState(-1);
367 platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
367 clearInt(ctx, active_int);
368 return iar;
369 } else {
370 return SPURIOUS_INT;
371 }
372
373 break;
374 case GICC_RPR:
375 return iccrpr[0];

--- 421 unchanged lines hidden (view full) ---

797
798 uint32_t prev_highest = cpuHighestInt[cpu];
799 cpuHighestInt[cpu] = highest_int;
800
801 if (highest_int == SPURIOUS_INT) {
802 if (isLevelSensitive(cpu, prev_highest)) {
803
804 DPRINTF(Interrupt, "Clear IRQ for cpu%d\n", cpu);
368 return iar;
369 } else {
370 return SPURIOUS_INT;
371 }
372
373 break;
374 case GICC_RPR:
375 return iccrpr[0];

--- 421 unchanged lines hidden (view full) ---

797
798 uint32_t prev_highest = cpuHighestInt[cpu];
799 cpuHighestInt[cpu] = highest_int;
800
801 if (highest_int == SPURIOUS_INT) {
802 if (isLevelSensitive(cpu, prev_highest)) {
803
804 DPRINTF(Interrupt, "Clear IRQ for cpu%d\n", cpu);
805 platform->intrctrl->clear(cpu, ArmISA::INT_IRQ, 0);
805 clearInt(cpu, prev_highest);
806 }
807 continue;
808 }
809
810 /* @todo make this work for more than one cpu, need to handle 1:N, N:N
811 * models */
812 if (enabled && cpuEnabled(cpu) &&
813 (highest_pri < getCpuPriority(cpu)) &&
814 !(getActiveInt(cpu, intNumToWord(highest_int))
815 & (1 << intNumToBit(highest_int)))) {
816
817 DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n", highest_int,
818 cpu);
806 }
807 continue;
808 }
809
810 /* @todo make this work for more than one cpu, need to handle 1:N, N:N
811 * models */
812 if (enabled && cpuEnabled(cpu) &&
813 (highest_pri < getCpuPriority(cpu)) &&
814 !(getActiveInt(cpu, intNumToWord(highest_int))
815 & (1 << intNumToBit(highest_int)))) {
816
817 DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n", highest_int,
818 cpu);
819 postInt(cpu, curTick() + intLatency);
819
820 if (isFiq(cpu, highest_int)) {
821 postFiq(cpu, curTick() + intLatency);
822 } else {
823 postInt(cpu, curTick() + intLatency);
824 }
820 }
821 }
822}
823
824void
825GicV2::updateRunPri()
826{
827 for (int cpu = 0; cpu < sys->numContexts(); cpu++) {

--- 69 unchanged lines hidden (view full) ---

897{
898 DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
899 num, cpu);
900 cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
901 updateIntState(intNumToWord(num));
902}
903
904void
825 }
826 }
827}
828
829void
830GicV2::updateRunPri()
831{
832 for (int cpu = 0; cpu < sys->numContexts(); cpu++) {

--- 69 unchanged lines hidden (view full) ---

902{
903 DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
904 num, cpu);
905 cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
906 updateIntState(intNumToWord(num));
907}
908
909void
910GicV2::clearInt(ContextID ctx, uint32_t int_num)
911{
912 if (isFiq(ctx, int_num)) {
913 platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
914 } else {
915 platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
916 }
917}
918
919void
905GicV2::postInt(uint32_t cpu, Tick when)
906{
907 if (!(postIntEvent[cpu]->scheduled())) {
908 ++pendingDelayedInterrupts;
909 eventq->schedule(postIntEvent[cpu], when);
910 }
911}
912

--- 155 unchanged lines hidden --- 		920GicV2::postInt(uint32_t cpu, Tick when)
921{
922 if (!(postIntEvent[cpu]->scheduled())) {
923 ++pendingDelayedInterrupts;
924 eventq->schedule(postIntEvent[cpu], when);
925 }
926}
927

--- 155 unchanged lines hidden ---