gic_v2.cc (13110:f7fcb16be5ab) gic_v2.cc (13111:74ef47d9c035)
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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83 cpuControl[x] = 0;
84 cpuPriority[x] = 0xff;
85 cpuBpr[x] = GICC_BPR_MINIMUM;
86 // Initialize cpu highest int
87 cpuHighestInt[x] = SPURIOUS_INT;
88 postIntEvent[x] =
89 new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
90 "Post Interrupt to CPU");
1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 74 unchanged lines hidden (view full) ---

83 cpuControl[x] = 0;
84 cpuPriority[x] = 0xff;
85 cpuBpr[x] = GICC_BPR_MINIMUM;
86 // Initialize cpu highest int
87 cpuHighestInt[x] = SPURIOUS_INT;
88 postIntEvent[x] =
89 new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
90 "Post Interrupt to CPU");
91 postFiqEvent[x] =
92 new EventFunctionWrapper([this, x]{ postDelayedFiq(x); },
93 "Post FIQ to CPU");
91 }
92 DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled(0),
93 cpuEnabled(1));
94
95 gem5ExtensionsEnabled = false;
96}
97
98GicV2::~GicV2()
99{
94 }
95 DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled(0),
96 cpuEnabled(1));
97
98 gem5ExtensionsEnabled = false;
99}
100
101GicV2::~GicV2()
102{
100 for (int x = 0; x < CPU_MAX; x++)
103 for (int x = 0; x < CPU_MAX; x++) {
101 delete postIntEvent[x];
104 delete postIntEvent[x];
105 delete postFiqEvent[x];
106 }
102}
103
104Tick
105GicV2::read(PacketPtr pkt)
106{
107 const Addr addr = pkt->getAddr();
108
109 if (distRange.contains(addr))

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910{
911 platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
912 --pendingDelayedInterrupts;
913 assert(pendingDelayedInterrupts >= 0);
914 if (pendingDelayedInterrupts == 0)
915 signalDrainDone();
916}
917
107}
108
109Tick
110GicV2::read(PacketPtr pkt)
111{
112 const Addr addr = pkt->getAddr();
113
114 if (distRange.contains(addr))

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915{
916 platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
917 --pendingDelayedInterrupts;
918 assert(pendingDelayedInterrupts >= 0);
919 if (pendingDelayedInterrupts == 0)
920 signalDrainDone();
921}
922
923void
924GicV2::postFiq(uint32_t cpu, Tick when)
925{
926 if (!(postFiqEvent[cpu]->scheduled())) {
927 ++pendingDelayedInterrupts;
928 eventq->schedule(postFiqEvent[cpu], when);
929 }
930}
931
932void
933GicV2::postDelayedFiq(uint32_t cpu)
934{
935 platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
936 --pendingDelayedInterrupts;
937 assert(pendingDelayedInterrupts >= 0);
938 if (pendingDelayedInterrupts == 0)
939 signalDrainDone();
940}
941
918DrainState
919GicV2::drain()
920{
921 if (pendingDelayedInterrupts == 0) {
922 return DrainState::Drained;
923 } else {
924 return DrainState::Draining;
925 }

--- 118 unchanged lines hidden --- 		942DrainState
943GicV2::drain()
944{
945 if (pendingDelayedInterrupts == 0) {
946 return DrainState::Drained;
947 } else {
948 return DrainState::Draining;
949 }

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