1/* 2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 147 unchanged lines hidden (view full) --- 156 pkt->makeAtomicResponse(); 157 return distPioDelay; 158} 159 160uint32_t 161GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) 162{ 163 if (GICD_IGROUPR.contains(daddr)) { |
164 uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2; 165 assert(ix < 32); 166 return getIntGroup(ctx, ix); |
167 } 168 169 if (GICD_ISENABLER.contains(daddr)) { 170 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2; 171 assert(ix < 32); 172 return getIntEnabled(ctx, ix); 173 } 174 --- 237 unchanged lines hidden (view full) --- 412 return distPioDelay; 413} 414 415void 416GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data, 417 size_t data_sz) 418{ 419 if (GICD_IGROUPR.contains(daddr)) { |
420 uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2; 421 assert(ix < 32); 422 getIntGroup(ctx, ix) |= data; 423 return; |
424 } 425 426 if (GICD_ISENABLER.contains(daddr)) { 427 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2; 428 assert(ix < 32); 429 getIntEnabled(ctx, ix) |= data; 430 return; 431 } --- 506 unchanged lines hidden (view full) --- 938{ 939 DPRINTF(Checkpoint, "Serializing Arm GIC\n"); 940 941 SERIALIZE_SCALAR(enabled); 942 SERIALIZE_SCALAR(itLines); 943 SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1); 944 SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1); 945 SERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1); |
946 SERIALIZE_ARRAY(intGroup, INT_BITS_MAX-1); |
947 SERIALIZE_ARRAY(iccrpr, CPU_MAX); 948 SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES); 949 SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES); 950 SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2); 951 SERIALIZE_ARRAY(cpuControl, CPU_MAX); 952 SERIALIZE_ARRAY(cpuPriority, CPU_MAX); 953 SERIALIZE_ARRAY(cpuBpr, CPU_MAX); 954 SERIALIZE_ARRAY(cpuHighestInt, CPU_MAX); --- 13 unchanged lines hidden (view full) --- 968} 969 970void 971GicV2::BankedRegs::serialize(CheckpointOut &cp) const 972{ 973 SERIALIZE_SCALAR(intEnabled); 974 SERIALIZE_SCALAR(pendingInt); 975 SERIALIZE_SCALAR(activeInt); |
976 SERIALIZE_SCALAR(intGroup); |
977 SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX); 978} 979 980void 981GicV2::unserialize(CheckpointIn &cp) 982{ 983 DPRINTF(Checkpoint, "Unserializing Arm GIC\n"); 984 985 UNSERIALIZE_SCALAR(enabled); 986 UNSERIALIZE_SCALAR(itLines); 987 UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1); 988 UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1); 989 UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1); |
990 UNSERIALIZE_ARRAY(intGroup, INT_BITS_MAX-1); |
991 UNSERIALIZE_ARRAY(iccrpr, CPU_MAX); 992 UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES); 993 UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES); 994 UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2); 995 UNSERIALIZE_ARRAY(cpuControl, CPU_MAX); 996 UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX); 997 UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX); 998 UNSERIALIZE_ARRAY(cpuHighestInt, CPU_MAX); --- 28 unchanged lines hidden (view full) --- 1027} 1028 1029void 1030GicV2::BankedRegs::unserialize(CheckpointIn &cp) 1031{ 1032 UNSERIALIZE_SCALAR(intEnabled); 1033 UNSERIALIZE_SCALAR(pendingInt); 1034 UNSERIALIZE_SCALAR(activeInt); |
1035 UNSERIALIZE_SCALAR(intGroup); |
1036 UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX); 1037} 1038 1039GicV2 * 1040GicV2Params::create() 1041{ 1042 return new GicV2(this); 1043} |