1/*
2 * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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156 pkt->makeAtomicResponse();
157 return distPioDelay;
158}
159
160uint32_t
161GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
162{
163 if (GICD_IGROUPR.contains(daddr)) {
164 return 0; // unimplemented; RAZ (read as zero)
165 }
166
167 if (GICD_ISENABLER.contains(daddr)) {
168 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
169 assert(ix < 32);
170 return getIntEnabled(ctx, ix);
171 }
172

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410 return distPioDelay;
411}
412
413void
414GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
415 size_t data_sz)
416{
417 if (GICD_IGROUPR.contains(daddr)) {
418 return; // unimplemented; WI (writes ignored)
419 }
420
421 if (GICD_ISENABLER.contains(daddr)) {
422 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
423 assert(ix < 32);
424 getIntEnabled(ctx, ix) |= data;
425 return;
426 }

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933{
934 DPRINTF(Checkpoint, "Serializing Arm GIC\n");
935
936 SERIALIZE_SCALAR(enabled);
937 SERIALIZE_SCALAR(itLines);
938 SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
939 SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
940 SERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
941 SERIALIZE_ARRAY(iccrpr, CPU_MAX);
942 SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
943 SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
944 SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
945 SERIALIZE_ARRAY(cpuControl, CPU_MAX);
946 SERIALIZE_ARRAY(cpuPriority, CPU_MAX);
947 SERIALIZE_ARRAY(cpuBpr, CPU_MAX);
948 SERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);

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962}
963
964void
965GicV2::BankedRegs::serialize(CheckpointOut &cp) const
966{
967 SERIALIZE_SCALAR(intEnabled);
968 SERIALIZE_SCALAR(pendingInt);
969 SERIALIZE_SCALAR(activeInt);
970 SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
971}
972
973void
974GicV2::unserialize(CheckpointIn &cp)
975{
976 DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
977
978 UNSERIALIZE_SCALAR(enabled);
979 UNSERIALIZE_SCALAR(itLines);
980 UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
981 UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
982 UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
983 UNSERIALIZE_ARRAY(iccrpr, CPU_MAX);
984 UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
985 UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
986 UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
987 UNSERIALIZE_ARRAY(cpuControl, CPU_MAX);
988 UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX);
989 UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX);
990 UNSERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);

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1019}
1020
1021void
1022GicV2::BankedRegs::unserialize(CheckpointIn &cp)
1023{
1024 UNSERIALIZE_SCALAR(intEnabled);
1025 UNSERIALIZE_SCALAR(pendingInt);
1026 UNSERIALIZE_SCALAR(activeInt);
1027 UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
1028}
1029
1030GicV2 *
1031GicV2Params::create()
1032{
1033 return new GicV2(this);
1034}