generic_timer.hh (12975:f521b0fcc17c) generic_timer.hh (13557:fc33e6048b25)
1/*
2 * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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218 const GenericTimerParams * params() const;
219
220 GenericTimer(GenericTimerParams *p);
221
222 void serialize(CheckpointOut &cp) const override;
223 void unserialize(CheckpointIn &cp) override;
224
225 public:
1/*
2 * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 209 unchanged lines hidden (view full) ---

218 const GenericTimerParams * params() const;
219
220 GenericTimer(GenericTimerParams *p);
221
222 void serialize(CheckpointOut &cp) const override;
223 void unserialize(CheckpointIn &cp) override;
224
225 public:
226 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
227 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
227 RegVal readMiscReg(int misc_reg, unsigned cpu);
228
229 protected:
230 struct CoreTimers {
231 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
232 ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
233 ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
234 : irqPhysS(_irqPhysS),
235 irqPhysNS(_irqPhysNS),

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281};
282
283class GenericTimerISA : public ArmISA::BaseISADevice
284{
285 public:
286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
287 : parent(_parent), cpu(_cpu) {}
288
228
229 protected:
230 struct CoreTimers {
231 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
232 ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
233 ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
234 : irqPhysS(_irqPhysS),
235 irqPhysNS(_irqPhysNS),

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281};
282
283class GenericTimerISA : public ArmISA::BaseISADevice
284{
285 public:
286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
287 : parent(_parent), cpu(_cpu) {}
288
289 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
290 ArmISA::MiscReg readMiscReg(int misc_reg) override;
289 void setMiscReg(int misc_reg, RegVal val) override;
290 RegVal readMiscReg(int misc_reg) override;
291
292 protected:
293 GenericTimer &parent;
294 unsigned cpu;
295};
296
297class GenericTimerMem : public PioDevice
298{

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292 protected:
293 GenericTimer &parent;
294 unsigned cpu;
295};
296
297class GenericTimerMem : public PioDevice
298{

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