generic_timer.hh (12971:a7fbe4a6eed7) generic_timer.hh (12975:f521b0fcc17c)
1/*
2 * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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106 private:
107 // Disable copying
108 SystemCounter(const SystemCounter &c);
109};
110
111/// Per-CPU architected timer.
112class ArchTimer : public Serializable, public Drainable
113{
1/*
2 * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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106 private:
107 // Disable copying
108 SystemCounter(const SystemCounter &c);
109};
110
111/// Per-CPU architected timer.
112class ArchTimer : public Serializable, public Drainable
113{
114 public:
115 class Interrupt
116 {
117 public:
118 Interrupt(BaseGic &gic, unsigned irq)
119 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
120
121 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
122 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
123
124 void send();
125 void clear();
126
127 private:
128 BaseGic &_gic;
129 const bool _ppi;
130 const unsigned _irq;
131 const unsigned _cpu;
132 };
133
134 protected:
135 /// Control register.
136 BitUnion32(ArchTimerCtrl)
137 Bitfield<0> enable;
138 Bitfield<1> imask;
139 Bitfield<2> istatus;
140 EndBitUnion(ArchTimerCtrl)
141
142 /// Name of this timer.
143 const std::string _name;
144
145 /// Pointer to parent class.
146 SimObject &_parent;
147
148 SystemCounter &_systemCounter;
149
114 protected:
115 /// Control register.
116 BitUnion32(ArchTimerCtrl)
117 Bitfield<0> enable;
118 Bitfield<1> imask;
119 Bitfield<2> istatus;
120 EndBitUnion(ArchTimerCtrl)
121
122 /// Name of this timer.
123 const std::string _name;
124
125 /// Pointer to parent class.
126 SimObject &_parent;
127
128 SystemCounter &_systemCounter;
129
150 Interrupt _interrupt;
130 ArmInterruptPin * const _interrupt;
151
152 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
153 ArchTimerCtrl _control;
154 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
155 uint64_t _counterLimit;
156 /// Offset relative to the physical timer (CNTVOFF)
157 uint64_t _offset;
158

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167 EventFunctionWrapper _counterLimitReachedEvent;
168
169 virtual bool scheduleEvents() { return true; }
170
171 public:
172 ArchTimer(const std::string &name,
173 SimObject &parent,
174 SystemCounter &sysctr,
131
132 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
133 ArchTimerCtrl _control;
134 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
135 uint64_t _counterLimit;
136 /// Offset relative to the physical timer (CNTVOFF)
137 uint64_t _offset;
138

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147 EventFunctionWrapper _counterLimitReachedEvent;
148
149 virtual bool scheduleEvents() { return true; }
150
151 public:
152 ArchTimer(const std::string &name,
153 SimObject &parent,
154 SystemCounter &sysctr,
175 const Interrupt &interrupt);
155 ArmInterruptPin *interrupt);
176
177 /// Returns the timer name.
178 std::string name() const { return _name; }
179
180 /// Returns the CompareValue view of the timer.
181 uint64_t compareValue() const { return _counterLimit; }
182 /// Sets the CompareValue view of the timer.
183 void setCompareValue(uint64_t val);

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215 private:
216 ArmSystem &system;
217
218 public:
219 ArchTimerKvm(const std::string &name,
220 ArmSystem &system,
221 SimObject &parent,
222 SystemCounter &sysctr,
156
157 /// Returns the timer name.
158 std::string name() const { return _name; }
159
160 /// Returns the CompareValue view of the timer.
161 uint64_t compareValue() const { return _counterLimit; }
162 /// Sets the CompareValue view of the timer.
163 void setCompareValue(uint64_t val);

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195 private:
196 ArmSystem &system;
197
198 public:
199 ArchTimerKvm(const std::string &name,
200 ArmSystem &system,
201 SimObject &parent,
202 SystemCounter &sysctr,
223 const Interrupt &interrupt)
203 ArmInterruptPin *interrupt)
224 : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
225
226 protected:
227 // For ArchTimer's in a GenericTimerISA with Kvm execution about
228 // to begin, skip rescheduling the event.
229 // Otherwise, we should reschedule the event (if necessary).
230 bool scheduleEvents() override {
231 return !system.validKvmEnvironment();
232 }
233};
234
235class GenericTimer : public ClockedObject
236{
237 public:
204 : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
205
206 protected:
207 // For ArchTimer's in a GenericTimerISA with Kvm execution about
208 // to begin, skip rescheduling the event.
209 // Otherwise, we should reschedule the event (if necessary).
210 bool scheduleEvents() override {
211 return !system.validKvmEnvironment();
212 }
213};
214
215class GenericTimer : public ClockedObject
216{
217 public:
218 const GenericTimerParams * params() const;
219
238 GenericTimer(GenericTimerParams *p);
239
240 void serialize(CheckpointOut &cp) const override;
241 void unserialize(CheckpointIn &cp) override;
242
243 public:
244 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
245 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
246
247 protected:
248 struct CoreTimers {
249 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
220 GenericTimer(GenericTimerParams *p);
221
222 void serialize(CheckpointOut &cp) const override;
223 void unserialize(CheckpointIn &cp) override;
224
225 public:
226 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
227 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
228
229 protected:
230 struct CoreTimers {
231 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
250 unsigned _irqPhysS, unsigned _irqPhysNS,
251 unsigned _irqVirt, unsigned _irqHyp)
252 : irqPhysS(*parent.gic, _irqPhysS, cpu),
253 irqPhysNS(*parent.gic, _irqPhysNS, cpu),
254 irqVirt(*parent.gic, _irqVirt, cpu),
255 irqHyp(*parent.gic, _irqHyp, cpu),
232 ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
233 ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
234 : irqPhysS(_irqPhysS),
235 irqPhysNS(_irqPhysNS),
236 irqVirt(_irqVirt),
237 irqHyp(_irqHyp),
256 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
257 system, parent, parent.systemCounter,
238 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
239 system, parent, parent.systemCounter,
258 irqPhysS),
240 _irqPhysS),
259 // This should really be phys_timerN, but we are stuck with
260 // arch_timer for backwards compatibility.
261 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
262 system, parent, parent.systemCounter,
241 // This should really be phys_timerN, but we are stuck with
242 // arch_timer for backwards compatibility.
243 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
244 system, parent, parent.systemCounter,
263 irqPhysNS),
245 _irqPhysNS),
264 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
265 system, parent, parent.systemCounter,
246 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
247 system, parent, parent.systemCounter,
266 irqVirt),
248 _irqVirt),
267 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
268 system, parent, parent.systemCounter,
249 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
250 system, parent, parent.systemCounter,
269 irqHyp)
251 _irqHyp)
270 {}
271
252 {}
253
272 ArchTimer::Interrupt irqPhysS;
273 ArchTimer::Interrupt irqPhysNS;
274 ArchTimer::Interrupt irqVirt;
275 ArchTimer::Interrupt irqHyp;
254 ArmInterruptPin const *irqPhysS;
255 ArmInterruptPin const *irqPhysNS;
256 ArmInterruptPin const *irqVirt;
257 ArmInterruptPin const *irqHyp;
276
277 ArchTimerKvm physS;
278 ArchTimerKvm physNS;
279 ArchTimerKvm virt;
280 ArchTimerKvm hyp;
281
282 private:
283 // Disable copying

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291 SystemCounter systemCounter;
292
293 /// Per-CPU physical architected timers.
294 std::vector<std::unique_ptr<CoreTimers>> timers;
295
296 protected: // Configuration
297 /// ARM system containing this timer
298 ArmSystem &system;
258
259 ArchTimerKvm physS;
260 ArchTimerKvm physNS;
261 ArchTimerKvm virt;
262 ArchTimerKvm hyp;
263
264 private:
265 // Disable copying

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273 SystemCounter systemCounter;
274
275 /// Per-CPU physical architected timers.
276 std::vector<std::unique_ptr<CoreTimers>> timers;
277
278 protected: // Configuration
279 /// ARM system containing this timer
280 ArmSystem &system;
299
300 /// Pointer to the GIC, needed to trigger timer interrupts.
301 BaseGic *const gic;
302
303 /// Physical timer interrupt (S)
304 const unsigned irqPhysS;
305 /// Physical timer interrupt (NS)
306 const unsigned irqPhysNS;
307
308 /// Virtual timer interrupt
309 const unsigned irqVirt;
310
311 /// Hypervisor timer interrupt
312 const unsigned irqHyp;
313};
314
315class GenericTimerISA : public ArmISA::BaseISADevice
316{
317 public:
318 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
319 : parent(_parent), cpu(_cpu) {}
320

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282
283class GenericTimerISA : public ArmISA::BaseISADevice
284{
285 public:
286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
287 : parent(_parent), cpu(_cpu) {}
288

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