generic_timer.hh (12467:087fab1b0e54) generic_timer.hh (12733:fd6b0c5419aa)
1/*
2 * Copyright (c) 2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64 protected:
65 /// Counter frequency (as specified by CNTFRQ).
66 uint64_t _freq;
67 /// Cached copy of the counter period (inverse of the frequency).
68 Tick _period;
69 /// Tick when the counter was reset.
70 Tick _resetTick;
71
1/*
2 * Copyright (c) 2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 55 unchanged lines hidden (view full) ---

64 protected:
65 /// Counter frequency (as specified by CNTFRQ).
66 uint64_t _freq;
67 /// Cached copy of the counter period (inverse of the frequency).
68 Tick _period;
69 /// Tick when the counter was reset.
70 Tick _resetTick;
71
72 /// Kernel event stream control register
72 uint32_t _regCntkctl;
73 uint32_t _regCntkctl;
74 /// Hypervisor event stream control register
75 uint32_t _regCnthctl;
73
74 public:
75 SystemCounter();
76
77 /// Returns the current value of the physical counter.
78 uint64_t value() const
79 {
80 if (_freq == 0)

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89 void setFreq(uint32_t freq);
90
91 /// Returns the counter period.
92 Tick period() const { return _period; }
93
94 void setKernelControl(uint32_t val) { _regCntkctl = val; }
95 uint32_t getKernelControl() { return _regCntkctl; }
96
76
77 public:
78 SystemCounter();
79
80 /// Returns the current value of the physical counter.
81 uint64_t value() const
82 {
83 if (_freq == 0)

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92 void setFreq(uint32_t freq);
93
94 /// Returns the counter period.
95 Tick period() const { return _period; }
96
97 void setKernelControl(uint32_t val) { _regCntkctl = val; }
98 uint32_t getKernelControl() { return _regCntkctl; }
99
100 void setHypControl(uint32_t val) { _regCnthctl = val; }
101 uint32_t getHypControl() { return _regCnthctl; }
102
97 void serialize(CheckpointOut &cp) const override;
98 void unserialize(CheckpointIn &cp) override;
99
100 private:
101 // Disable copying
102 SystemCounter(const SystemCounter &c);
103};
104

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236
237 public:
238 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
239 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
240
241 protected:
242 struct CoreTimers {
243 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
103 void serialize(CheckpointOut &cp) const override;
104 void unserialize(CheckpointIn &cp) override;
105
106 private:
107 // Disable copying
108 SystemCounter(const SystemCounter &c);
109};
110

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242
243 public:
244 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
245 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
246
247 protected:
248 struct CoreTimers {
249 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
244 unsigned _irqPhys, unsigned _irqVirt)
245 : irqPhys(*parent.gic, _irqPhys, cpu),
250 unsigned _irqPhysS, unsigned _irqPhysNS,
251 unsigned _irqVirt, unsigned _irqHyp)
252 : irqPhysS(*parent.gic, _irqPhysS, cpu),
253 irqPhysNS(*parent.gic, _irqPhysNS, cpu),
246 irqVirt(*parent.gic, _irqVirt, cpu),
254 irqVirt(*parent.gic, _irqVirt, cpu),
255 irqHyp(*parent.gic, _irqHyp, cpu),
256 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
257 system, parent, parent.systemCounter,
258 irqPhysS),
247 // This should really be phys_timerN, but we are stuck with
248 // arch_timer for backwards compatibility.
259 // This should really be phys_timerN, but we are stuck with
260 // arch_timer for backwards compatibility.
249 phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
250 system, parent, parent.systemCounter,
251 irqPhys),
261 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
262 system, parent, parent.systemCounter,
263 irqPhysNS),
252 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
253 system, parent, parent.systemCounter,
264 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
265 system, parent, parent.systemCounter,
254 irqVirt)
266 irqVirt),
267 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
268 system, parent, parent.systemCounter,
269 irqHyp)
255 {}
256
270 {}
271
257 ArchTimer::Interrupt irqPhys;
272 ArchTimer::Interrupt irqPhysS;
273 ArchTimer::Interrupt irqPhysNS;
258 ArchTimer::Interrupt irqVirt;
274 ArchTimer::Interrupt irqVirt;
275 ArchTimer::Interrupt irqHyp;
259
276
260 ArchTimerKvm phys;
277 ArchTimerKvm physS;
278 ArchTimerKvm physNS;
261 ArchTimerKvm virt;
279 ArchTimerKvm virt;
280 ArchTimerKvm hyp;
262
263 private:
264 // Disable copying
265 CoreTimers(const CoreTimers &c);
266 };
267
268 CoreTimers &getTimers(int cpu_id);
269 void createTimers(unsigned cpus);

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276
277 protected: // Configuration
278 /// ARM system containing this timer
279 ArmSystem &system;
280
281 /// Pointer to the GIC, needed to trigger timer interrupts.
282 BaseGic *const gic;
283
281
282 private:
283 // Disable copying
284 CoreTimers(const CoreTimers &c);
285 };
286
287 CoreTimers &getTimers(int cpu_id);
288 void createTimers(unsigned cpus);

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295
296 protected: // Configuration
297 /// ARM system containing this timer
298 ArmSystem &system;
299
300 /// Pointer to the GIC, needed to trigger timer interrupts.
301 BaseGic *const gic;
302
284 /// Physical timer interrupt
285 const unsigned irqPhys;
303 /// Physical timer interrupt (S)
304 const unsigned irqPhysS;
305 /// Physical timer interrupt (NS)
306 const unsigned irqPhysNS;
286
287 /// Virtual timer interrupt
288 const unsigned irqVirt;
307
308 /// Virtual timer interrupt
309 const unsigned irqVirt;
310
311 /// Hypervisor timer interrupt
312 const unsigned irqHyp;
289};
290
291class GenericTimerISA : public ArmISA::BaseISADevice
292{
293 public:
294 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
295 : parent(_parent), cpu(_cpu) {}
296

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314
315class GenericTimerISA : public ArmISA::BaseISADevice
316{
317 public:
318 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
319 : parent(_parent), cpu(_cpu) {}
320

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