generic_timer.hh (10905:a6ca6831e775) generic_timer.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 void setFreq(uint32_t freq);
89
90 /// Returns the counter period.
91 Tick period() const { return _period; }
92
93 void setKernelControl(uint32_t val) { _regCntkctl = val; }
94 uint32_t getKernelControl() { return _regCntkctl; }
95
1/*
2 * Copyright (c) 2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 79 unchanged lines hidden (view full) ---

88 void setFreq(uint32_t freq);
89
90 /// Returns the counter period.
91 Tick period() const { return _period; }
92
93 void setKernelControl(uint32_t val) { _regCntkctl = val; }
94 uint32_t getKernelControl() { return _regCntkctl; }
95
96 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
97 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
96 void serialize(CheckpointOut &cp) const override;
97 void unserialize(CheckpointIn &cp) override;
98
99 private:
100 // Disable copying
101 SystemCounter(const SystemCounter &c);
102};
103
104/// Per-CPU architected timer.
105class ArchTimer : public Serializable

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184 void setControl(uint32_t val);
185
186 uint64_t offset() const { return _offset; }
187 void setOffset(uint64_t val);
188
189 /// Returns the value of the counter which this timer relies on.
190 uint64_t value() const;
191
98
99 private:
100 // Disable copying
101 SystemCounter(const SystemCounter &c);
102};
103
104/// Per-CPU architected timer.
105class ArchTimer : public Serializable

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184 void setControl(uint32_t val);
185
186 uint64_t offset() const { return _offset; }
187 void setOffset(uint64_t val);
188
189 /// Returns the value of the counter which this timer relies on.
190 uint64_t value() const;
191
192 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
193 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
192 void serialize(CheckpointOut &cp) const override;
193 void unserialize(CheckpointIn &cp) override;
194
195 private:
196 // Disable copying
197 ArchTimer(const ArchTimer &t);
198};
199
200class GenericTimer : public SimObject
201{
202 public:
203 GenericTimer(GenericTimerParams *p);
204
194
195 private:
196 // Disable copying
197 ArchTimer(const ArchTimer &t);
198};
199
200class GenericTimer : public SimObject
201{
202 public:
203 GenericTimer(GenericTimerParams *p);
204
205 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
206 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
205 void serialize(CheckpointOut &cp) const override;
206 void unserialize(CheckpointIn &cp) override;
207
208 public:
209 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
210 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
211
212 protected:
213 struct CoreTimers {
214 CoreTimers(GenericTimer &parent, unsigned cpu,

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257};
258
259class GenericTimerISA : public ArmISA::BaseISADevice
260{
261 public:
262 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
263 : parent(_parent), cpu(_cpu) {}
264
207
208 public:
209 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
210 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
211
212 protected:
213 struct CoreTimers {
214 CoreTimers(GenericTimer &parent, unsigned cpu,

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257};
258
259class GenericTimerISA : public ArmISA::BaseISADevice
260{
261 public:
262 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
263 : parent(_parent), cpu(_cpu) {}
264
265 void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE {
265 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
266 parent.setMiscReg(misc_reg, cpu, val);
267 }
266 parent.setMiscReg(misc_reg, cpu, val);
267 }
268 ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE {
268 ArmISA::MiscReg readMiscReg(int misc_reg) override {
269 return parent.readMiscReg(misc_reg, cpu);
270 }
271
272 protected:
273 GenericTimer &parent;
274 unsigned cpu;
275};
276
277class GenericTimerMem : public PioDevice
278{
279 public:
280 GenericTimerMem(GenericTimerMemParams *p);
281
269 return parent.readMiscReg(misc_reg, cpu);
270 }
271
272 protected:
273 GenericTimer &parent;
274 unsigned cpu;
275};
276
277class GenericTimerMem : public PioDevice
278{
279 public:
280 GenericTimerMem(GenericTimerMemParams *p);
281
282 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
283 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
282 void serialize(CheckpointOut &cp) const override;
283 void unserialize(CheckpointIn &cp) override;
284
285 public: // PioDevice
284
285 public: // PioDevice
286 AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; }
287 Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
288 Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
286 AddrRangeList getAddrRanges() const override { return addrRanges; }
287 Tick read(PacketPtr pkt) override;
288 Tick write(PacketPtr pkt) override;
289
290 protected:
291 uint64_t ctrlRead(Addr addr, size_t size) const;
292 void ctrlWrite(Addr addr, size_t size, uint64_t value);
293
294 uint64_t timerRead(Addr addr, size_t size) const;
295 void timerWrite(Addr addr, size_t size, uint64_t value);
296

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290 protected:
291 uint64_t ctrlRead(Addr addr, size_t size) const;
292 void ctrlWrite(Addr addr, size_t size, uint64_t value);
293
294 uint64_t timerRead(Addr addr, size_t size) const;
295 void timerWrite(Addr addr, size_t size, uint64_t value);
296

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