1/* 2 * Copyright (c) 2013, 2015, 2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 55 unchanged lines hidden (view full) --- 64 protected: 65 /// Counter frequency (as specified by CNTFRQ). 66 uint64_t _freq; 67 /// Cached copy of the counter period (inverse of the frequency). 68 Tick _period; 69 /// Tick when the counter was reset. 70 Tick _resetTick; 71 |
72 /// Kernel event stream control register |
73 uint32_t _regCntkctl; |
74 /// Hypervisor event stream control register 75 uint32_t _regCnthctl; |
76 77 public: 78 SystemCounter(); 79 80 /// Returns the current value of the physical counter. 81 uint64_t value() const 82 { 83 if (_freq == 0) --- 8 unchanged lines hidden (view full) --- 92 void setFreq(uint32_t freq); 93 94 /// Returns the counter period. 95 Tick period() const { return _period; } 96 97 void setKernelControl(uint32_t val) { _regCntkctl = val; } 98 uint32_t getKernelControl() { return _regCntkctl; } 99 |
100 void setHypControl(uint32_t val) { _regCnthctl = val; } 101 uint32_t getHypControl() { return _regCnthctl; } 102 |
103 void serialize(CheckpointOut &cp) const override; 104 void unserialize(CheckpointIn &cp) override; 105 106 private: 107 // Disable copying 108 SystemCounter(const SystemCounter &c); 109}; 110 --- 131 unchanged lines hidden (view full) --- 242 243 public: 244 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); 245 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); 246 247 protected: 248 struct CoreTimers { 249 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu, |
250 unsigned _irqPhysS, unsigned _irqPhysNS, 251 unsigned _irqVirt, unsigned _irqHyp) 252 : irqPhysS(*parent.gic, _irqPhysS, cpu), 253 irqPhysNS(*parent.gic, _irqPhysNS, cpu), |
254 irqVirt(*parent.gic, _irqVirt, cpu), |
255 irqHyp(*parent.gic, _irqHyp, cpu), 256 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu), 257 system, parent, parent.systemCounter, 258 irqPhysS), |
259 // This should really be phys_timerN, but we are stuck with 260 // arch_timer for backwards compatibility. |
261 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu), 262 system, parent, parent.systemCounter, 263 irqPhysNS), |
264 virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 265 system, parent, parent.systemCounter, |
266 irqVirt), 267 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu), 268 system, parent, parent.systemCounter, 269 irqHyp) |
270 {} 271 |
272 ArchTimer::Interrupt irqPhysS; 273 ArchTimer::Interrupt irqPhysNS; |
274 ArchTimer::Interrupt irqVirt; |
275 ArchTimer::Interrupt irqHyp; |
276 |
277 ArchTimerKvm physS; 278 ArchTimerKvm physNS; |
279 ArchTimerKvm virt; |
280 ArchTimerKvm hyp; |
281 282 private: 283 // Disable copying 284 CoreTimers(const CoreTimers &c); 285 }; 286 287 CoreTimers &getTimers(int cpu_id); 288 void createTimers(unsigned cpus); --- 6 unchanged lines hidden (view full) --- 295 296 protected: // Configuration 297 /// ARM system containing this timer 298 ArmSystem &system; 299 300 /// Pointer to the GIC, needed to trigger timer interrupts. 301 BaseGic *const gic; 302 |
303 /// Physical timer interrupt (S) 304 const unsigned irqPhysS; 305 /// Physical timer interrupt (NS) 306 const unsigned irqPhysNS; |
307 308 /// Virtual timer interrupt 309 const unsigned irqVirt; |
310 311 /// Hypervisor timer interrupt 312 const unsigned irqHyp; |
313}; 314 315class GenericTimerISA : public ArmISA::BaseISADevice 316{ 317 public: 318 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 319 : parent(_parent), cpu(_cpu) {} 320 --- 70 unchanged lines hidden --- |