1/*
2 * Copyright (c) 2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 * Andreas Sandberg
39 */
40
41#ifndef __DEV_ARM_GENERIC_TIMER_HH__
42#define __DEV_ARM_GENERIC_TIMER_HH__
43
44#include "arch/arm/isa_device.hh"
45#include "arch/arm/system.hh"
46#include "base/bitunion.hh"
47#include "dev/arm/base_gic.hh"
48#include "sim/core.hh"
49#include "sim/sim_object.hh"
50
51/// @file
52/// This module implements the global system counter and the local per-CPU
53/// architected timers as specified by the ARM Generic Timer extension (ARM
54/// ARM, Issue C, Chapter 17).
55
56class Checkpoint;
57class GenericTimerParams;
58class GenericTimerMemParams;
59
60/// Global system counter. It is shared by the architected timers.
61/// @todo: implement memory-mapped controls
62class SystemCounter : public Serializable
63{
64 protected:
65 /// Counter frequency (as specified by CNTFRQ).
66 uint64_t _freq;
67 /// Cached copy of the counter period (inverse of the frequency).
68 Tick _period;
69 /// Tick when the counter was reset.
70 Tick _resetTick;
71
| 1/*
2 * Copyright (c) 2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 * Andreas Sandberg
39 */
40
41#ifndef __DEV_ARM_GENERIC_TIMER_HH__
42#define __DEV_ARM_GENERIC_TIMER_HH__
43
44#include "arch/arm/isa_device.hh"
45#include "arch/arm/system.hh"
46#include "base/bitunion.hh"
47#include "dev/arm/base_gic.hh"
48#include "sim/core.hh"
49#include "sim/sim_object.hh"
50
51/// @file
52/// This module implements the global system counter and the local per-CPU
53/// architected timers as specified by the ARM Generic Timer extension (ARM
54/// ARM, Issue C, Chapter 17).
55
56class Checkpoint;
57class GenericTimerParams;
58class GenericTimerMemParams;
59
60/// Global system counter. It is shared by the architected timers.
61/// @todo: implement memory-mapped controls
62class SystemCounter : public Serializable
63{
64 protected:
65 /// Counter frequency (as specified by CNTFRQ).
66 uint64_t _freq;
67 /// Cached copy of the counter period (inverse of the frequency).
68 Tick _period;
69 /// Tick when the counter was reset.
70 Tick _resetTick;
71
|
| 72 /// Kernel event stream control register
|
72 uint32_t _regCntkctl;
| 73 uint32_t _regCntkctl;
|
| 74 /// Hypervisor event stream control register
75 uint32_t _regCnthctl;
|
73
74 public:
75 SystemCounter();
76
77 /// Returns the current value of the physical counter.
78 uint64_t value() const
79 {
80 if (_freq == 0)
81 return 0; // Counter is still off.
82 return (curTick() - _resetTick) / _period;
83 }
84
85 /// Returns the counter frequency.
86 uint64_t freq() const { return _freq; }
87 /// Sets the counter frequency.
88 /// @param freq frequency in Hz.
89 void setFreq(uint32_t freq);
90
91 /// Returns the counter period.
92 Tick period() const { return _period; }
93
94 void setKernelControl(uint32_t val) { _regCntkctl = val; }
95 uint32_t getKernelControl() { return _regCntkctl; }
96
| 76
77 public:
78 SystemCounter();
79
80 /// Returns the current value of the physical counter.
81 uint64_t value() const
82 {
83 if (_freq == 0)
84 return 0; // Counter is still off.
85 return (curTick() - _resetTick) / _period;
86 }
87
88 /// Returns the counter frequency.
89 uint64_t freq() const { return _freq; }
90 /// Sets the counter frequency.
91 /// @param freq frequency in Hz.
92 void setFreq(uint32_t freq);
93
94 /// Returns the counter period.
95 Tick period() const { return _period; }
96
97 void setKernelControl(uint32_t val) { _regCntkctl = val; }
98 uint32_t getKernelControl() { return _regCntkctl; }
99
|
| 100 void setHypControl(uint32_t val) { _regCnthctl = val; }
101 uint32_t getHypControl() { return _regCnthctl; }
102
|
97 void serialize(CheckpointOut &cp) const override;
98 void unserialize(CheckpointIn &cp) override;
99
100 private:
101 // Disable copying
102 SystemCounter(const SystemCounter &c);
103};
104
105/// Per-CPU architected timer.
106class ArchTimer : public Serializable, public Drainable
107{
108 public:
109 class Interrupt
110 {
111 public:
112 Interrupt(BaseGic &gic, unsigned irq)
113 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
114
115 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
116 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
117
118 void send();
119 void clear();
120
121 private:
122 BaseGic &_gic;
123 const bool _ppi;
124 const unsigned _irq;
125 const unsigned _cpu;
126 };
127
128 protected:
129 /// Control register.
130 BitUnion32(ArchTimerCtrl)
131 Bitfield<0> enable;
132 Bitfield<1> imask;
133 Bitfield<2> istatus;
134 EndBitUnion(ArchTimerCtrl)
135
136 /// Name of this timer.
137 const std::string _name;
138
139 /// Pointer to parent class.
140 SimObject &_parent;
141
142 SystemCounter &_systemCounter;
143
144 Interrupt _interrupt;
145
146 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
147 ArchTimerCtrl _control;
148 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
149 uint64_t _counterLimit;
150 /// Offset relative to the physical timer (CNTVOFF)
151 uint64_t _offset;
152
153 /**
154 * Timer settings or the offset has changed, re-evaluate
155 * trigger condition and raise interrupt if necessary.
156 */
157 void updateCounter();
158
159 /// Called when the upcounter reaches the programmed value.
160 void counterLimitReached();
161 EventFunctionWrapper _counterLimitReachedEvent;
162
163 virtual bool scheduleEvents() { return true; }
164
165 public:
166 ArchTimer(const std::string &name,
167 SimObject &parent,
168 SystemCounter &sysctr,
169 const Interrupt &interrupt);
170
171 /// Returns the timer name.
172 std::string name() const { return _name; }
173
174 /// Returns the CompareValue view of the timer.
175 uint64_t compareValue() const { return _counterLimit; }
176 /// Sets the CompareValue view of the timer.
177 void setCompareValue(uint64_t val);
178
179 /// Returns the TimerValue view of the timer.
180 uint32_t timerValue() const { return _counterLimit - value(); }
181 /// Sets the TimerValue view of the timer.
182 void setTimerValue(uint32_t val);
183
184 /// Sets the control register.
185 uint32_t control() const { return _control; }
186 void setControl(uint32_t val);
187
188 uint64_t offset() const { return _offset; }
189 void setOffset(uint64_t val);
190
191 /// Returns the value of the counter which this timer relies on.
192 uint64_t value() const;
193
194 // Serializable
195 void serialize(CheckpointOut &cp) const override;
196 void unserialize(CheckpointIn &cp) override;
197
198 // Drainable
199 DrainState drain() override;
200 void drainResume() override;
201
202 private:
203 // Disable copying
204 ArchTimer(const ArchTimer &t);
205};
206
207class ArchTimerKvm : public ArchTimer
208{
209 private:
210 ArmSystem &system;
211
212 public:
213 ArchTimerKvm(const std::string &name,
214 ArmSystem &system,
215 SimObject &parent,
216 SystemCounter &sysctr,
217 const Interrupt &interrupt)
218 : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
219
220 protected:
221 // For ArchTimer's in a GenericTimerISA with Kvm execution about
222 // to begin, skip rescheduling the event.
223 // Otherwise, we should reschedule the event (if necessary).
224 bool scheduleEvents() override {
225 return !system.validKvmEnvironment();
226 }
227};
228
229class GenericTimer : public ClockedObject
230{
231 public:
232 GenericTimer(GenericTimerParams *p);
233
234 void serialize(CheckpointOut &cp) const override;
235 void unserialize(CheckpointIn &cp) override;
236
237 public:
238 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
239 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
240
241 protected:
242 struct CoreTimers {
243 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
| 103 void serialize(CheckpointOut &cp) const override;
104 void unserialize(CheckpointIn &cp) override;
105
106 private:
107 // Disable copying
108 SystemCounter(const SystemCounter &c);
109};
110
111/// Per-CPU architected timer.
112class ArchTimer : public Serializable, public Drainable
113{
114 public:
115 class Interrupt
116 {
117 public:
118 Interrupt(BaseGic &gic, unsigned irq)
119 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
120
121 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
122 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
123
124 void send();
125 void clear();
126
127 private:
128 BaseGic &_gic;
129 const bool _ppi;
130 const unsigned _irq;
131 const unsigned _cpu;
132 };
133
134 protected:
135 /// Control register.
136 BitUnion32(ArchTimerCtrl)
137 Bitfield<0> enable;
138 Bitfield<1> imask;
139 Bitfield<2> istatus;
140 EndBitUnion(ArchTimerCtrl)
141
142 /// Name of this timer.
143 const std::string _name;
144
145 /// Pointer to parent class.
146 SimObject &_parent;
147
148 SystemCounter &_systemCounter;
149
150 Interrupt _interrupt;
151
152 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
153 ArchTimerCtrl _control;
154 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
155 uint64_t _counterLimit;
156 /// Offset relative to the physical timer (CNTVOFF)
157 uint64_t _offset;
158
159 /**
160 * Timer settings or the offset has changed, re-evaluate
161 * trigger condition and raise interrupt if necessary.
162 */
163 void updateCounter();
164
165 /// Called when the upcounter reaches the programmed value.
166 void counterLimitReached();
167 EventFunctionWrapper _counterLimitReachedEvent;
168
169 virtual bool scheduleEvents() { return true; }
170
171 public:
172 ArchTimer(const std::string &name,
173 SimObject &parent,
174 SystemCounter &sysctr,
175 const Interrupt &interrupt);
176
177 /// Returns the timer name.
178 std::string name() const { return _name; }
179
180 /// Returns the CompareValue view of the timer.
181 uint64_t compareValue() const { return _counterLimit; }
182 /// Sets the CompareValue view of the timer.
183 void setCompareValue(uint64_t val);
184
185 /// Returns the TimerValue view of the timer.
186 uint32_t timerValue() const { return _counterLimit - value(); }
187 /// Sets the TimerValue view of the timer.
188 void setTimerValue(uint32_t val);
189
190 /// Sets the control register.
191 uint32_t control() const { return _control; }
192 void setControl(uint32_t val);
193
194 uint64_t offset() const { return _offset; }
195 void setOffset(uint64_t val);
196
197 /// Returns the value of the counter which this timer relies on.
198 uint64_t value() const;
199
200 // Serializable
201 void serialize(CheckpointOut &cp) const override;
202 void unserialize(CheckpointIn &cp) override;
203
204 // Drainable
205 DrainState drain() override;
206 void drainResume() override;
207
208 private:
209 // Disable copying
210 ArchTimer(const ArchTimer &t);
211};
212
213class ArchTimerKvm : public ArchTimer
214{
215 private:
216 ArmSystem &system;
217
218 public:
219 ArchTimerKvm(const std::string &name,
220 ArmSystem &system,
221 SimObject &parent,
222 SystemCounter &sysctr,
223 const Interrupt &interrupt)
224 : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
225
226 protected:
227 // For ArchTimer's in a GenericTimerISA with Kvm execution about
228 // to begin, skip rescheduling the event.
229 // Otherwise, we should reschedule the event (if necessary).
230 bool scheduleEvents() override {
231 return !system.validKvmEnvironment();
232 }
233};
234
235class GenericTimer : public ClockedObject
236{
237 public:
238 GenericTimer(GenericTimerParams *p);
239
240 void serialize(CheckpointOut &cp) const override;
241 void unserialize(CheckpointIn &cp) override;
242
243 public:
244 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
245 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
246
247 protected:
248 struct CoreTimers {
249 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu,
|
244 unsigned _irqPhys, unsigned _irqVirt)
245 : irqPhys(*parent.gic, _irqPhys, cpu),
| 250 unsigned _irqPhysS, unsigned _irqPhysNS,
251 unsigned _irqVirt, unsigned _irqHyp)
252 : irqPhysS(*parent.gic, _irqPhysS, cpu),
253 irqPhysNS(*parent.gic, _irqPhysNS, cpu),
|
246 irqVirt(*parent.gic, _irqVirt, cpu),
| 254 irqVirt(*parent.gic, _irqVirt, cpu),
|
| 255 irqHyp(*parent.gic, _irqHyp, cpu),
256 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
257 system, parent, parent.systemCounter,
258 irqPhysS),
|
247 // This should really be phys_timerN, but we are stuck with
248 // arch_timer for backwards compatibility.
| 259 // This should really be phys_timerN, but we are stuck with
260 // arch_timer for backwards compatibility.
|
249 phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
250 system, parent, parent.systemCounter,
251 irqPhys),
| 261 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
262 system, parent, parent.systemCounter,
263 irqPhysNS),
|
252 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
253 system, parent, parent.systemCounter,
| 264 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
265 system, parent, parent.systemCounter,
|
254 irqVirt)
| 266 irqVirt),
267 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
268 system, parent, parent.systemCounter,
269 irqHyp)
|
255 {}
256
| 270 {}
271
|
257 ArchTimer::Interrupt irqPhys;
| 272 ArchTimer::Interrupt irqPhysS;
273 ArchTimer::Interrupt irqPhysNS;
|
258 ArchTimer::Interrupt irqVirt;
| 274 ArchTimer::Interrupt irqVirt;
|
| 275 ArchTimer::Interrupt irqHyp;
|
259
| 276
|
260 ArchTimerKvm phys;
| 277 ArchTimerKvm physS;
278 ArchTimerKvm physNS;
|
261 ArchTimerKvm virt;
| 279 ArchTimerKvm virt;
|
| 280 ArchTimerKvm hyp;
|
262
263 private:
264 // Disable copying
265 CoreTimers(const CoreTimers &c);
266 };
267
268 CoreTimers &getTimers(int cpu_id);
269 void createTimers(unsigned cpus);
270
271 /// System counter.
272 SystemCounter systemCounter;
273
274 /// Per-CPU physical architected timers.
275 std::vector<std::unique_ptr<CoreTimers>> timers;
276
277 protected: // Configuration
278 /// ARM system containing this timer
279 ArmSystem &system;
280
281 /// Pointer to the GIC, needed to trigger timer interrupts.
282 BaseGic *const gic;
283
| 281
282 private:
283 // Disable copying
284 CoreTimers(const CoreTimers &c);
285 };
286
287 CoreTimers &getTimers(int cpu_id);
288 void createTimers(unsigned cpus);
289
290 /// System counter.
291 SystemCounter systemCounter;
292
293 /// Per-CPU physical architected timers.
294 std::vector<std::unique_ptr<CoreTimers>> timers;
295
296 protected: // Configuration
297 /// ARM system containing this timer
298 ArmSystem &system;
299
300 /// Pointer to the GIC, needed to trigger timer interrupts.
301 BaseGic *const gic;
302
|
284 /// Physical timer interrupt
285 const unsigned irqPhys;
| 303 /// Physical timer interrupt (S)
304 const unsigned irqPhysS;
305 /// Physical timer interrupt (NS)
306 const unsigned irqPhysNS;
|
286
287 /// Virtual timer interrupt
288 const unsigned irqVirt;
| 307
308 /// Virtual timer interrupt
309 const unsigned irqVirt;
|
| 310
311 /// Hypervisor timer interrupt
312 const unsigned irqHyp;
|
289};
290
291class GenericTimerISA : public ArmISA::BaseISADevice
292{
293 public:
294 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
295 : parent(_parent), cpu(_cpu) {}
296
297 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
298 parent.setMiscReg(misc_reg, cpu, val);
299 }
300 ArmISA::MiscReg readMiscReg(int misc_reg) override {
301 return parent.readMiscReg(misc_reg, cpu);
302 }
303
304 protected:
305 GenericTimer &parent;
306 unsigned cpu;
307};
308
309class GenericTimerMem : public PioDevice
310{
311 public:
312 GenericTimerMem(GenericTimerMemParams *p);
313
314 void serialize(CheckpointOut &cp) const override;
315 void unserialize(CheckpointIn &cp) override;
316
317 public: // PioDevice
318 AddrRangeList getAddrRanges() const override { return addrRanges; }
319 Tick read(PacketPtr pkt) override;
320 Tick write(PacketPtr pkt) override;
321
322 protected:
323 uint64_t ctrlRead(Addr addr, size_t size) const;
324 void ctrlWrite(Addr addr, size_t size, uint64_t value);
325
326 uint64_t timerRead(Addr addr, size_t size) const;
327 void timerWrite(Addr addr, size_t size, uint64_t value);
328
329 protected: // Registers
330 static const Addr CTRL_CNTFRQ = 0x000;
331 static const Addr CTRL_CNTNSAR = 0x004;
332 static const Addr CTRL_CNTTIDR = 0x008;
333 static const Addr CTRL_CNTACR_BASE = 0x040;
334 static const Addr CTRL_CNTVOFF_LO_BASE = 0x080;
335 static const Addr CTRL_CNTVOFF_HI_BASE = 0x084;
336
337 static const Addr TIMER_CNTPCT_LO = 0x000;
338 static const Addr TIMER_CNTPCT_HI = 0x004;
339 static const Addr TIMER_CNTVCT_LO = 0x008;
340 static const Addr TIMER_CNTVCT_HI = 0x00C;
341 static const Addr TIMER_CNTFRQ = 0x010;
342 static const Addr TIMER_CNTEL0ACR = 0x014;
343 static const Addr TIMER_CNTVOFF_LO = 0x018;
344 static const Addr TIMER_CNTVOFF_HI = 0x01C;
345 static const Addr TIMER_CNTP_CVAL_LO = 0x020;
346 static const Addr TIMER_CNTP_CVAL_HI = 0x024;
347 static const Addr TIMER_CNTP_TVAL = 0x028;
348 static const Addr TIMER_CNTP_CTL = 0x02C;
349 static const Addr TIMER_CNTV_CVAL_LO = 0x030;
350 static const Addr TIMER_CNTV_CVAL_HI = 0x034;
351 static const Addr TIMER_CNTV_TVAL = 0x038;
352 static const Addr TIMER_CNTV_CTL = 0x03C;
353
354 protected: // Params
355 const AddrRange ctrlRange;
356 const AddrRange timerRange;
357 const AddrRangeList addrRanges;
358
359 protected:
360 /// System counter.
361 SystemCounter systemCounter;
362 ArchTimer physTimer;
363 ArchTimer virtTimer;
364};
365
366#endif // __DEV_ARM_GENERIC_TIMER_HH__
| 313};
314
315class GenericTimerISA : public ArmISA::BaseISADevice
316{
317 public:
318 GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
319 : parent(_parent), cpu(_cpu) {}
320
321 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
322 parent.setMiscReg(misc_reg, cpu, val);
323 }
324 ArmISA::MiscReg readMiscReg(int misc_reg) override {
325 return parent.readMiscReg(misc_reg, cpu);
326 }
327
328 protected:
329 GenericTimer &parent;
330 unsigned cpu;
331};
332
333class GenericTimerMem : public PioDevice
334{
335 public:
336 GenericTimerMem(GenericTimerMemParams *p);
337
338 void serialize(CheckpointOut &cp) const override;
339 void unserialize(CheckpointIn &cp) override;
340
341 public: // PioDevice
342 AddrRangeList getAddrRanges() const override { return addrRanges; }
343 Tick read(PacketPtr pkt) override;
344 Tick write(PacketPtr pkt) override;
345
346 protected:
347 uint64_t ctrlRead(Addr addr, size_t size) const;
348 void ctrlWrite(Addr addr, size_t size, uint64_t value);
349
350 uint64_t timerRead(Addr addr, size_t size) const;
351 void timerWrite(Addr addr, size_t size, uint64_t value);
352
353 protected: // Registers
354 static const Addr CTRL_CNTFRQ = 0x000;
355 static const Addr CTRL_CNTNSAR = 0x004;
356 static const Addr CTRL_CNTTIDR = 0x008;
357 static const Addr CTRL_CNTACR_BASE = 0x040;
358 static const Addr CTRL_CNTVOFF_LO_BASE = 0x080;
359 static const Addr CTRL_CNTVOFF_HI_BASE = 0x084;
360
361 static const Addr TIMER_CNTPCT_LO = 0x000;
362 static const Addr TIMER_CNTPCT_HI = 0x004;
363 static const Addr TIMER_CNTVCT_LO = 0x008;
364 static const Addr TIMER_CNTVCT_HI = 0x00C;
365 static const Addr TIMER_CNTFRQ = 0x010;
366 static const Addr TIMER_CNTEL0ACR = 0x014;
367 static const Addr TIMER_CNTVOFF_LO = 0x018;
368 static const Addr TIMER_CNTVOFF_HI = 0x01C;
369 static const Addr TIMER_CNTP_CVAL_LO = 0x020;
370 static const Addr TIMER_CNTP_CVAL_HI = 0x024;
371 static const Addr TIMER_CNTP_TVAL = 0x028;
372 static const Addr TIMER_CNTP_CTL = 0x02C;
373 static const Addr TIMER_CNTV_CVAL_LO = 0x030;
374 static const Addr TIMER_CNTV_CVAL_HI = 0x034;
375 static const Addr TIMER_CNTV_TVAL = 0x038;
376 static const Addr TIMER_CNTV_CTL = 0x03C;
377
378 protected: // Params
379 const AddrRange ctrlRange;
380 const AddrRange timerRange;
381 const AddrRangeList addrRanges;
382
383 protected:
384 /// System counter.
385 SystemCounter systemCounter;
386 ArchTimer physTimer;
387 ArchTimer virtTimer;
388};
389
390#endif // __DEV_ARM_GENERIC_TIMER_HH__
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