a9scu.cc (9808:13ffc0066b76) a9scu.cc (10186:c215b6b513ba)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 48 unchanged lines hidden (view full) ---

57 Addr daddr = pkt->getAddr() - pioAddr;
58 pkt->allocate();
59
60 switch(daddr) {
61 case Control:
62 pkt->set(1); // SCU already enabled
63 break;
64 case Config:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 48 unchanged lines hidden (view full) ---

57 Addr daddr = pkt->getAddr() - pioAddr;
58 pkt->allocate();
59
60 switch(daddr) {
61 case Control:
62 pkt->set(1); // SCU already enabled
63 break;
64 case Config:
65 assert(sys->numContexts() <= 4);
65 /* Without making a completely new SCU, we can use the core count field
66 * as 4 bits and inform the OS of up to 16 CPUs. Although the core
67 * count is technically bits [1:0] only, bits [3:2] are SBZ for future
68 * expansion like this.
69 */
70 if (sys->numContexts() > 4) {
71 warn_once("A9SCU with >4 CPUs is unsupported\n");
72 if (sys->numContexts() > 15)
73 fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts());
74 }
66 int smp_bits, core_cnt;
67 smp_bits = power(2,sys->numContexts()) - 1;
68 core_cnt = sys->numContexts() - 1;
69 pkt->set(smp_bits << 4 | core_cnt);
70 break;
71 default:
72 // Only configuration register is implemented
73 panic("Tried to read SCU at offset %#x\n", daddr);

--- 28 unchanged lines hidden --- 		75 int smp_bits, core_cnt;
76 smp_bits = power(2,sys->numContexts()) - 1;
77 core_cnt = sys->numContexts() - 1;
78 pkt->set(smp_bits << 4 | core_cnt);
79 break;
80 default:
81 // Only configuration register is implemented
82 panic("Tried to read SCU at offset %#x\n", daddr);

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