1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "dev/arm/a9scu.hh"
41
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "mem/packet.hh"
45#include "mem/packet_access.hh"
46#include "sim/system.hh"
47
48A9SCU::A9SCU(Params *p)
49 : BasicPioDevice(p, 0x60)
50{
51}
52
53Tick
54A9SCU::read(PacketPtr pkt)
55{
56 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
57 assert(pkt->getSize() == 4);
58 Addr daddr = pkt->getAddr() - pioAddr;
59
60 switch(daddr) {
61 case Control:
62 pkt->set(1); // SCU already enabled
63 break;
64 case Config:
65 /* Without making a completely new SCU, we can use the core count field
66 * as 4 bits and inform the OS of up to 16 CPUs. Although the core
67 * count is technically bits [1:0] only, bits [3:2] are SBZ for future
68 * expansion like this.
69 */
70 if (sys->numContexts() > 4) {
71 warn_once("A9SCU with >4 CPUs is unsupported\n");
72 if (sys->numContexts() > 15)
73 fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts());
74 }
75 int smp_bits, core_cnt;
76 smp_bits = power(2,sys->numContexts()) - 1;
77 core_cnt = sys->numContexts() - 1;
78 pkt->set(smp_bits << 4 | core_cnt);
79 break;
80 default:
81 // Only configuration register is implemented
82 panic("Tried to read SCU at offset %#x\n", daddr);
83 break;
84 }
85 pkt->makeAtomicResponse();
86 return pioDelay;
87
88}
89
90Tick
91A9SCU::write(PacketPtr pkt)
92{
93 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
94
95 Addr daddr = pkt->getAddr() - pioAddr;
96 switch (daddr) {
97 default:
98 // Nothing implemented at this point
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "dev/arm/a9scu.hh"
41
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "mem/packet.hh"
45#include "mem/packet_access.hh"
46#include "sim/system.hh"
47
48A9SCU::A9SCU(Params *p)
49 : BasicPioDevice(p, 0x60)
50{
51}
52
53Tick
54A9SCU::read(PacketPtr pkt)
55{
56 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
57 assert(pkt->getSize() == 4);
58 Addr daddr = pkt->getAddr() - pioAddr;
59
60 switch(daddr) {
61 case Control:
62 pkt->set(1); // SCU already enabled
63 break;
64 case Config:
65 /* Without making a completely new SCU, we can use the core count field
66 * as 4 bits and inform the OS of up to 16 CPUs. Although the core
67 * count is technically bits [1:0] only, bits [3:2] are SBZ for future
68 * expansion like this.
69 */
70 if (sys->numContexts() > 4) {
71 warn_once("A9SCU with >4 CPUs is unsupported\n");
72 if (sys->numContexts() > 15)
73 fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts());
74 }
75 int smp_bits, core_cnt;
76 smp_bits = power(2,sys->numContexts()) - 1;
77 core_cnt = sys->numContexts() - 1;
78 pkt->set(smp_bits << 4 | core_cnt);
79 break;
80 default:
81 // Only configuration register is implemented
82 panic("Tried to read SCU at offset %#x\n", daddr);
83 break;
84 }
85 pkt->makeAtomicResponse();
86 return pioDelay;
87
88}
89
90Tick
91A9SCU::write(PacketPtr pkt)
92{
93 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
94
95 Addr daddr = pkt->getAddr() - pioAddr;
96 switch (daddr) {
97 default:
98 // Nothing implemented at this point
|