SMMUv3.py (14068:9d3dd2493669) SMMUv3.py (14252:1659a606447f)
1# Copyright (c) 2013, 2018-2019 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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35#
36# Authors: Stan Czerniawski
37# Giacomo Travaglini
38
39from m5.params import *
40from m5.proxy import *
41from m5.util.fdthelper import *
42from m5.SimObject import *
1# Copyright (c) 2013, 2018-2019 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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35#
36# Authors: Stan Czerniawski
37# Giacomo Travaglini
38
39from m5.params import *
40from m5.proxy import *
41from m5.util.fdthelper import *
42from m5.SimObject import *
43from m5.objects.MemObject import MemObject
43from m5.objects.ClockedObject import ClockedObject
44
44
45class SMMUv3SlaveInterface(MemObject):
45class SMMUv3SlaveInterface(ClockedObject):
46 type = 'SMMUv3SlaveInterface'
47 cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
48
49 slave = SlavePort('Device port')
50 ats_master = MasterPort('ATS master port')
51 ats_slave = SlavePort('ATS slave port')
52
53 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')

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68 tlb_lat = Param.Cycles(3, 'Main TLB lookup latency')
69 tlb_slots = Param.Cycles(3, 'Main TLB lookup slots')
70
71 prefetch_enable = Param.Bool(False,
72 'Enable prefetch')
73 prefetch_reserve_last_way = Param.Bool(True,
74 'Reserve last way of the main TLB for prefetched entries')
75
46 type = 'SMMUv3SlaveInterface'
47 cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
48
49 slave = SlavePort('Device port')
50 ats_master = MasterPort('ATS master port')
51 ats_slave = SlavePort('ATS slave port')
52
53 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')

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68 tlb_lat = Param.Cycles(3, 'Main TLB lookup latency')
69 tlb_slots = Param.Cycles(3, 'Main TLB lookup slots')
70
71 prefetch_enable = Param.Bool(False,
72 'Enable prefetch')
73 prefetch_reserve_last_way = Param.Bool(True,
74 'Reserve last way of the main TLB for prefetched entries')
75
76class SMMUv3(MemObject):
76class SMMUv3(ClockedObject):
77 type = 'SMMUv3'
78 cxx_header = 'dev/arm/smmu_v3.hh'
79
80 master = MasterPort('Master port')
81 master_walker = MasterPort(
82 'Master port for SMMU initiated HWTW requests (optional)')
83 control = SlavePort('Control port for accessing memory-mapped registers')
84 sample_period = Param.Clock('10us', 'Stats sample period')

--- 125 unchanged lines hidden --- 		77 type = 'SMMUv3'
78 cxx_header = 'dev/arm/smmu_v3.hh'
79
80 master = MasterPort('Master port')
81 master_walker = MasterPort(
82 'Master port for SMMU initiated HWTW requests (optional)')
83 control = SlavePort('Control port for accessing memory-mapped registers')
84 sample_period = Param.Clock('10us', 'Stats sample period')

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