Cross Reference: /gem5/src/dev/arm/RealView.py

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RealView.py (9806:3f262c18ad5d)	RealView.py (9835:cc7a7fc71c42)
1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 type = 'RealView' 155 cxx_header = "dev/arm/realview.hh" 156 system = Param.System(Parent.any, "system") 157 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 158 mem_start_addr = Param.Addr(0, "Start address of main memory") 159 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 160 161 def setupBootLoader(self, mem_bus, cur_sys, loc):	1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 type = 'RealView' 155 cxx_header = "dev/arm/realview.hh" 156 system = Param.System(Parent.any, "system") 157 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 158 mem_start_addr = Param.Addr(0, "Start address of main memory") 159 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 160 161 def setupBootLoader(self, mem_bus, cur_sys, loc):
162 self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), 163 size = '64MB'))	162 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 163 conf_table_reported = False)
164 self.nvmem.port = mem_bus.master 165 cur_sys.boot_loader = loc('boot.arm') 166 167 168# Reference for memory map and interrupt number 169# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 170# Chapter 4: Programmer's Reference 171class RealViewPBX(RealView): --- 180 unchanged lines hidden (view full) --- 352 pciconfig = PciConfigAll(size='256MB') 353 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 354 InterruptLine=1, InterruptPin=1) 355 356 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 357 InterruptLine=2, InterruptPin=2) 358 359	164 self.nvmem.port = mem_bus.master 165 cur_sys.boot_loader = loc('boot.arm') 166 167 168# Reference for memory map and interrupt number 169# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 170# Chapter 4: Programmer's Reference 171class RealViewPBX(RealView): --- 180 unchanged lines hidden (view full) --- 352 pciconfig = PciConfigAll(size='256MB') 353 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 354 InterruptLine=1, InterruptPin=1) 355 356 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 357 InterruptLine=2, InterruptPin=2) 358 359
360 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'))	360 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 361 conf_table_reported = False)
361 rtc = PL031(pio_addr=0x1C170000, int_num=36) 362 363 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 364 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 365 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 366 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 367 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 368 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 369 aaci_fake = AmbaFake(pio_addr=0x1C040000) 370 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 371 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 372 mmc_fake = AmbaFake(pio_addr=0x1c050000) 373 374 def setupBootLoader(self, mem_bus, cur_sys, loc):	362 rtc = PL031(pio_addr=0x1C170000, int_num=36) 363 364 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 365 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 366 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 367 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 368 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 369 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 370 aaci_fake = AmbaFake(pio_addr=0x1C040000) 371 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 372 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 373 mmc_fake = AmbaFake(pio_addr=0x1c050000) 374 375 def setupBootLoader(self, mem_bus, cur_sys, loc):
375 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))	376 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 377 conf_table_reported = False)
376 self.nvmem.port = mem_bus.master 377 cur_sys.boot_loader = loc('boot_emm.arm') 378 cur_sys.atags_addr = 0x80000100 379 380 # Attach I/O devices that are on chip and also set the appropriate 381 # ranges for the bridge 382 def attachOnChipIO(self, bus, bridge): 383 self.gic.pio = bus.master --- 49 unchanged lines hidden ---	378 self.nvmem.port = mem_bus.master 379 cur_sys.boot_loader = loc('boot_emm.arm') 380 cur_sys.atags_addr = 0x80000100 381 382 # Attach I/O devices that are on chip and also set the appropriate 383 # ranges for the bridge 384 def attachOnChipIO(self, bus, bridge): 385 self.gic.pio = bus.master --- 49 unchanged lines hidden ---