| RealView.py (9525:0587c8983d47) | RealView.py (9646:7a0c51f14095) |
|---|---|
| 1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138class Pl111(AmbaDmaDevice): 139 type = 'Pl111' 140 cxx_header = "dev/arm/pl111.hh" 141 pixel_clock = Param.Clock('24MHz', "Pixel clock") 142 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 143 amba_id = 0x00141111 144 | 1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138class Pl111(AmbaDmaDevice): 139 type = 'Pl111' 140 cxx_header = "dev/arm/pl111.hh" 141 pixel_clock = Param.Clock('24MHz', "Pixel clock") 142 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 143 amba_id = 0x00141111 144 |
| 145class HDLcd(AmbaDmaDevice): 146 type = 'HDLcd' 147 cxx_header = "dev/arm/hdlcd.hh" 148 pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 149 "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 150 "default up to 165MHz)") 151 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 152 "display") 153 amba_id = 0x00141000 154 |
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| 145class RealView(Platform): 146 type = 'RealView' 147 cxx_header = "dev/arm/realview.hh" 148 system = Param.System(Parent.any, "system") 149 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 150 mem_start_addr = Param.Addr(0, "Start address of main memory") 151 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 152 --- 175 unchanged lines hidden (view full) --- 328 pci_cfg_base = 0x30000000 329 uart = Pl011(pio_addr=0x1c090000, int_num=37) 330 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 331 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 332 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 333 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 334 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 335 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) | 155class RealView(Platform): 156 type = 'RealView' 157 cxx_header = "dev/arm/realview.hh" 158 system = Param.System(Parent.any, "system") 159 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 160 mem_start_addr = Param.Addr(0, "Start address of main memory") 161 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 162 --- 175 unchanged lines hidden (view full) --- 338 pci_cfg_base = 0x30000000 339 uart = Pl011(pio_addr=0x1c090000, int_num=37) 340 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 341 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 342 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 343 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 344 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 345 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) |
| 346 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) |
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| 336 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 337 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 338 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 339 io_shift = 2, ctrl_offset = 2, Command = 0x1, 340 BAR0 = 0x1C1A0000, BAR0Size = '256B', 341 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 342 BAR0LegacyIO = True, BAR1LegacyIO = True) 343 --- 27 unchanged lines hidden (view full) --- 371 cur_sys.boot_loader = loc('boot_emm.arm') 372 cur_sys.atags_addr = 0x80000100 373 374 # Attach I/O devices that are on chip and also set the appropriate 375 # ranges for the bridge 376 def attachOnChipIO(self, bus, bridge): 377 self.gic.pio = bus.master 378 self.local_cpu_timer.pio = bus.master | 347 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 348 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 349 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 350 io_shift = 2, ctrl_offset = 2, Command = 0x1, 351 BAR0 = 0x1C1A0000, BAR0Size = '256B', 352 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 353 BAR0LegacyIO = True, BAR1LegacyIO = True) 354 --- 27 unchanged lines hidden (view full) --- 382 cur_sys.boot_loader = loc('boot_emm.arm') 383 cur_sys.atags_addr = 0x80000100 384 385 # Attach I/O devices that are on chip and also set the appropriate 386 # ranges for the bridge 387 def attachOnChipIO(self, bus, bridge): 388 self.gic.pio = bus.master 389 self.local_cpu_timer.pio = bus.master |
| 390 self.hdlcd.dma = bus.slave |
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| 379 # Bridge ranges based on excluding what is part of on-chip I/O 380 # (gic, a9scu) 381 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), | 391 # Bridge ranges based on excluding what is part of on-chip I/O 392 # (gic, a9scu) 393 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), |
| 394 AddrRange(0x2B000000, size='4MB'), |
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| 382 AddrRange(0x30000000, size='256MB'), 383 AddrRange(0x40000000, size='512MB'), 384 AddrRange(0x18000000, size='64MB'), 385 AddrRange(0x1C000000, size='64MB')] 386 387 # Attach I/O devices to specified bus object. Can't do this 388 # earlier, since the bus object itself is typically defined at the 389 # System level. 390 def attachIO(self, bus): 391 self.uart.pio = bus.master 392 self.realview_io.pio = bus.master 393 self.timer0.pio = bus.master 394 self.timer1.pio = bus.master 395 self.clcd.pio = bus.master 396 self.clcd.dma = bus.slave | 395 AddrRange(0x30000000, size='256MB'), 396 AddrRange(0x40000000, size='512MB'), 397 AddrRange(0x18000000, size='64MB'), 398 AddrRange(0x1C000000, size='64MB')] 399 400 # Attach I/O devices to specified bus object. Can't do this 401 # earlier, since the bus object itself is typically defined at the 402 # System level. 403 def attachIO(self, bus): 404 self.uart.pio = bus.master 405 self.realview_io.pio = bus.master 406 self.timer0.pio = bus.master 407 self.timer1.pio = bus.master 408 self.clcd.pio = bus.master 409 self.clcd.dma = bus.slave |
| 410 self.hdlcd.pio = bus.master |
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| 397 self.kmi0.pio = bus.master 398 self.kmi1.pio = bus.master 399 self.cf_ctrl.pio = bus.master 400 self.cf_ctrl.dma = bus.slave 401 self.cf_ctrl.config = bus.master 402 self.rtc.pio = bus.master 403 bus.use_default_range = True 404 self.vram.port = bus.master --- 19 unchanged lines hidden --- | 411 self.kmi0.pio = bus.master 412 self.kmi1.pio = bus.master 413 self.cf_ctrl.pio = bus.master 414 self.cf_ctrl.dma = bus.slave 415 self.cf_ctrl.config = bus.master 416 self.rtc.pio = bus.master 417 bus.use_default_range = True 418 self.vram.port = bus.master --- 19 unchanged lines hidden --- |