RealView.py (9000:6c2381ecdfbc) | RealView.py (9052:acd6ffe55960) |
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1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 303 unchanged lines hidden (view full) --- 312 self.ssp_fake.pio = bus.master 313 self.sci_fake.pio = bus.master 314 self.aaci_fake.pio = bus.master 315 self.mmc_fake.pio = bus.master 316 self.rtc_fake.pio = bus.master 317 self.flash_fake.pio = bus.master 318 self.smcreg_fake.pio = bus.master 319 | 1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 303 unchanged lines hidden (view full) --- 312 self.ssp_fake.pio = bus.master 313 self.sci_fake.pio = bus.master 314 self.aaci_fake.pio = bus.master 315 self.mmc_fake.pio = bus.master 316 self.rtc_fake.pio = bus.master 317 self.flash_fake.pio = bus.master 318 self.smcreg_fake.pio = bus.master 319 |
320class VExpress_ELT(RealView): 321 max_mem_size = '2GB' 322 pci_cfg_base = 0xD0000000 323 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 324 uart = Pl011(pio_addr=0xFF009000, int_num=121) 325 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 326 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 327 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 328 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 329 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 330 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 331 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 332 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 333 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 334 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 335 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 336 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 337 a9scu = A9SCU(pio_addr=0xE0200000) 338 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 339 io_shift = 2, ctrl_offset = 2, Command = 0x1, 340 BAR0 = 0xFF01A000, BAR0Size = '256B', 341 BAR1 = 0xFF01A100, BAR1Size = '4096B', 342 BAR0LegacyIO = True, BAR1LegacyIO = True) 343 344 pciconfig = PciConfigAll() 345 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 346 InterruptLine=1, InterruptPin=1) 347 348 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 349 InterruptLine=2, InterruptPin=2) 350 351 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 352 dmac_fake = AmbaFake(pio_addr=0xE0020000) 353 uart1_fake = AmbaFake(pio_addr=0xE000A000) 354 uart2_fake = AmbaFake(pio_addr=0xE000B000) 355 uart3_fake = AmbaFake(pio_addr=0xE000C000) 356 smc_fake = AmbaFake(pio_addr=0xEC000000) 357 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 358 watchdog_fake = AmbaFake(pio_addr=0xE0010000) 359 aaci_fake = AmbaFake(pio_addr=0xFF004000) 360 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 361 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 362 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 363 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 364 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 365 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 366 367 368 # Attach I/O devices that are on chip and also set the appropriate 369 # ranges for the bridge 370 def attachOnChipIO(self, bus, bridge): 371 self.gic.pio = bus.master 372 self.a9scu.pio = bus.master 373 self.local_cpu_timer.pio = bus.master 374 # Bridge ranges based on excluding what is part of on-chip I/O 375 # (gic, a9scu) 376 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 377 AddrRange(self.l2x0_fake.pio_addr, Addr.max)] 378 379 # Attach I/O devices to specified bus object. Can't do this 380 # earlier, since the bus object itself is typically defined at the 381 # System level. 382 def attachIO(self, bus): 383 self.elba_uart.pio = bus.master 384 self.uart.pio = bus.master 385 self.realview_io.pio = bus.master 386 self.v2m_timer0.pio = bus.master 387 self.v2m_timer1.pio = bus.master 388 self.elba_timer0.pio = bus.master 389 self.elba_timer1.pio = bus.master 390 self.clcd.pio = bus.master 391 self.clcd.dma = bus.slave 392 self.kmi0.pio = bus.master 393 self.kmi1.pio = bus.master 394 self.elba_kmi0.pio = bus.master 395 self.elba_kmi1.pio = bus.master 396 self.cf_ctrl.pio = bus.master 397 self.cf_ctrl.config = bus.master 398 self.cf_ctrl.dma = bus.slave 399 self.ide.pio = bus.master 400 self.ide.config = bus.master 401 self.ide.dma = bus.slave 402 self.ethernet.pio = bus.master 403 self.ethernet.config = bus.master 404 self.ethernet.dma = bus.slave 405 self.pciconfig.pio = bus.default 406 bus.use_default_range = True 407 408 self.l2x0_fake.pio = bus.master 409 self.dmac_fake.pio = bus.master 410 self.uart1_fake.pio = bus.master 411 self.uart2_fake.pio = bus.master 412 self.uart3_fake.pio = bus.master 413 self.smc_fake.pio = bus.master 414 self.sp810_fake.pio = bus.master 415 self.watchdog_fake.pio = bus.master 416 self.aaci_fake.pio = bus.master 417 self.elba_aaci_fake.pio = bus.master 418 self.mmc_fake.pio = bus.master 419 self.rtc_fake.pio = bus.master 420 self.spsc_fake.pio = bus.master 421 self.lan_fake.pio = bus.master 422 self.usb_fake.pio = bus.master 423 424 | |
425class VExpress_EMM(RealView): 426 mem_start_addr = '2GB' 427 max_mem_size = '2GB' | 320class VExpress_EMM(RealView): 321 mem_start_addr = '2GB' 322 max_mem_size = '2GB' |
323 pci_cfg_base = 0x30000000 |
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428 uart = Pl011(pio_addr=0x1c090000, int_num=37) 429 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 430 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000) 431 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 432 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz') 433 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz') 434 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 435 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 436 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45) 437 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 438 io_shift = 2, ctrl_offset = 2, Command = 0x1, 439 BAR0 = 0x1C1A0000, BAR0Size = '256B', 440 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 441 BAR0LegacyIO = True, BAR1LegacyIO = True) | 324 uart = Pl011(pio_addr=0x1c090000, int_num=37) 325 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 326 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000) 327 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 328 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz') 329 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz') 330 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 331 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 332 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45) 333 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 334 io_shift = 2, ctrl_offset = 2, Command = 0x1, 335 BAR0 = 0x1C1A0000, BAR0Size = '256B', 336 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 337 BAR0LegacyIO = True, BAR1LegacyIO = True) |
338 339 pciconfig = PciConfigAll(size='256MB') 340 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 341 InterruptLine=1, InterruptPin=1) 342 343 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 344 InterruptLine=2, InterruptPin=2) 345 346 |
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442 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 443 zero = True) 444 rtc = PL031(pio_addr=0x1C170000, int_num=36) 445 446 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 447 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 448 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 449 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) --- 36 unchanged lines hidden (view full) --- 486 self.kmi0.pio = bus.master 487 self.kmi1.pio = bus.master 488 self.cf_ctrl.pio = bus.master 489 self.cf_ctrl.dma = bus.slave 490 self.cf_ctrl.config = bus.master 491 self.rtc.pio = bus.master 492 bus.use_default_range = True 493 self.vram.port = bus.master | 347 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 348 zero = True) 349 rtc = PL031(pio_addr=0x1C170000, int_num=36) 350 351 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 352 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 353 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 354 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) --- 36 unchanged lines hidden (view full) --- 391 self.kmi0.pio = bus.master 392 self.kmi1.pio = bus.master 393 self.cf_ctrl.pio = bus.master 394 self.cf_ctrl.dma = bus.slave 395 self.cf_ctrl.config = bus.master 396 self.rtc.pio = bus.master 397 bus.use_default_range = True 398 self.vram.port = bus.master |
399 self.ide.pio = bus.master 400 self.ide.config = bus.master 401 self.ide.dma = bus.slave 402 self.ethernet.pio = bus.master 403 self.ethernet.config = bus.master 404 self.ethernet.dma = bus.slave 405 self.pciconfig.pio = bus.default |
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494 495 self.l2x0_fake.pio = bus.master 496 self.uart1_fake.pio = bus.master 497 self.uart2_fake.pio = bus.master 498 self.uart3_fake.pio = bus.master 499 self.sp810_fake.pio = bus.master 500 self.watchdog_fake.pio = bus.master 501 self.aaci_fake.pio = bus.master 502 self.lan_fake.pio = bus.master 503 self.usb_fake.pio = bus.master 504 self.mmc_fake.pio = bus.master 505 | 406 407 self.l2x0_fake.pio = bus.master 408 self.uart1_fake.pio = bus.master 409 self.uart2_fake.pio = bus.master 410 self.uart3_fake.pio = bus.master 411 self.sp810_fake.pio = bus.master 412 self.watchdog_fake.pio = bus.master 413 self.aaci_fake.pio = bus.master 414 self.lan_fake.pio = bus.master 415 self.usb_fake.pio = bus.master 416 self.mmc_fake.pio = bus.master 417 |