RealView.py (13167:258a04d4c20b) | RealView.py (13504:5a01198080fa) |
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1# Copyright (c) 2009-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 310 unchanged lines hidden (view full) --- 319 if isinstance(obj, SimObject): 320 node.append(obj.generateDeviceTree(state)) 321 322 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 323 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 324 325 yield node 326 | 1# Copyright (c) 2009-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 310 unchanged lines hidden (view full) --- 319 if isinstance(obj, SimObject): 320 node.append(obj.generateDeviceTree(state)) 321 322 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 323 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 324 325 yield node 326 |
327class VGic(PioDevice): 328 type = 'VGic' 329 cxx_header = "dev/arm/vgic.hh" 330 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 331 platform = Param.Platform(Parent.any, "Platform this device is part of.") 332 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 333 hv_addr = Param.Addr(0, "Address for hv control") 334 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 335 # The number of list registers is not currently configurable at runtime. 336 ppint = Param.UInt32("HV maintenance interrupt number") 337 338 def generateDeviceTree(self, state): 339 gic = self.gic.unproxy(self) 340 341 node = FdtNode("interrupt-controller") 342 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 343 "arm,cortex-a9-gic"]) 344 node.append(FdtPropertyWords("#interrupt-cells", [3])) 345 node.append(FdtPropertyWords("#address-cells", [0])) 346 node.append(FdtProperty("interrupt-controller")) 347 348 regs = ( 349 state.addrCells(gic.dist_addr) + 350 state.sizeCells(0x1000) + 351 state.addrCells(gic.cpu_addr) + 352 state.sizeCells(0x1000) + 353 state.addrCells(self.hv_addr) + 354 state.sizeCells(0x2000) + 355 state.addrCells(self.vcpu_addr) + 356 state.sizeCells(0x2000) ) 357 358 node.append(FdtPropertyWords("reg", regs)) 359 node.append(FdtPropertyWords("interrupts", 360 [1, int(self.ppint)-16, 0xf04])) 361 362 node.appendPhandle(gic) 363 364 yield node 365 | |
366class AmbaFake(AmbaPioDevice): 367 type = 'AmbaFake' 368 cxx_header = "dev/arm/amba_fake.hh" 369 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 370 amba_id = 0; 371 372class Pl011(Uart): 373 type = 'Pl011' --- 737 unchanged lines hidden --- | 327class AmbaFake(AmbaPioDevice): 328 type = 'AmbaFake' 329 cxx_header = "dev/arm/amba_fake.hh" 330 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 331 amba_id = 0; 332 333class Pl011(Uart): 334 type = 'Pl011' --- 737 unchanged lines hidden --- |