RealView.py (12472:3cbae56f402d) | RealView.py (12474:31aaa43d1401) |
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1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 104 unchanged lines hidden (view full) --- 113class GenericArmPciHost(GenericPciHost): 114 type = 'GenericArmPciHost' 115 cxx_header = "dev/arm/pci_host.hh" 116 117 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 118 int_base = Param.Unsigned("PCI interrupt base") 119 int_count = Param.Unsigned("Maximum number of interrupts used by this host") 120 | 1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 104 unchanged lines hidden (view full) --- 113class GenericArmPciHost(GenericPciHost): 114 type = 'GenericArmPciHost' 115 cxx_header = "dev/arm/pci_host.hh" 116 117 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 118 int_base = Param.Unsigned("PCI interrupt base") 119 int_count = Param.Unsigned("Maximum number of interrupts used by this host") 120 |
121 def generateDeviceTree(self, state): 122 local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 123 intterrupt_cells = 1 124 125 node = FdtNode("pci") 126 127 if int(self.conf_device_bits) == 8: 128 node.appendCompatible("pci-host-cam-generic") 129 elif int(self.conf_device_bits) == 12: 130 node.appendCompatible("pci-host-ecam-generic") 131 else: 132 m5.fatal("No compatibility string for the set conf_device_width") 133 134 node.append(FdtPropertyStrings("device_type", ["pci"])) 135 136 # Cell sizes of child nodes/peripherals 137 node.append(local_state.addrCellsProperty()) 138 node.append(local_state.sizeCellsProperty()) 139 node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 140 # PCI address for CPU 141 node.append(FdtPropertyWords("reg", 142 state.addrCells(self.conf_base) + 143 state.sizeCells(self.conf_size) )) 144 145 # Ranges mapping 146 # For now some of this is hard coded, because the PCI module does not 147 # have a proper full understanding of the memory map, but adapting the 148 # PCI module is beyond the scope of what I'm trying to do here. 149 # Values are taken from the VExpress_GEM5_V1 platform. 150 ranges = [] 151 # Pio address range 152 ranges += self.pciFdtAddr(space=1, addr=0) 153 ranges += state.addrCells(self.pci_pio_base) 154 ranges += local_state.sizeCells(0x10000) # Fixed size 155 156 # AXI memory address range 157 ranges += self.pciFdtAddr(space=2, addr=0) 158 ranges += state.addrCells(0x40000000) # Fixed offset 159 ranges += local_state.sizeCells(0x40000000) # Fixed size 160 node.append(FdtPropertyWords("ranges", ranges)) 161 162 if str(self.int_policy) == 'ARM_PCI_INT_DEV': 163 int_phandle = state.phandle(self._parent.unproxy(self).gic) 164 # Interrupt mapping 165 interrupts = [] 166 for i in range(int(self.int_count)): 167 interrupts += self.pciFdtAddr(device=i, addr=0) + \ 168 [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 169 170 node.append(FdtPropertyWords("interrupt-map", interrupts)) 171 172 int_count = int(self.int_count) 173 if int_count & (int_count - 1): 174 fatal("PCI interrupt count should be power of 2") 175 176 intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 177 node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 178 else: 179 m5.fatal("Unsupported PCI interrupt policy " + 180 "for Device Tree generation") 181 182 node.append(FdtProperty("dma-coherent")) 183 184 yield node 185 |
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121class RealViewCtrl(BasicPioDevice): 122 type = 'RealViewCtrl' 123 cxx_header = "dev/arm/rv_ctrl.hh" 124 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 125 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 126 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 127 128 def generateDeviceTree(self, state): --- 999 unchanged lines hidden --- | 186class RealViewCtrl(BasicPioDevice): 187 type = 'RealViewCtrl' 188 cxx_header = "dev/arm/rv_ctrl.hh" 189 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 190 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 191 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 192 193 def generateDeviceTree(self, state): --- 999 unchanged lines hidden --- |