RealView.py (11296:fe89fe1d1869) RealView.py (11297:d1f8610cdffd)
1# Copyright (c) 2009-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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266 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
267
268class RealView(Platform):
269 type = 'RealView'
270 cxx_header = "dev/arm/realview.hh"
271 system = Param.System(Parent.any, "system")
272 _mem_regions = [(Addr(0), Addr('256MB'))]
273
1# Copyright (c) 2009-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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266 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
267
268class RealView(Platform):
269 type = 'RealView'
270 cxx_header = "dev/arm/realview.hh"
271 system = Param.System(Parent.any, "system")
272 _mem_regions = [(Addr(0), Addr('256MB'))]
273
274 def _on_chip_devices(self):
275 return []
276
277 def _off_chip_devices(self):
278 return []
279
280 _off_chip_ranges = []
281
282 def _attach_io(self, devices, bus):
283 for d in devices:
284 if hasattr(d, "pio"):
285 d.pio = bus.master
286 if hasattr(d, "dma"):
287 d.dma = bus.slave
288
289 def _attach_clk(self, devices, clkdomain):
290 for d in devices:
291 if hasattr(d, "clk_domain"):
292 d.clk_domain = clkdomain
293
274 def attachPciDevices(self):
275 pass
276
277 def enableMSIX(self):
278 pass
279
280 def onChipIOClkDomain(self, clkdomain):
294 def attachPciDevices(self):
295 pass
296
297 def enableMSIX(self):
298 pass
299
300 def onChipIOClkDomain(self, clkdomain):
281 pass
301 self._attach_clk(self._on_chip_devices(), clkdomain)
282
283 def offChipIOClkDomain(self, clkdomain):
302
303 def offChipIOClkDomain(self, clkdomain):
284 pass
304 self._attach_clk(self._off_chip_devices(), clkdomain)
285
305
306 def attachOnChipIO(self, bus, bridge=None):
307 self._attach_io(self._on_chip_devices(), bus)
308 if bridge:
309 bridge.ranges = self._off_chip_ranges
310
311 def attachIO(self, bus):
312 self._attach_io(self._off_chip_devices(), bus)
313
314
286 def setupBootLoader(self, mem_bus, cur_sys, loc):
287 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
288 conf_table_reported = False)
289 self.nvmem.port = mem_bus.master
290 cur_sys.boot_loader = loc('boot.arm')
291 cur_sys.atags_addr = 0x100
292 cur_sys.load_addr_mask = 0xfffffff
293 cur_sys.load_offset = 0

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711 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
712 self.nvmem.port = mem_bus.master
713 cur_sys.boot_loader = loc('boot_emm.arm64')
714 cur_sys.atags_addr = 0x8000000
715 cur_sys.load_addr_mask = 0xfffffff
716 cur_sys.load_offset = 0x80000000
717
718
315 def setupBootLoader(self, mem_bus, cur_sys, loc):
316 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
317 conf_table_reported = False)
318 self.nvmem.port = mem_bus.master
319 cur_sys.boot_loader = loc('boot.arm')
320 cur_sys.atags_addr = 0x100
321 cur_sys.load_addr_mask = 0xfffffff
322 cur_sys.load_offset = 0

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740 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
741 self.nvmem.port = mem_bus.master
742 cur_sys.boot_loader = loc('boot_emm.arm64')
743 cur_sys.atags_addr = 0x8000000
744 cur_sys.load_addr_mask = 0xfffffff
745 cur_sys.load_offset = 0x80000000
746
747
748class VExpress_GEM5_V1(RealView):
749 """
750The VExpress gem5 memory map is loosely based on a modified
751Versatile Express RS1 memory map.
752
753The gem5 platform has been designed to implement a subset of the
754original Versatile Express RS1 memory map. Off-chip peripherals should,
755when possible, adhere to the Versatile Express memory map. Non-PCI
756off-chip devices that are gem5-specific should live in the CS5 memory
757space to avoid conflicts with existing devices that we might want to
758model in the future. Such devices should normally have interrupts in
759the gem5-specific SPI range.
760
761On-chip peripherals are loosely modeled after the ARM CoreTile Express
762A15x2 A7x3 memory and interrupt map. In particular, the GIC and
763Generic Timer have the same interrupt lines and base addresses. Other
764on-chip devices are gem5 specific.
765
766Unlike the original Versatile Express RS2 extended platform, gem5 implements a
767large contigious DRAM space, without aliases or holes, starting at the
7682GiB boundary. This means that PCI memory is limited to 1GiB.
769
770Memory map:
771 0x00000000-0x03ffffff: Boot memory (CS0)
772 0x04000000-0x07ffffff: Reserved
773 0x08000000-0x0bffffff: Reserved (CS0 alias)
774 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
775 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
776 0x10000000-0x1000ffff: gem5 energy controller
777
778 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
779 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
780 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
781 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
782 0x1c060000-0x1c06ffff: KMI0 (keyboard)
783 0x1c070000-0x1c07ffff: KMI1 (mouse)
784 0x1c090000-0x1c09ffff: UART0
785 0x1c0a0000-0x1c0affff: UART1 (reserved)
786 0x1c0b0000-0x1c0bffff: UART2 (reserved)
787 0x1c0c0000-0x1c0cffff: UART3 (reserved)
788 0x1c170000-0x1c17ffff: RTC
789
790 0x20000000-0x3fffffff: On-chip peripherals:
791 0x2b000000-0x2b00ffff: HDLCD
792
793 0x2c001000-0x2c001fff: GIC (distributor)
794 0x2c002000-0x2c0020ff: GIC (CPU interface)
795 0x2c004000-0x2c005fff: vGIC (HV)
796 0x2c006000-0x2c007fff: vGIC (VCPU)
797 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
798
799 0x2d000000-0x2d00ffff: GPU (reserved)
800
801 0x2f000000-0x2fffffff: PCI IO space
802 0x30000000-0x3fffffff: PCI config space
803
804 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
805
806 0x80000000-X: DRAM
807
808Interrupts:
809 0- 15: Software generated interrupts (SGIs)
810 16- 31: On-chip private peripherals (PPIs)
811 25 : vgic
812 26 : generic_timer (hyp)
813 27 : generic_timer (virt)
814 28 : Reserved (Legacy FIQ)
815 29 : generic_timer (phys, sec)
816 30 : generic_timer (phys, non-sec)
817 31 : Reserved (Legacy IRQ)
818 32- 95: Mother board peripherals (SPIs)
819 32 : Reserved (SP805)
820 33 : Reserved (IOFPGA SW int)
821 34-35: Reserved (SP804)
822 36 : RTC
823 37-40: uart0-uart3
824 41-42: Reserved (PL180)
825 43 : Reserved (AACI)
826 44-45: kmi0-kmi1
827 46 : Reserved (CLCD)
828 47 : Reserved (Ethernet)
829 48 : Reserved (USB)
830 95-255: On-chip interrupt sources (we use these for
831 gem5-specific devices, SPIs)
832 95 : HDLCD
833 96- 98: GPU (reserved)
834 100-103: PCI
835 256-319: MSI frame 0 (gem5-specific, SPIs)
836 320-511: Unused
837
838 """
839
840 # Everything above 2GiB is memory
841 _mem_regions = [(Addr('2GB'), Addr('510GB'))]
842
843 _off_chip_ranges = [
844 # CS1-CS5
845 AddrRange(0x0c000000, 0x1fffffff),
846 # External AXI interface (PCI)
847 AddrRange(0x2f000000, 0x7fffffff),
848 ]
849
850 # Platform control device (off-chip)
851 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
852 idreg=0x02250000, pio_addr=0x1c010000)
853 mcc = VExpressMCC()
854 dcc = CoreTile2A15DCC()
855
856 ### On-chip devices ###
857 gic = Pl390(dist_addr=0x2c001000, cpu_addr=0x2c002000, it_lines=512)
858 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
859 gicv2m = Gicv2m()
860 gicv2m.frames = [
861 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
862 ]
863
864 generic_timer = GenericTimer(int_phys=29, int_virt=27)
865
866 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
867 pio_addr=0x2b000000, int_num=95)
868
869 def _on_chip_devices(self):
870 return [
871 self.gic, self.vgic, self.gicv2m,
872 self.hdlcd,
873 self.generic_timer,
874 ]
875
876 ### Off-chip devices ###
877 uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
878
879 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
880 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
881
882 rtc = PL031(pio_addr=0x1c170000, int_num=36)
883
884 ### gem5-specific off-chip devices ###
885 pci_host = GenericArmPciHost(
886 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
887 pci_pio_base=0x2f000000,
888 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
889
890 energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
891
892
893 def _off_chip_devices(self):
894 return [
895 self.realview_io,
896 self.uart0,
897 self.kmi0, self.kmi1,
898 self.rtc,
899 self.pci_host,
900 self.energy_ctrl,
901 ]
902
903 def attachPciDevice(self, device, bus):
904 device.host = self.pci_host
905 device.pio = bus.master
906 device.dma = bus.slave
907
908 def setupBootLoader(self, mem_bus, cur_sys, loc):
909 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'))
910 self.nvmem.port = mem_bus.master
911 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
912 cur_sys.atags_addr = 0x8000000
913 cur_sys.load_addr_mask = 0xfffffff
914 cur_sys.load_offset = 0x80000000