| RealView.py (11237:2d5d847aab27) | RealView.py (11244:a2af58a06c4e) |
|---|---|
| 1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 31 unchanged lines hidden (view full) --- 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice | 1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 31 unchanged lines hidden (view full) --- 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice |
| 48from Pci import PciConfigAll | 48from PciHost import * |
| 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl --- 193 unchanged lines hidden (view full) --- 250 251 pxl_clk = Param.ClockDomain("Pixel clock source") 252 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 253 254class RealView(Platform): 255 type = 'RealView' 256 cxx_header = "dev/arm/realview.hh" 257 system = Param.System(Parent.any, "system") | 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl --- 193 unchanged lines hidden (view full) --- 250 251 pxl_clk = Param.ClockDomain("Pixel clock source") 252 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 253 254class RealView(Platform): 255 type = 'RealView' 256 cxx_header = "dev/arm/realview.hh" 257 system = Param.System(Parent.any, "system") |
| 258 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 259 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 260 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 261 " be compatible with the pci-generic-host or the legacy host bridge?") | |
| 262 _mem_regions = [(Addr(0), Addr('256MB'))] 263 264 def attachPciDevices(self): 265 pass 266 267 def enableMSIX(self): 268 pass 269 --- 17 unchanged lines hidden (view full) --- 287# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 288# Chapter 4: Programmer's Reference 289class RealViewPBX(RealView): 290 uart = Pl011(pio_addr=0x10009000, int_num=44) 291 realview_io = RealViewCtrl(pio_addr=0x10000000) 292 mcc = VExpressMCC() 293 dcc = CoreTile2A15DCC() 294 gic = Pl390() | 258 _mem_regions = [(Addr(0), Addr('256MB'))] 259 260 def attachPciDevices(self): 261 pass 262 263 def enableMSIX(self): 264 pass 265 --- 17 unchanged lines hidden (view full) --- 283# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 284# Chapter 4: Programmer's Reference 285class RealViewPBX(RealView): 286 uart = Pl011(pio_addr=0x10009000, int_num=44) 287 realview_io = RealViewCtrl(pio_addr=0x10000000) 288 mcc = VExpressMCC() 289 dcc = CoreTile2A15DCC() 290 gic = Pl390() |
| 291 pci_host = GenericPciHost( 292 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 293 pci_pio_base=0) |
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| 295 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 296 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 297 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 298 clcd = Pl111(pio_addr=0x10020000, int_num=55) 299 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 300 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 301 a9scu = A9SCU(pio_addr=0x1f000000) 302 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, --- 48 unchanged lines hidden (view full) --- 351 self.local_cpu_timer.clk_domain = clkdomain 352 353 # Attach I/O devices to specified bus object. Can't do this 354 # earlier, since the bus object itself is typically defined at the 355 # System level. 356 def attachIO(self, bus): 357 self.uart.pio = bus.master 358 self.realview_io.pio = bus.master | 294 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 295 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 296 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 297 clcd = Pl111(pio_addr=0x10020000, int_num=55) 298 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 299 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 300 a9scu = A9SCU(pio_addr=0x1f000000) 301 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, --- 48 unchanged lines hidden (view full) --- 350 self.local_cpu_timer.clk_domain = clkdomain 351 352 # Attach I/O devices to specified bus object. Can't do this 353 # earlier, since the bus object itself is typically defined at the 354 # System level. 355 def attachIO(self, bus): 356 self.uart.pio = bus.master 357 self.realview_io.pio = bus.master |
| 358 self.pci_host.pio = bus.master |
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| 359 self.timer0.pio = bus.master 360 self.timer1.pio = bus.master 361 self.clcd.pio = bus.master 362 self.clcd.dma = bus.slave 363 self.kmi0.pio = bus.master 364 self.kmi1.pio = bus.master 365 self.cf_ctrl.pio = bus.master | 359 self.timer0.pio = bus.master 360 self.timer1.pio = bus.master 361 self.clcd.pio = bus.master 362 self.clcd.dma = bus.slave 363 self.kmi0.pio = bus.master 364 self.kmi1.pio = bus.master 365 self.cf_ctrl.pio = bus.master |
| 366 self.cf_ctrl.config = bus.master | |
| 367 self.cf_ctrl.dma = bus.slave 368 self.dmac_fake.pio = bus.master 369 self.uart1_fake.pio = bus.master 370 self.uart2_fake.pio = bus.master 371 self.uart3_fake.pio = bus.master 372 self.smc_fake.pio = bus.master 373 self.sp810_fake.pio = bus.master 374 self.watchdog_fake.pio = bus.master --- 91 unchanged lines hidden (view full) --- 466 self.l2x0_fake.clk_domain = clkdomain 467 468 # Attach I/O devices to specified bus object. Can't do this 469 # earlier, since the bus object itself is typically defined at the 470 # System level. 471 def attachIO(self, bus): 472 self.uart.pio = bus.master 473 self.realview_io.pio = bus.master | 366 self.cf_ctrl.dma = bus.slave 367 self.dmac_fake.pio = bus.master 368 self.uart1_fake.pio = bus.master 369 self.uart2_fake.pio = bus.master 370 self.uart3_fake.pio = bus.master 371 self.smc_fake.pio = bus.master 372 self.sp810_fake.pio = bus.master 373 self.watchdog_fake.pio = bus.master --- 91 unchanged lines hidden (view full) --- 465 self.l2x0_fake.clk_domain = clkdomain 466 467 # Attach I/O devices to specified bus object. Can't do this 468 # earlier, since the bus object itself is typically defined at the 469 # System level. 470 def attachIO(self, bus): 471 self.uart.pio = bus.master 472 self.realview_io.pio = bus.master |
| 473 self.pci_host.pio = bus.master |
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| 474 self.timer0.pio = bus.master 475 self.timer1.pio = bus.master 476 self.clcd.pio = bus.master 477 self.clcd.dma = bus.slave 478 self.kmi0.pio = bus.master 479 self.kmi1.pio = bus.master 480 self.dmac_fake.pio = bus.master 481 self.uart1_fake.pio = bus.master --- 40 unchanged lines hidden (view full) --- 522 self.mmc_fake.clk_domain = clkdomain 523 self.rtc.clk_domain = clkdomain 524 self.flash_fake.clk_domain = clkdomain 525 self.smcreg_fake.clk_domain = clkdomain 526 self.energy_ctrl.clk_domain = clkdomain 527 528class VExpress_EMM(RealView): 529 _mem_regions = [(Addr('2GB'), Addr('2GB'))] | 474 self.timer0.pio = bus.master 475 self.timer1.pio = bus.master 476 self.clcd.pio = bus.master 477 self.clcd.dma = bus.slave 478 self.kmi0.pio = bus.master 479 self.kmi1.pio = bus.master 480 self.dmac_fake.pio = bus.master 481 self.uart1_fake.pio = bus.master --- 40 unchanged lines hidden (view full) --- 522 self.mmc_fake.clk_domain = clkdomain 523 self.rtc.clk_domain = clkdomain 524 self.flash_fake.clk_domain = clkdomain 525 self.smcreg_fake.clk_domain = clkdomain 526 self.energy_ctrl.clk_domain = clkdomain 527 528class VExpress_EMM(RealView): 529 _mem_regions = [(Addr('2GB'), Addr('2GB'))] |
| 530 pci_cfg_base = 0x30000000 | |
| 531 uart = Pl011(pio_addr=0x1c090000, int_num=37) 532 realview_io = RealViewCtrl( 533 proc_id0=0x14000000, proc_id1=0x14000000, 534 idreg=0x02250000, pio_addr=0x1C010000) 535 mcc = VExpressMCC() 536 dcc = CoreTile2A15DCC() 537 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) | 530 uart = Pl011(pio_addr=0x1c090000, int_num=37) 531 realview_io = RealViewCtrl( 532 proc_id0=0x14000000, proc_id1=0x14000000, 533 idreg=0x02250000, pio_addr=0x1C010000) 534 mcc = VExpressMCC() 535 dcc = CoreTile2A15DCC() 536 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) |
| 537 pci_host = GenericPciHost( 538 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 539 pci_pio_base=0) |
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| 538 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 539 generic_timer = GenericTimer(int_phys=29, int_virt=27) 540 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 541 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 542 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 543 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 544 pio_addr=0x2b000000, int_num=117, 545 workaround_swap_rb=True) 546 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 547 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 548 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 549 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 550 io_shift = 2, ctrl_offset = 2, Command = 0x1, 551 BAR0 = 0x1C1A0000, BAR0Size = '256B', 552 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 553 BAR0LegacyIO = True, BAR1LegacyIO = True) 554 | 540 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 541 generic_timer = GenericTimer(int_phys=29, int_virt=27) 542 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 543 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 544 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 545 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 546 pio_addr=0x2b000000, int_num=117, 547 workaround_swap_rb=True) 548 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 549 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 550 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 551 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 552 io_shift = 2, ctrl_offset = 2, Command = 0x1, 553 BAR0 = 0x1C1A0000, BAR0Size = '256B', 554 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 555 BAR0LegacyIO = True, BAR1LegacyIO = True) 556 |
| 555 pciconfig = PciConfigAll(size='256MB') | |
| 556 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 557 conf_table_reported = False) 558 rtc = PL031(pio_addr=0x1C170000, int_num=36) 559 560 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 561 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 562 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 563 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) --- 55 unchanged lines hidden (view full) --- 619 self.hdlcd.clk_domain = clkdomain 620 self.vgic.clk_domain = clkdomain 621 622 # Attach I/O devices to specified bus object. Done here 623 # as the specified bus to connect to may not always be fixed. 624 def attachIO(self, bus): 625 self.uart.pio = bus.master 626 self.realview_io.pio = bus.master | 557 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 558 conf_table_reported = False) 559 rtc = PL031(pio_addr=0x1C170000, int_num=36) 560 561 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 562 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 563 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 564 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) --- 55 unchanged lines hidden (view full) --- 620 self.hdlcd.clk_domain = clkdomain 621 self.vgic.clk_domain = clkdomain 622 623 # Attach I/O devices to specified bus object. Done here 624 # as the specified bus to connect to may not always be fixed. 625 def attachIO(self, bus): 626 self.uart.pio = bus.master 627 self.realview_io.pio = bus.master |
| 628 self.pci_host.pio = bus.master |
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| 627 self.timer0.pio = bus.master 628 self.timer1.pio = bus.master 629 self.clcd.pio = bus.master 630 self.clcd.dma = bus.slave 631 self.hdlcd.pio = bus.master 632 self.kmi0.pio = bus.master 633 self.kmi1.pio = bus.master 634 self.cf_ctrl.pio = bus.master 635 self.cf_ctrl.dma = bus.slave | 629 self.timer0.pio = bus.master 630 self.timer1.pio = bus.master 631 self.clcd.pio = bus.master 632 self.clcd.dma = bus.slave 633 self.hdlcd.pio = bus.master 634 self.kmi0.pio = bus.master 635 self.kmi1.pio = bus.master 636 self.cf_ctrl.pio = bus.master 637 self.cf_ctrl.dma = bus.slave |
| 636 self.cf_ctrl.config = bus.master | |
| 637 self.rtc.pio = bus.master | 638 self.rtc.pio = bus.master |
| 638 bus.use_default_range = True | |
| 639 self.vram.port = bus.master | 639 self.vram.port = bus.master |
| 640 self.pciconfig.pio = bus.default | |
| 641 642 self.l2x0_fake.pio = bus.master 643 self.uart1_fake.pio = bus.master 644 self.uart2_fake.pio = bus.master 645 self.uart3_fake.pio = bus.master 646 self.sp810_fake.pio = bus.master 647 self.watchdog_fake.pio = bus.master 648 self.aaci_fake.pio = bus.master 649 self.lan_fake.pio = bus.master 650 self.usb_fake.pio = bus.master 651 self.mmc_fake.pio = bus.master 652 self.energy_ctrl.pio = bus.master 653 654 # Try to attach the I/O if it exists 655 try: 656 self.ide.pio = bus.master | 640 641 self.l2x0_fake.pio = bus.master 642 self.uart1_fake.pio = bus.master 643 self.uart2_fake.pio = bus.master 644 self.uart3_fake.pio = bus.master 645 self.sp810_fake.pio = bus.master 646 self.watchdog_fake.pio = bus.master 647 self.aaci_fake.pio = bus.master 648 self.lan_fake.pio = bus.master 649 self.usb_fake.pio = bus.master 650 self.mmc_fake.pio = bus.master 651 self.energy_ctrl.pio = bus.master 652 653 # Try to attach the I/O if it exists 654 try: 655 self.ide.pio = bus.master |
| 657 self.ide.config = bus.master | |
| 658 self.ide.dma = bus.slave 659 self.ethernet.pio = bus.master | 656 self.ide.dma = bus.slave 657 self.ethernet.pio = bus.master |
| 660 self.ethernet.config = bus.master | |
| 661 self.ethernet.dma = bus.slave 662 except: 663 pass 664 665 # Set the clock domain for IO objects that are considered 666 # to be "far" away from the cores. 667 def offChipIOClkDomain(self, clkdomain): 668 self.uart.clk_domain = clkdomain 669 self.realview_io.clk_domain = clkdomain 670 self.timer0.clk_domain = clkdomain 671 self.timer1.clk_domain = clkdomain 672 self.clcd.clk_domain = clkdomain 673 self.kmi0.clk_domain = clkdomain 674 self.kmi1.clk_domain = clkdomain 675 self.cf_ctrl.clk_domain = clkdomain 676 self.rtc.clk_domain = clkdomain 677 self.vram.clk_domain = clkdomain | 658 self.ethernet.dma = bus.slave 659 except: 660 pass 661 662 # Set the clock domain for IO objects that are considered 663 # to be "far" away from the cores. 664 def offChipIOClkDomain(self, clkdomain): 665 self.uart.clk_domain = clkdomain 666 self.realview_io.clk_domain = clkdomain 667 self.timer0.clk_domain = clkdomain 668 self.timer1.clk_domain = clkdomain 669 self.clcd.clk_domain = clkdomain 670 self.kmi0.clk_domain = clkdomain 671 self.kmi1.clk_domain = clkdomain 672 self.cf_ctrl.clk_domain = clkdomain 673 self.rtc.clk_domain = clkdomain 674 self.vram.clk_domain = clkdomain |
| 678 self.pciconfig.clk_domain = clkdomain | |
| 679 680 self.l2x0_fake.clk_domain = clkdomain 681 self.uart1_fake.clk_domain = clkdomain 682 self.uart2_fake.clk_domain = clkdomain 683 self.uart3_fake.clk_domain = clkdomain 684 self.sp810_fake.clk_domain = clkdomain 685 self.watchdog_fake.clk_domain = clkdomain 686 self.aaci_fake.clk_domain = clkdomain 687 self.lan_fake.clk_domain = clkdomain 688 self.usb_fake.clk_domain = clkdomain 689 self.mmc_fake.clk_domain = clkdomain 690 self.energy_ctrl.clk_domain = clkdomain 691 692class VExpress_EMM64(VExpress_EMM): | 675 676 self.l2x0_fake.clk_domain = clkdomain 677 self.uart1_fake.clk_domain = clkdomain 678 self.uart2_fake.clk_domain = clkdomain 679 self.uart3_fake.clk_domain = clkdomain 680 self.sp810_fake.clk_domain = clkdomain 681 self.watchdog_fake.clk_domain = clkdomain 682 self.aaci_fake.clk_domain = clkdomain 683 self.lan_fake.clk_domain = clkdomain 684 self.usb_fake.clk_domain = clkdomain 685 self.mmc_fake.clk_domain = clkdomain 686 self.energy_ctrl.clk_domain = clkdomain 687 688class VExpress_EMM64(VExpress_EMM): |
| 693 pci_io_base = 0x2f000000 694 pci_cfg_gen_offsets = True | |
| 695 # Three memory regions are specified totalling 512GB 696 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 697 (Addr('512GB'), Addr('480GB'))] | 689 # Three memory regions are specified totalling 512GB 690 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 691 (Addr('512GB'), Addr('480GB'))] |
| 692 pci_host = GenericPciHost( 693 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 694 pci_pio_base=0x2f000000) 695 |
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| 698 def setupBootLoader(self, mem_bus, cur_sys, loc): 699 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 700 self.nvmem.port = mem_bus.master 701 cur_sys.boot_loader = loc('boot_emm.arm64') 702 cur_sys.atags_addr = 0x8000000 703 cur_sys.load_addr_mask = 0xfffffff 704 cur_sys.load_offset = 0x80000000 705 706 | 696 def setupBootLoader(self, mem_bus, cur_sys, loc): 697 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 698 self.nvmem.port = mem_bus.master 699 cur_sys.boot_loader = loc('boot_emm.arm64') 700 cur_sys.atags_addr = 0x8000000 701 cur_sys.load_addr_mask = 0xfffffff 702 cur_sys.load_offset = 0x80000000 703 704 |