| RealView.py (10397:3064e1beeb49) | RealView.py (10780:46070443051e) |
|---|---|
| 1# Copyright (c) 2009-2014 ARM Limited | 1# Copyright (c) 2009-2015 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 494 unchanged lines hidden (view full) --- 504 self.nvmem.port = mem_bus.master 505 cur_sys.boot_loader = loc('boot_emm.arm') 506 cur_sys.atags_addr = 0x8000000 507 cur_sys.load_addr_mask = 0xfffffff 508 cur_sys.load_offset = 0x80000000 509 510 # Attach I/O devices that are on chip and also set the appropriate 511 # ranges for the bridge | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 494 unchanged lines hidden (view full) --- 504 self.nvmem.port = mem_bus.master 505 cur_sys.boot_loader = loc('boot_emm.arm') 506 cur_sys.atags_addr = 0x8000000 507 cur_sys.load_addr_mask = 0xfffffff 508 cur_sys.load_offset = 0x80000000 509 510 # Attach I/O devices that are on chip and also set the appropriate 511 # ranges for the bridge |
| 512 def attachOnChipIO(self, bus, bridge): 513 self.gic.pio = bus.master 514 self.local_cpu_timer.pio = bus.master 515 if hasattr(self, "gicv2m"): 516 self.gicv2m.pio = bus.master 517 self.hdlcd.dma = bus.slave 518 # Bridge ranges based on excluding what is part of on-chip I/O 519 # (gic, a9scu) 520 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 521 AddrRange(0x2B000000, size='4MB'), 522 AddrRange(0x30000000, size='256MB'), 523 AddrRange(0x40000000, size='512MB'), 524 AddrRange(0x18000000, size='64MB'), 525 AddrRange(0x1C000000, size='64MB')] 526 self.vgic.pio = bus.master | 512 def attachOnChipIO(self, bus, bridge=None): 513 self.gic.pio = bus.master 514 self.vgic.pio = bus.master 515 self.local_cpu_timer.pio = bus.master 516 if hasattr(self, "gicv2m"): 517 self.gicv2m.pio = bus.master 518 self.hdlcd.dma = bus.slave 519 if bridge: 520 # Bridge ranges based on excluding what is part of on-chip I/O 521 # (gic, a9scu) 522 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 523 AddrRange(0x2B000000, size='4MB'), 524 AddrRange(0x30000000, size='256MB'), 525 AddrRange(0x40000000, size='512MB'), 526 AddrRange(0x18000000, size='64MB'), 527 AddrRange(0x1C000000, size='64MB')] |
| 527 528 529 # Set the clock domain for IO objects that are considered 530 # to be "close" to the cores. 531 def onChipIOClkDomain(self, clkdomain): 532 self.gic.clk_domain = clkdomain 533 if hasattr(self, "gicv2m"): 534 self.gicv2m.clk_domain = clkdomain --- 88 unchanged lines hidden --- | 528 529 530 # Set the clock domain for IO objects that are considered 531 # to be "close" to the cores. 532 def onChipIOClkDomain(self, clkdomain): 533 self.gic.clk_domain = clkdomain 534 if hasattr(self, "gicv2m"): 535 self.gicv2m.clk_domain = clkdomain --- 88 unchanged lines hidden --- |